stats.txt revision 9265
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000011 # Number of seconds simulated 49265SAli.Saidi@ARM.comsim_ticks 10738000 # Number of ticks simulated 59265SAli.Saidi@ARM.comfinal_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79265SAli.Saidi@ARM.comhost_inst_rate 30784 # Simulator instruction rate (inst/s) 89265SAli.Saidi@ARM.comhost_op_rate 38403 # Simulator op (including micro ops) rate (op/s) 99265SAli.Saidi@ARM.comhost_tick_rate 71910456 # Simulator tick rate (ticks/s) 109265SAli.Saidi@ARM.comhost_mem_usage 227312 # Number of bytes of host memory used 119265SAli.Saidi@ARM.comhost_seconds 0.15 # Real time elapsed on the host 129265SAli.Saidi@ARM.comsim_insts 4596 # Number of instructions simulated 139265SAli.Saidi@ARM.comsim_ops 5734 # Number of ops (including micro ops) simulated 149265SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 159265SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory 169265SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 25728 # Number of bytes read from this memory 179265SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 189265SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 199265SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 209265SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory 219265SAli.Saidi@ARM.comsystem.physmem.num_reads::total 402 # Number of read requests responded to by this memory 229265SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) 239265SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) 249265SAli.Saidi@ARM.comsystem.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) 259265SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) 269265SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) 279265SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) 289265SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) 299265SAli.Saidi@ARM.comsystem.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) 308317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 318317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 328317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 338317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 348317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 358317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 367860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 377860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 387860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 398317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 418317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 428317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 438317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 448317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 468317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 478317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 487860SN/Asystem.cpu.dtb.hits 0 # DTB hits 497860SN/Asystem.cpu.dtb.misses 0 # DTB misses 508317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 518317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 528317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 538317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 548317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 558317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 568317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 578317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 588317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 598317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 608317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 618317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 628317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 638317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 648317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 658317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 668317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 678317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 688317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 698317SN/Asystem.cpu.itb.hits 0 # DTB hits 708317SN/Asystem.cpu.itb.misses 0 # DTB misses 718317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 728317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 739265SAli.Saidi@ARM.comsystem.cpu.numCycles 21477 # number of cpu cycles simulated 748317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 758317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 769265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2491 # Number of BP lookups 779265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted 789265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect 799265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups 809265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 692 # Number of BTB hits 818317SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 829265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. 839265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. 849265SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss 859265SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 12142 # Number of instructions fetch has processed 869265SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2491 # Number of branches that fetch encountered 879265SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken 889265SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked 899265SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing 909265SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked 919079SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 929265SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1931 # Number of cache lines fetched 939265SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed 949265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) 959265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) 969265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) 977860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 989265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) 999265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) 1009265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) 1019265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) 1029265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) 1039265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) 1049265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) 1059265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) 1069265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) 1077860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1087860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1097860SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1109265SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) 1119265SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle 1129265SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle 1139265SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle 1149265SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked 1159265SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2402 # Number of cycles decode is running 1169265SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking 1179265SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing 1189265SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch 1199096Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 1209265SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode 1219096Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode 1229265SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing 1239265SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle 1249265SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking 1259265SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst 1269265SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2220 # Number of cycles rename is running 1279265SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking 1289265SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename 1299096Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full 1309265SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full 1319265SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed 1329265SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made 1339265SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups 1349265SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups 1359265SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 1369265SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing 1379265SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 49 # count of serializing insts renamed 1389265SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed 1399265SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 766 # count of insts added to the skid buffer 1409265SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. 1419265SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. 1429265SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. 1439265SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. 1449265SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) 1459265SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ 1469265SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8841 # Number of instructions issued 1479265SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued 1489265SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling 1499265SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph 1509265SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 1519265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle 1529265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle 1539265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle 1548241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1559265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle 1569265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle 1579265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle 1589265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle 1599265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle 1609265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle 1619265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle 1629265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle 1639265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle 1648241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1658241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1668241SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1679265SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle 1688317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1699265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available 1709265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available 1719265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available 1729265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available 1739265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available 1749265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available 1759265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available 1769265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available 1779265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available 1789265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available 1799265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available 1809265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available 1819265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available 1829265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available 1839265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available 1849265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available 1859265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available 1869265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available 1879265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available 1889265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available 1899265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available 1909265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available 1919265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available 1929265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available 1939265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available 1949265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available 1959265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available 1969265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available 1979265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available 1989265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available 1999265SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available 2008317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2018317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2028317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 2039265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued 2049265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued 2059265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued 2069265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued 2079265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued 2089265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued 2099265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued 2109265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued 2119265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued 2129265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued 2139265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued 2149265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued 2159265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued 2169265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued 2179265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued 2189265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued 2199265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued 2209265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued 2219265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued 2229265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued 2239265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued 2249265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued 2259265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued 2269265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued 2279265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued 2289265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued 2299265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued 2309265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued 2319265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued 2329265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued 2339265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued 2348317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2358317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2369265SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8841 # Type of FU issued 2379265SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.411650 # Inst issue rate 2389265SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 213 # FU busy when requested 2399265SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) 2409265SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads 2419265SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes 2429265SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses 2438632SN/Asystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 2449265SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 2458317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 2469265SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses 2478632SN/Asystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 2489265SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores 2498317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2509265SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed 2519096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 2528844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 2539265SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed 2548317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2558317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2568632SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2578317SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2588317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2599265SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing 2609265SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking 2619265SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking 2629265SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ 2639265SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch 2649265SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions 2659265SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions 2669265SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions 2679265SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall 2689096Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall 2698844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 2709265SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly 2719265SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly 2729265SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute 2739265SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions 2749265SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed 2759265SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute 2768317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2779079SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 2789265SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3250 # number of memory reference insts executed 2799265SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1412 # Number of branches executed 2809265SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1169 # Number of stores executed 2819265SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.393211 # Inst execution rate 2829265SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit 2839265SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 8006 # cumulative count of insts written-back 2849265SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 3825 # num instructions producing a value 2859265SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 7724 # num instructions consuming a value 2868317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2879265SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.372771 # insts written-back per cycle 2889265SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back 2898317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2909265SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit 2919265SAli.Saidi@ARM.comsystem.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 2929265SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted 2939265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle 2949265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle 2959265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle 2968317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2979265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle 2989265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle 2999265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle 3009265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle 3019265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle 3029265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle 3039265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle 3049265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle 3059265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle 3068317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 3078317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 3088317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3099265SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle 3109265SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 4596 # Number of instructions committed 3119265SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed 3128317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3139265SAli.Saidi@ARM.comsystem.cpu.commit.refs 2140 # Number of memory references committed 3149265SAli.Saidi@ARM.comsystem.cpu.commit.loads 1201 # Number of loads committed 3158317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 3169265SAli.Saidi@ARM.comsystem.cpu.commit.branches 1008 # Number of branches committed 3178317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 3189265SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 4980 # Number of committed integer instructions. 3198317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 3209265SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached 3218317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3229265SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 23095 # The number of ROB reads 3239265SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 23459 # The number of ROB writes 3249265SAli.Saidi@ARM.comsystem.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself 3259265SAli.Saidi@ARM.comsystem.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling 3269265SAli.Saidi@ARM.comsystem.cpu.committedInsts 4596 # Number of Instructions Simulated 3279265SAli.Saidi@ARM.comsystem.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 3289265SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 4596 # Number of Instructions Simulated 3299265SAli.Saidi@ARM.comsystem.cpu.cpi 4.672977 # CPI: Cycles Per Instruction 3309265SAli.Saidi@ARM.comsystem.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads 3319265SAli.Saidi@ARM.comsystem.cpu.ipc 0.213996 # IPC: Instructions Per Cycle 3329265SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads 3339265SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 38788 # number of integer regfile reads 3349265SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 7902 # number of integer regfile writes 3358632SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 3369265SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 15082 # number of misc regfile reads 3379265SAli.Saidi@ARM.comsystem.cpu.misc_regfile_writes 26 # number of misc regfile writes 3389265SAli.Saidi@ARM.comsystem.cpu.icache.replacements 4 # number of replacements 3399265SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use 3409265SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1558 # Total number of references to valid blocks. 3419265SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. 3429265SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. 3438317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3449265SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor 3459265SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy 3469265SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy 3479265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits 3489265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits 3499265SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits 3509265SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits 3519265SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits 3529265SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1558 # number of overall hits 3539265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses 3549265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses 3559265SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses 3569265SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses 3579265SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses 3589265SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 373 # number of overall misses 3599265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles 3609265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles 3619265SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles 3629265SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles 3639265SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles 3649265SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles 3659265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) 3669265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) 3679265SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses 3689265SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses 3699265SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses 3709265SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses 3719265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses 3729265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses 3739265SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses 3749265SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses 3759265SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses 3769265SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses 3779265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency 3789265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency 3799265SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency 3809265SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency 3819265SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency 3829265SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency 3838317SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3848317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3858317SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3868317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3878983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3888983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3898317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3908317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3919265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 74 # number of ReadReq MSHR hits 3929265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 3939265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 74 # number of demand (read+write) MSHR hits 3949265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 3959265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 74 # number of overall MSHR hits 3969265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 74 # number of overall MSHR hits 3979265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses 3989265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses 3999265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses 4009265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses 4019265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses 4029265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses 4039265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10560500 # number of ReadReq MSHR miss cycles 4049265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 10560500 # number of ReadReq MSHR miss cycles 4059265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 10560500 # number of demand (read+write) MSHR miss cycles 4069265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 10560500 # number of demand (read+write) MSHR miss cycles 4079265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles 4089265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles 4099265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses 4109265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses 4119265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses 4129265SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses 4139265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses 4149265SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.154842 # mshr miss rate for overall accesses 4159265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35319.397993 # average ReadReq mshr miss latency 4169265SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35319.397993 # average ReadReq mshr miss latency 4179265SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency 4189265SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency 4199265SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency 4209265SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency 4218317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4228317SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4239265SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 86.954141 # Cycle average of tags in use 4249265SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2354 # Total number of references to valid blocks. 4259265SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. 4269265SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 15.905405 # Average number of references to valid blocks. 4278317SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4289265SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 86.954141 # Average occupied blocks per requestor 4299265SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.021229 # Average percentage of cache occupancy 4309265SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy 4319265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1727 # number of ReadReq hits 4329265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1727 # number of ReadReq hits 4339096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits 4349096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits 4359265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 4369265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 4379265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 4389265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 4399265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits 4409265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits 4419265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits 4429265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2329 # number of overall hits 4439265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 4449265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 4459096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses 4469096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses 4478835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 4488835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 4499265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses 4509265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses 4519265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses 4529265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 502 # number of overall misses 4539265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 7113500 # number of ReadReq miss cycles 4549265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 7113500 # number of ReadReq miss cycles 4559265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 12639500 # number of WriteReq miss cycles 4569265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 12639500 # number of WriteReq miss cycles 4578835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 4588835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles 4599265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 19753000 # number of demand (read+write) miss cycles 4609265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 19753000 # number of demand (read+write) miss cycles 4619265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 19753000 # number of overall miss cycles 4629265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles 4639265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) 4649265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) 4658835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 4668835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 4679265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 4689265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 4699265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 4709265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 4719265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2831 # number of demand (read+write) accesses 4729265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2831 # number of demand (read+write) accesses 4739265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2831 # number of overall (read+write) accesses 4749265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2831 # number of overall (read+write) accesses 4759265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.099583 # miss rate for ReadReq accesses 4769265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.099583 # miss rate for ReadReq accesses 4779096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses 4789096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses 4799265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 4809265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 4819265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.177323 # miss rate for demand accesses 4829265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.177323 # miss rate for demand accesses 4839265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses 4849265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses 4859265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency 4869265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency 4879265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency 4889265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency 4898835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 4909055Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency 4919265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency 4929265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency 4939265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency 4949265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency 4958317SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4968317SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4978317SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4988317SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4998983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5008983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5018317SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 5028317SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 5039265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits 5049265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 5059096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits 5069096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits 5078835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 5088835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 5099265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits 5109265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits 5119265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits 5129265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits 5139265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 5149265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 5158835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 5168835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 5179265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 5189265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 5199265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 5209265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses 5219265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3692500 # number of ReadReq MSHR miss cycles 5229265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3692500 # number of ReadReq MSHR miss cycles 5239265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1708000 # number of WriteReq MSHR miss cycles 5249265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1708000 # number of WriteReq MSHR miss cycles 5259265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5400500 # number of demand (read+write) MSHR miss cycles 5269265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5400500 # number of demand (read+write) MSHR miss cycles 5279265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5400500 # number of overall MSHR miss cycles 5289265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5400500 # number of overall MSHR miss cycles 5299265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055266 # mshr miss rate for ReadReq accesses 5309265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055266 # mshr miss rate for ReadReq accesses 5318835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 5329055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 5339265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for demand accesses 5349265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.052278 # mshr miss rate for demand accesses 5359265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for overall accesses 5369265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.052278 # mshr miss rate for overall accesses 5379265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34834.905660 # average ReadReq mshr miss latency 5389265SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34834.905660 # average ReadReq mshr miss latency 5399265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40666.666667 # average WriteReq mshr miss latency 5409265SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40666.666667 # average WriteReq mshr miss latency 5419265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36489.864865 # average overall mshr miss latency 5429265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency 5439265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36489.864865 # average overall mshr miss latency 5449265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 36489.864865 # average overall mshr miss latency 5458317SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5468317SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5479265SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 187.774695 # Cycle average of tags in use 5489265SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. 5499265SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 360 # Sample count of references to valid blocks. 5509265SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.108333 # Average number of references to valid blocks. 5518317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5529265SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 141.174021 # Average occupied blocks per requestor 5539265SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 46.600674 # Average occupied blocks per requestor 5549265SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy 5559265SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001422 # Average percentage of cache occupancy 5569265SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.005730 # Average percentage of cache occupancy 5579096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 5589265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 5599265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 5609096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 5619265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 5629265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 5639096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 5649265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 5659265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 39 # number of overall hits 5669265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses 5679265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 5689265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 366 # number of ReadReq misses 5698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 5708835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 5719265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 280 # number of demand (read+write) misses 5729265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses 5739265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 408 # number of demand (read+write) misses 5749265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 280 # number of overall misses 5759265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses 5769265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 408 # number of overall misses 5779265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10109500 # number of ReadReq miss cycles 5789265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3421000 # number of ReadReq miss cycles 5799265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 13530500 # number of ReadReq miss cycles 5809265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1660500 # number of ReadExReq miss cycles 5819265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1660500 # number of ReadExReq miss cycles 5829265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 10109500 # number of demand (read+write) miss cycles 5839265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 5081500 # number of demand (read+write) miss cycles 5849265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 15191000 # number of demand (read+write) miss cycles 5859265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 10109500 # number of overall miss cycles 5869265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 5081500 # number of overall miss cycles 5879265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 15191000 # number of overall miss cycles 5889265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 299 # number of ReadReq accesses(hits+misses) 5899265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 5909265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) 5918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 5928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 5939265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses 5949265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses 5959265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 5969265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses 5979265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses 5989265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 5999265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.936455 # miss rate for ReadReq accesses 6009265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 6019265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.903704 # miss rate for ReadReq accesses 6028835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6039055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6049265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.936455 # miss rate for demand accesses 6059265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.864865 # miss rate for demand accesses 6069265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.912752 # miss rate for demand accesses 6079265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.936455 # miss rate for overall accesses 6089265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.864865 # miss rate for overall accesses 6099265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.912752 # miss rate for overall accesses 6109265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36105.357143 # average ReadReq miss latency 6119265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39779.069767 # average ReadReq miss latency 6129265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 36968.579235 # average ReadReq miss latency 6139265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39535.714286 # average ReadExReq miss latency 6149265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 39535.714286 # average ReadExReq miss latency 6159265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency 6169265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency 6179265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37232.843137 # average overall miss latency 6189265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency 6199265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency 6209265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37232.843137 # average overall miss latency 6218317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6228317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6238317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6248317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6258983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6268983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6278317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6287860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6299096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 6308844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 6319096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 6329096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 6338844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 6349096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 6359096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 6368844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 6379096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 6389265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 6399265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 6409265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 360 # number of ReadReq MSHR misses 6418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 6428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 6439265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 6449265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses 6459265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 402 # number of demand (read+write) MSHR misses 6469265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 6479265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses 6489265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 402 # number of overall MSHR misses 6499265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9218000 # number of ReadReq MSHR miss cycles 6509265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3041500 # number of ReadReq MSHR miss cycles 6519265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 12259500 # number of ReadReq MSHR miss cycles 6529265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles 6539265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles 6549265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9218000 # number of demand (read+write) MSHR miss cycles 6559265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4569000 # number of demand (read+write) MSHR miss cycles 6569265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 13787000 # number of demand (read+write) MSHR miss cycles 6579265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9218000 # number of overall MSHR miss cycles 6589265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4569000 # number of overall MSHR miss cycles 6599265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 13787000 # number of overall MSHR miss cycles 6609265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for ReadReq accesses 6619265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.773585 # mshr miss rate for ReadReq accesses 6629265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888889 # mshr miss rate for ReadReq accesses 6638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6649055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6659265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for demand accesses 6669265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for demand accesses 6679265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.899329 # mshr miss rate for demand accesses 6689265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for overall accesses 6699265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for overall accesses 6709265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.899329 # mshr miss rate for overall accesses 6719265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33158.273381 # average ReadReq mshr miss latency 6729265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency 6739265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency 6749265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency 6759265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency 6769265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency 6779265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency 6789265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency 6799265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency 6809265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency 6819265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency 6827860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6837860SN/A 6847860SN/A---------- End Simulation Statistics ---------- 685