stats.txt revision 9079
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 38464SN/Asim_seconds 0.000010 # Number of seconds simulated 49079SAli.Saidi@ARM.comsim_ticks 10305000 # Number of ticks simulated 59079SAli.Saidi@ARM.comfinal_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79079SAli.Saidi@ARM.comhost_inst_rate 29768 # Simulator instruction rate (inst/s) 89079SAli.Saidi@ARM.comhost_op_rate 37142 # Simulator op (including micro ops) rate (op/s) 99079SAli.Saidi@ARM.comhost_tick_rate 66801597 # Simulator tick rate (ticks/s) 109079SAli.Saidi@ARM.comhost_mem_usage 232684 # Number of bytes of host memory used 119079SAli.Saidi@ARM.comhost_seconds 0.15 # Real time elapsed on the host 129079SAli.Saidi@ARM.comsim_insts 4591 # Number of instructions simulated 139079SAli.Saidi@ARM.comsim_ops 5729 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 159079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 25536 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 209079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory 219079SAli.Saidi@ARM.comsystem.physmem.num_reads::total 399 # Number of read requests responded to by this memory 229079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) 239079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) 249079SAli.Saidi@ARM.comsystem.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) 259079SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) 269079SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) 279079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) 289079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) 299079SAli.Saidi@ARM.comsystem.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) 308317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 318317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 328317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 338317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 348317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 358317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 367860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 377860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 387860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 398317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 418317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 428317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 438317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 448317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 468317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 478317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 487860SN/Asystem.cpu.dtb.hits 0 # DTB hits 497860SN/Asystem.cpu.dtb.misses 0 # DTB misses 508317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 518317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 528317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 538317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 548317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 558317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 568317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 578317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 588317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 598317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 608317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 618317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 628317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 638317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 648317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 658317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 668317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 678317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 688317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 698317SN/Asystem.cpu.itb.hits 0 # DTB hits 708317SN/Asystem.cpu.itb.misses 0 # DTB misses 718317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 728317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 739079SAli.Saidi@ARM.comsystem.cpu.numCycles 20611 # number of cpu cycles simulated 748317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 758317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 769079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2522 # Number of BP lookups 779079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted 789079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect 799079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups 809079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 669 # Number of BTB hits 818317SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 829079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. 839079SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. 849079SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss 859079SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 12809 # Number of instructions fetch has processed 869079SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2522 # Number of branches that fetch encountered 879079SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken 889079SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked 899079SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing 909079SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked 919079SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 929079SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1996 # Number of cache lines fetched 939079SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed 949079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) 959079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) 969079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) 977860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 989079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) 999079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) 1009079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) 1019079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) 1029079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) 1039079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) 1049079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) 1059079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) 1069079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) 1077860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1087860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1097860SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1109079SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) 1119079SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle 1129079SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle 1139079SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle 1149079SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked 1159079SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2573 # Number of cycles decode is running 1169079SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking 1179079SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing 1189079SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch 1199079SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 1209079SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode 1219079SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode 1229079SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing 1239079SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle 1249079SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking 1259079SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst 1269079SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2368 # Number of cycles rename is running 1278911SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking 1289079SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename 1299079SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 1309079SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full 1319079SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed 1329079SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made 1339079SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups 1349079SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups 1359079SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 1369079SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing 1379079SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 45 # count of serializing insts renamed 1388911SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed 1399079SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 627 # count of insts added to the skid buffer 1409079SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. 1419079SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. 1429079SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. 1439079SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. 1449079SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) 1459079SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ 1469079SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 9186 # Number of instructions issued 1479079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued 1489079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling 1499079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph 1509079SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed 1519079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle 1529079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle 1539079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle 1548241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1559079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle 1569079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle 1579079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle 1589079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle 1599079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle 1609079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle 1619079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle 1629079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle 1639079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle 1648241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1658241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1668241SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1679079SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle 1688317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1699079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available 1709079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available 1719079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available 1729079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available 1739079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available 1749079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available 1759079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available 1769079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available 1779079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available 1789079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available 1799079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available 1809079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available 1819079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available 1829079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available 1839079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available 1849079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available 1859079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available 1869079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available 1879079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available 1889079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available 1899079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available 1909079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available 1919079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available 1929079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available 1939079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available 1949079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available 1959079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available 1969079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available 1979079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available 1989079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available 1999079SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available 2008317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2018317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2028317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 2039079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued 2049079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued 2059079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued 2069079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued 2079079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued 2089079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued 2099079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued 2109079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued 2119079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued 2129079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued 2139079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued 2149079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued 2159079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued 2169079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued 2179079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued 2189079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued 2199079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued 2209079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued 2219079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued 2229079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued 2239079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued 2249079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued 2259079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued 2269079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued 2279079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued 2289079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued 2299079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued 2309079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued 2319079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued 2329079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued 2339079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued 2348317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2358317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2369079SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 9186 # Type of FU issued 2379079SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.445684 # Inst issue rate 2389079SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 217 # FU busy when requested 2399079SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) 2409079SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads 2419079SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes 2429079SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses 2438632SN/Asystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 2449079SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes 2458317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 2469079SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses 2478632SN/Asystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 2489079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores 2498317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2509079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed 2518317SN/Asystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 2528844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 2539079SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed 2548317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2558317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2568632SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2578317SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2588317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2599079SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing 2609079SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking 2618844SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking 2629079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ 2639079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch 2649079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions 2659079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions 2669079SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions 2678844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 2688317SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2698844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 2709079SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly 2719079SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly 2729079SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute 2739079SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions 2749079SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed 2759079SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute 2768317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2779079SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 2789079SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3377 # number of memory reference insts executed 2799079SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1400 # Number of branches executed 2809079SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1208 # Number of stores executed 2819079SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.423027 # Inst execution rate 2829079SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit 2839079SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 8236 # cumulative count of insts written-back 2849079SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 3901 # num instructions producing a value 2859079SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 7899 # num instructions consuming a value 2868317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2879079SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.399592 # insts written-back per cycle 2889079SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back 2898317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2909079SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions 2919079SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 5729 # The number of committed instructions 2929079SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit 2938632SN/Asystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 2949079SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted 2959079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle 2969079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle 2979079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle 2988317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2999079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle 3009079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle 3019079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle 3029079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle 3039079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle 3049079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle 3059079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle 3069079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle 3079079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle 3088317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 3098317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 3108317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3119079SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle 3129079SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 4591 # Number of instructions committed 3139079SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 3148317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3159079SAli.Saidi@ARM.comsystem.cpu.commit.refs 2138 # Number of memory references committed 3169079SAli.Saidi@ARM.comsystem.cpu.commit.loads 1200 # Number of loads committed 3178317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 3189079SAli.Saidi@ARM.comsystem.cpu.commit.branches 944 # Number of branches committed 3198317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 3209079SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 3218317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 3229079SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached 3238317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3249079SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 22509 # The number of ROB reads 3259079SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 24591 # The number of ROB writes 3269079SAli.Saidi@ARM.comsystem.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself 3279079SAli.Saidi@ARM.comsystem.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling 3289079SAli.Saidi@ARM.comsystem.cpu.committedInsts 4591 # Number of Instructions Simulated 3299079SAli.Saidi@ARM.comsystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 3309079SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 4591 # Number of Instructions Simulated 3319079SAli.Saidi@ARM.comsystem.cpu.cpi 4.489436 # CPI: Cycles Per Instruction 3329079SAli.Saidi@ARM.comsystem.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads 3339079SAli.Saidi@ARM.comsystem.cpu.ipc 0.222745 # IPC: Instructions Per Cycle 3349079SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads 3359079SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 40006 # number of integer regfile reads 3369079SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 8113 # number of integer regfile writes 3378632SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 3389079SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 15846 # number of misc regfile reads 3398317SN/Asystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 3409079SAli.Saidi@ARM.comsystem.cpu.icache.replacements 5 # number of replacements 3419079SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use 3429079SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1637 # Total number of references to valid blocks. 3438844SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 3449079SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. 3458317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3469079SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor 3479079SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy 3489079SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy 3499079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits 3509079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits 3519079SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits 3529079SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits 3539079SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits 3549079SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1637 # number of overall hits 3559079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses 3569079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses 3579079SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses 3589079SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses 3599079SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses 3609079SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 359 # number of overall misses 3619079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles 3629079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles 3639079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles 3649079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles 3659079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles 3669079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles 3679079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) 3689079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) 3699079SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses 3709079SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses 3719079SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses 3729079SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses 3739079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses 3749079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses 3759079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses 3769079SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses 3779079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses 3789079SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses 3799079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency 3809079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency 3819079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency 3829079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency 3839079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency 3849079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency 3858317SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3868317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3878317SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3888317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3898983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3908983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3918317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3928317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3939079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits 3949079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 3959079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits 3969079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits 3979079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits 3989079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits 3998844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 4008844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 4018844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 4028844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 4038844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 4048844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 4059079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles 4069079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles 4079079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles 4089079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles 4099079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles 4109079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles 4119079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses 4129079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses 4139079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses 4149079SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses 4159079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses 4169079SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses 4179079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency 4189079SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency 4199079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency 4209079SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency 4219079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency 4229079SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency 4238317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4248317SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4259079SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use 4269079SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. 4278844SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. 4289079SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. 4298317SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4309079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor 4319079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy 4329079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy 4339079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits 4349079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits 4358835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits 4368835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits 4378835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 4388835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 4398835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 4408835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 4419079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits 4429079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits 4439079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits 4449079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2425 # number of overall hits 4459079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses 4469079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses 4478835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses 4488835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses 4498835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 4508835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 4519079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses 4529079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses 4539079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses 4549079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 477 # number of overall misses 4559079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles 4569079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles 4579079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles 4589079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles 4598835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 4608835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles 4619079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles 4629079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles 4639079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles 4649079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles 4659079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) 4669079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) 4678835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 4688835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 4698835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 4708835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 4718835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 4728835SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 4739079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses 4749079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses 4759079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses 4769079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses 4779079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses 4789079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses 4798835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses 4809055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses 4818835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 4829055Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 4839079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses 4849079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses 4859079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses 4869079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses 4879079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency 4889079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency 4899079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency 4909079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency 4918835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 4929055Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency 4939079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency 4949079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency 4959079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency 4969079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency 4978317SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4988317SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4998317SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5008317SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 5018983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5028983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5038317SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 5048317SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 5059079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits 5069079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits 5078835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 5088835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 5098835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 5108835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 5119079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits 5129079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits 5139079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits 5149079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits 5158844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses 5168844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses 5178835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 5188835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 5198844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 5208844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses 5218844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 5228844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses 5239079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles 5249079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles 5259079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles 5269079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles 5279079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles 5289079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles 5299079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles 5309079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles 5319079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses 5329079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses 5338835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 5349055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 5359079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses 5369079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses 5379079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses 5389079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses 5399079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency 5409079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency 5419079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency 5429079SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency 5439079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency 5449079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency 5459079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency 5469079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency 5478317SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5488317SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5499079SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use 5509079SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. 5519079SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. 5529079SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. 5538317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5549079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor 5559079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor 5569079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy 5579079SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy 5588911SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy 5598844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 5609079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 5619079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits 5628844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 5639079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 5649079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits 5658844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 5669079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 5679079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 42 # number of overall hits 5688844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 5699079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 5709079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses 5718835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 5728835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 5738844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 5749079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 5759079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 5768844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 5779079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 5789079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 403 # number of overall misses 5799079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles 5809079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles 5819079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles 5829079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles 5839079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles 5849079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles 5859079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles 5869079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles 5879079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles 5889079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles 5899079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles 5908844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 5918844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) 5928844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) 5938835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 5948835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 5958844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 5968844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 5978844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses 5988844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 5998844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 6008844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses 6018844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses 6029079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses 6039079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses 6048835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6059055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6068844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses 6079079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses 6089079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses 6098844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses 6109079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses 6119079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses 6129079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency 6139079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency 6149079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency 6159079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency 6169079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency 6179079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency 6189079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency 6199079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency 6209079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency 6219079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency 6229079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency 6238317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6248317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6258317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6268317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6278983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6288983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6298317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6307860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6318844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 6328844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 6338844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 6348844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 6358844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 6368844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 6378844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 6389079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 6399079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses 6408835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 6418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 6428844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 6439079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses 6449079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses 6458844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 6469079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses 6479079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses 6489079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles 6499079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles 6509079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles 6519079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles 6529079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles 6539079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles 6549079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles 6559079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles 6569079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles 6579079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles 6589079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles 6598844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses 6609079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses 6619079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses 6628835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6639055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6648844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses 6659079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses 6669079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses 6678844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses 6689079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses 6699079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses 6709079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency 6719079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency 6729079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency 6739079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency 6749079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency 6759079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency 6769079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency 6779079SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency 6789079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency 6799079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency 6809079SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency 6817860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6827860SN/A 6837860SN/A---------- End Simulation Statistics ---------- 684