xref: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000010                       # Number of seconds simulated
sim_ticks                                    10303500                       # Number of ticks simulated
final_tick                                   10303500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  49511                       # Simulator instruction rate (inst/s)
host_op_rate                                    61757                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              110854808                       # Simulator tick rate (ticks/s)
host_mem_usage                                 229756                       # Number of bytes of host memory used
host_seconds                                     0.09                       # Real time elapsed on the host
sim_insts                                        4600                       # Number of instructions simulated
sim_ops                                          5739                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8000                       # Number of bytes read from this memory
system.physmem.bytes_read::total                25664                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   401                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1714368904                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            776435192                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              2490804096                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1714368904                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1714368904                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1714368904                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           776435192                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2490804096                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   13                       # Number of system calls
system.cpu.numCycles                            20608                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                     2552                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted               1875                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect                474                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups                  2008                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                      693                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                      237                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                  53                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles               6263                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                          13044                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                        2552                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches                930                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                          2846                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                    1780                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles                   1715                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            37                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                      2031                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                   304                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples              12075                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.376812                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.767860                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                     9229     76.43%     76.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                      246      2.04%     78.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                      197      1.63%     80.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                      227      1.88%     81.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                      225      1.86%     83.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                      278      2.30%     86.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                      120      0.99%     87.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                      130      1.08%     88.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                     1423     11.78%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total                12075                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.123835                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.632958                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                     6461                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles                  1883                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                      2624                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles                    61                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                   1046                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved                  445                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                   174                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts                  14512                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   583                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                   1046                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                     6744                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                     274                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles           1422                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                      2398                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles                   191                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts                  13646                       # Number of instructions processed by rename
system.cpu.rename.IQFullEvents                     14                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents                   155                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands               13298                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups                 62745                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups            61353                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              1392                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps                  5684                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                     7614                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                 44                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             42                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                       614                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads                 2865                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores                1803                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads                22                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores               17                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                      11802                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  52                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                      9165                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued               112                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined            5733                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined        16704                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             15                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples         12075                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.759006                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.446143                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0                8430     69.81%     69.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1                1334     11.05%     80.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2                 801      6.63%     87.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3                 552      4.57%     92.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4                 480      3.98%     96.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 289      2.39%     98.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 130      1.08%     99.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                  44      0.36%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                  15      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total           12075                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                       2      0.93%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                    150     69.77%     70.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                    63     29.30%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu                  5502     60.03%     60.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    7      0.08%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead                 2395     26.13%     86.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite                1258     13.73%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total                   9165                       # Type of FU issued
system.cpu.iq.rate                           0.444730                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                         215                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023459                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads              30696                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes             17588                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses         8151                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses                   9360                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads               60                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads         1664                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores          865                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                   1046                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                     169                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                    21                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts               11855                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts               180                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts                  2865                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts                 1803                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 40                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                     13                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect            104                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect          321                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts                  425                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts                  8667                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts                  2152                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts               498                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             1                       # number of nop insts executed
system.cpu.iew.exec_refs                         3351                       # number of memory reference insts executed
system.cpu.iew.exec_branches                     1406                       # Number of branches executed
system.cpu.iew.exec_stores                       1199                       # Number of stores executed
system.cpu.iew.exec_rate                     0.420565                       # Inst execution rate
system.cpu.iew.wb_sent                           8349                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                          8167                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                      3874                       # num instructions producing a value
system.cpu.iew.wb_consumers                      7832                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       0.396302                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.494637                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts           4600                       # The number of committed instructions
system.cpu.commit.commitCommittedOps             5739                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts            6115                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts               378                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples        11030                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.520308                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.336045                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0         8688     78.77%     78.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1         1103     10.00%     88.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2          433      3.93%     92.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3          253      2.29%     94.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4          182      1.65%     96.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5          178      1.61%     98.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6           56      0.51%     98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7           39      0.35%     99.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8           98      0.89%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total        11030                       # Number of insts commited each cycle
system.cpu.commit.committedInsts                 4600                       # Number of instructions committed
system.cpu.commit.committedOps                   5739                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                           2139                       # Number of memory references committed
system.cpu.commit.loads                          1201                       # Number of loads committed
system.cpu.commit.membars                          12                       # Number of memory barriers committed
system.cpu.commit.branches                        945                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                      4985                       # Number of committed integer instructions.
system.cpu.commit.function_calls                   82                       # Number of function calls committed.
system.cpu.commit.bw_lim_events                    98                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                        22629                       # The number of ROB reads
system.cpu.rob.rob_writes                       24771                       # The number of ROB writes
system.cpu.timesIdled                             177                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                            8533                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                        4600                       # Number of Instructions Simulated
system.cpu.committedOps                          5739                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total                  4600                       # Number of Instructions Simulated
system.cpu.cpi                               4.480000                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         4.480000                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.223214                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.223214                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                    39716                       # number of integer regfile reads
system.cpu.int_regfile_writes                    8038                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads                   16043                       # number of misc regfile reads
system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
system.cpu.icache.replacements                      2                       # number of replacements
system.cpu.icache.tagsinuse                151.737773                       # Cycle average of tags in use
system.cpu.icache.total_refs                     1665                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    296                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   5.625000                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     151.737773                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.074091                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.074091                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst         1665                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            1665                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          1665                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             1665                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         1665                       # number of overall hits
system.cpu.icache.overall_hits::total            1665                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          366                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           366                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          366                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            366                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          366                       # number of overall misses
system.cpu.icache.overall_misses::total           366                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     12617500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     12617500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     12617500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     12617500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     12617500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     12617500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         2031                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         2031                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         2031                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         2031                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         2031                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         2031                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.180207                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.180207                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.180207                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.180207                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.180207                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.180207                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 34474.043716                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 34474.043716                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           70                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           70                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           70                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          296                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          296                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          296                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          296                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          296                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          296                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      9833500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total      9833500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst      9833500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total      9833500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst      9833500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total      9833500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.145741                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.145741                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.145741                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.145741                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 87.257006                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     2425                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    149                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  16.275168                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data      87.257006                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.021303                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.021303                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         1796                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1796                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          609                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            609                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data          2405                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             2405                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         2405                       # number of overall hits
system.cpu.dcache.overall_hits::total            2405                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data          170                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total           170                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          304                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          304                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data          474                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            474                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          474                       # number of overall misses
system.cpu.dcache.overall_misses::total           474                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      5541500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      5541500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data     10844000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total     10844000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        76500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        76500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     16385500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     16385500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     16385500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     16385500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1966                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1966                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2879                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2879                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2879                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2879                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086470                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.086470                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.332968                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.332968                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.164641                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.164641                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.164641                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.164641                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38250                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38250                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 34568.565401                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 34568.565401                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           63                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          262                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          262                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          325                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          325                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          325                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          325                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          107                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          107                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           42                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          149                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          149                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          149                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3192000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      3192000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1501500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      1501500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4693500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      4693500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4693500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      4693500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054425                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054425                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051754                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.051754                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051754                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.051754                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        35750                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        35750                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        31500                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        31500                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        31500                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        31500                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               188.789311                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                      40                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   359                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.111421                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst    142.150350                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     46.638961                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.004338                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.001423                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.005761                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total             40                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst           20                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data           20                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total              40                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           20                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data           20                       # number of overall hits
system.cpu.l2cache.overall_hits::total             40                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          276                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          363                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           42                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          276                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          129                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           405                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          276                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          129                       # number of overall misses
system.cpu.l2cache.overall_misses::total          405                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      9475500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2999000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     12474500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1446500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      1446500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst      9475500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      4445500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     13921000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst      9475500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      4445500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     13921000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          296                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          107                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          403                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           42                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           42                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          296                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          149                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          445                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          296                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          149                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          445                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.932432                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.813084                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.900744                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.932432                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.865772                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.910112                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.932432                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.865772                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.910112                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           83                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          359                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          125                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          401                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          125                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          401                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      8590500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2612000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11202500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1315000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1315000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      8590500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3927000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     12517500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      8590500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3927000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     12517500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.775701                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.890819                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.838926                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.901124                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.838926                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.901124                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        31125                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        31125                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        31416                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        31125                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        31416                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------