stats.txt revision 8464
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 9834500 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 38040 # Simulator instruction rate (inst/s) 7host_tick_rate 65174027 # Simulator tick rate (ticks/s) 8host_mem_usage 253652 # Number of bytes of host memory used 9host_seconds 0.15 # Real time elapsed on the host 10sim_insts 5739 # Number of instructions simulated 11system.cpu.dtb.inst_hits 0 # ITB inst hits 12system.cpu.dtb.inst_misses 0 # ITB inst misses 13system.cpu.dtb.read_hits 0 # DTB read hits 14system.cpu.dtb.read_misses 0 # DTB read misses 15system.cpu.dtb.write_hits 0 # DTB write hits 16system.cpu.dtb.write_misses 0 # DTB write misses 17system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 18system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 22system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 23system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 24system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 25system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 26system.cpu.dtb.read_accesses 0 # DTB read accesses 27system.cpu.dtb.write_accesses 0 # DTB write accesses 28system.cpu.dtb.inst_accesses 0 # ITB inst accesses 29system.cpu.dtb.hits 0 # DTB hits 30system.cpu.dtb.misses 0 # DTB misses 31system.cpu.dtb.accesses 0 # DTB accesses 32system.cpu.itb.inst_hits 0 # ITB inst hits 33system.cpu.itb.inst_misses 0 # ITB inst misses 34system.cpu.itb.read_hits 0 # DTB read hits 35system.cpu.itb.read_misses 0 # DTB read misses 36system.cpu.itb.write_hits 0 # DTB write hits 37system.cpu.itb.write_misses 0 # DTB write misses 38system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 39system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 43system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 44system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 45system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 46system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 47system.cpu.itb.read_accesses 0 # DTB read accesses 48system.cpu.itb.write_accesses 0 # DTB write accesses 49system.cpu.itb.inst_accesses 0 # ITB inst accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 13 # Number of system calls 54system.cpu.numCycles 19670 # number of cpu cycles simulated 55system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57system.cpu.BPredUnit.lookups 2538 # Number of BP lookups 58system.cpu.BPredUnit.condPredicted 1884 # Number of conditional branches predicted 59system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect 60system.cpu.BPredUnit.BTBLookups 1886 # Number of BTB lookups 61system.cpu.BPredUnit.BTBHits 760 # Number of BTB hits 62system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 63system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. 64system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. 65system.cpu.fetch.icacheStallCycles 6290 # Number of cycles fetch is stalled on an Icache miss 66system.cpu.fetch.Insts 12764 # Number of instructions fetch has processed 67system.cpu.fetch.Branches 2538 # Number of branches that fetch encountered 68system.cpu.fetch.predictedBranches 1028 # Number of branches that fetch has predicted taken 69system.cpu.fetch.Cycles 2852 # Number of cycles fetch has run and was not squashing or blocked 70system.cpu.fetch.SquashCycles 1670 # Number of cycles fetch has spent squashing 71system.cpu.fetch.BlockedCycles 1030 # Number of cycles fetch has spent blocked 72system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 73system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps 74system.cpu.fetch.CacheLines 2054 # Number of cache lines fetched 75system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed 76system.cpu.fetch.rateDist::samples 11334 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::mean 1.423857 # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::stdev 2.772019 # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::0 8482 74.84% 74.84% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::1 284 2.51% 77.34% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::2 192 1.69% 79.04% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::3 246 2.17% 81.21% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::4 242 2.14% 83.34% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::5 324 2.86% 86.20% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::6 124 1.09% 87.29% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::7 120 1.06% 88.35% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::8 1320 11.65% 100.00% # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::total 11334 # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.branchRate 0.129029 # Number of branch fetches per cycle 94system.cpu.fetch.rate 0.648907 # Number of inst fetches per cycle 95system.cpu.decode.IdleCycles 6573 # Number of cycles decode is idle 96system.cpu.decode.BlockedCycles 1079 # Number of cycles decode is blocked 97system.cpu.decode.RunCycles 2654 # Number of cycles decode is running 98system.cpu.decode.UnblockCycles 60 # Number of cycles decode is unblocking 99system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing 100system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch 101system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction 102system.cpu.decode.DecodedInsts 14169 # Number of instructions handled by decode 103system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode 104system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing 105system.cpu.rename.IdleCycles 6862 # Number of cycles rename is idle 106system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking 107system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst 108system.cpu.rename.RunCycles 2422 # Number of cycles rename is running 109system.cpu.rename.UnblockCycles 183 # Number of cycles rename is unblocking 110system.cpu.rename.RenamedInsts 13321 # Number of instructions processed by rename 111system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full 112system.cpu.rename.RenamedOperands 12898 # Number of destination operands rename has renamed 113system.cpu.rename.RenameLookups 60750 # Number of register rename lookups that rename has made 114system.cpu.rename.int_rename_lookups 59430 # Number of integer rename lookups 115system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups 116system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed 117system.cpu.rename.UndoneMaps 7209 # Number of HB maps that are undone due to squashing 118system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 119system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed 120system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer 121system.cpu.memDep0.insertedLoads 2701 # Number of loads inserted to the mem dependence unit. 122system.cpu.memDep0.insertedStores 1759 # Number of stores inserted to the mem dependence unit. 123system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 124system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. 125system.cpu.iq.iqInstsAdded 11506 # Number of instructions added to the IQ (excludes non-spec) 126system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ 127system.cpu.iq.iqInstsIssued 9339 # Number of instructions issued 128system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued 129system.cpu.iq.iqSquashedInstsExamined 5207 # Number of squashed instructions iterated over during squash; mainly for profiling 130system.cpu.iq.iqSquashedOperandsExamined 14048 # Number of squashed operands that are examined and possibly removed from graph 131system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 132system.cpu.iq.issued_per_cycle::samples 11334 # Number of insts issued each cycle 133system.cpu.iq.issued_per_cycle::mean 0.823981 # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::stdev 1.484525 # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::0 7613 67.17% 67.17% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::1 1341 11.83% 79.00% # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::2 855 7.54% 86.54% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::3 564 4.98% 91.52% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::4 476 4.20% 95.72% # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::5 284 2.51% 98.23% # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::6 147 1.30% 99.52% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::7 42 0.37% 99.89% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::total 11334 # Number of insts issued each cycle 149system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 150system.cpu.iq.fu_full::IntAlu 6 2.79% 2.79% # attempts to use FU when none available 151system.cpu.iq.fu_full::IntMult 0 0.00% 2.79% # attempts to use FU when none available 152system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available 153system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available 154system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available 155system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available 156system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available 157system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available 158system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available 179system.cpu.iq.fu_full::MemRead 138 64.19% 66.98% # attempts to use FU when none available 180system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available 181system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 182system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 183system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 184system.cpu.iq.FU_type_0::IntAlu 5727 61.32% 61.32% # Type of FU issued 185system.cpu.iq.FU_type_0::IntMult 7 0.07% 61.40% # Type of FU issued 186system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued 187system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.40% # Type of FU issued 188system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.40% # Type of FU issued 189system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.40% # Type of FU issued 190system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.40% # Type of FU issued 191system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.40% # Type of FU issued 192system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.40% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.40% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.40% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.40% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.40% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.40% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.40% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.40% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.40% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.40% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.40% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.40% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.40% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.40% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.40% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.40% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.40% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.43% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued 213system.cpu.iq.FU_type_0::MemRead 2324 24.88% 86.32% # Type of FU issued 214system.cpu.iq.FU_type_0::MemWrite 1278 13.68% 100.00% # Type of FU issued 215system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 216system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 217system.cpu.iq.FU_type_0::total 9339 # Type of FU issued 218system.cpu.iq.rate 0.474784 # Inst issue rate 219system.cpu.iq.fu_busy_cnt 215 # FU busy when requested 220system.cpu.iq.fu_busy_rate 0.023022 # FU busy rate (busy events/executed inst) 221system.cpu.iq.int_inst_queue_reads 30256 # Number of integer instruction queue reads 222system.cpu.iq.int_inst_queue_writes 16705 # Number of integer instruction queue writes 223system.cpu.iq.int_inst_queue_wakeup_accesses 8361 # Number of integer instruction queue wakeup accesses 224system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads 225system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 226system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 227system.cpu.iq.int_alu_accesses 9514 # Number of integer alu accesses 228system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses 229system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores 230system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 231system.cpu.iew.lsq.thread0.squashedLoads 1500 # Number of loads squashed 232system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 233system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 234system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed 235system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 236system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 237system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 238system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 239system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 240system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing 241system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking 242system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking 243system.cpu.iew.iewDispatchedInsts 11534 # Number of instructions dispatched to IQ 244system.cpu.iew.iewDispSquashedInsts 218 # Number of squashed instructions skipped by dispatch 245system.cpu.iew.iewDispLoadInsts 2701 # Number of dispatched load instructions 246system.cpu.iew.iewDispStoreInsts 1759 # Number of dispatched store instructions 247system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 248system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 249system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 250system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 251system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly 252system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly 253system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute 254system.cpu.iew.iewExecutedInsts 8897 # Number of executed instructions 255system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed 256system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute 257system.cpu.iew.exec_swp 0 # number of swp insts executed 258system.cpu.iew.exec_nop 3 # number of nop insts executed 259system.cpu.iew.exec_refs 3351 # number of memory reference insts executed 260system.cpu.iew.exec_branches 1479 # Number of branches executed 261system.cpu.iew.exec_stores 1222 # Number of stores executed 262system.cpu.iew.exec_rate 0.452313 # Inst execution rate 263system.cpu.iew.wb_sent 8556 # cumulative count of insts sent to commit 264system.cpu.iew.wb_count 8377 # cumulative count of insts written-back 265system.cpu.iew.wb_producers 3980 # num instructions producing a value 266system.cpu.iew.wb_consumers 7830 # num instructions consuming a value 267system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 268system.cpu.iew.wb_rate 0.425877 # insts written-back per cycle 269system.cpu.iew.wb_fanout 0.508301 # average fanout of values written-back 270system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 271system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions 272system.cpu.commit.commitSquashedInsts 5640 # The number of squashed insts skipped by commit 273system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards 274system.cpu.commit.branchMispredicts 351 # The number of times a branch was mispredicted 275system.cpu.commit.committed_per_cycle::samples 10367 # Number of insts commited each cycle 276system.cpu.commit.committed_per_cycle::mean 0.553583 # Number of insts commited each cycle 277system.cpu.commit.committed_per_cycle::stdev 1.355703 # Number of insts commited each cycle 278system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 279system.cpu.commit.committed_per_cycle::0 8010 77.26% 77.26% # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::1 1098 10.59% 87.86% # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::2 433 4.18% 92.03% # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::3 284 2.74% 94.77% # Number of insts commited each cycle 283system.cpu.commit.committed_per_cycle::4 184 1.77% 96.55% # Number of insts commited each cycle 284system.cpu.commit.committed_per_cycle::5 168 1.62% 98.17% # Number of insts commited each cycle 285system.cpu.commit.committed_per_cycle::6 67 0.65% 98.81% # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::7 39 0.38% 99.19% # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::8 84 0.81% 100.00% # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::total 10367 # Number of insts commited each cycle 292system.cpu.commit.count 5739 # Number of instructions committed 293system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 294system.cpu.commit.refs 2139 # Number of memory references committed 295system.cpu.commit.loads 1201 # Number of loads committed 296system.cpu.commit.membars 12 # Number of memory barriers committed 297system.cpu.commit.branches 945 # Number of branches committed 298system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 299system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 300system.cpu.commit.function_calls 82 # Number of function calls committed. 301system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached 302system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 303system.cpu.rob.rob_reads 21505 # The number of ROB reads 304system.cpu.rob.rob_writes 23748 # The number of ROB writes 305system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself 306system.cpu.idleCycles 8336 # Total number of cycles that the CPU has spent unscheduled due to idling 307system.cpu.committedInsts 5739 # Number of Instructions Simulated 308system.cpu.committedInsts_total 5739 # Number of Instructions Simulated 309system.cpu.cpi 3.427426 # CPI: Cycles Per Instruction 310system.cpu.cpi_total 3.427426 # CPI: Total CPI of All Threads 311system.cpu.ipc 0.291764 # IPC: Instructions Per Cycle 312system.cpu.ipc_total 0.291764 # IPC: Total IPC of All Threads 313system.cpu.int_regfile_reads 40468 # number of integer regfile reads 314system.cpu.int_regfile_writes 8226 # number of integer regfile writes 315system.cpu.fp_regfile_reads 29 # number of floating regfile reads 316system.cpu.misc_regfile_reads 15801 # number of misc regfile reads 317system.cpu.misc_regfile_writes 24 # number of misc regfile writes 318system.cpu.icache.replacements 2 # number of replacements 319system.cpu.icache.tagsinuse 150.859133 # Cycle average of tags in use 320system.cpu.icache.total_refs 1688 # Total number of references to valid blocks. 321system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 322system.cpu.icache.avg_refs 5.702703 # Average number of references to valid blocks. 323system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 324system.cpu.icache.occ_blocks::0 150.859133 # Average occupied blocks per context 325system.cpu.icache.occ_percent::0 0.073662 # Average percentage of cache occupancy 326system.cpu.icache.ReadReq_hits 1688 # number of ReadReq hits 327system.cpu.icache.demand_hits 1688 # number of demand (read+write) hits 328system.cpu.icache.overall_hits 1688 # number of overall hits 329system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses 330system.cpu.icache.demand_misses 366 # number of demand (read+write) misses 331system.cpu.icache.overall_misses 366 # number of overall misses 332system.cpu.icache.ReadReq_miss_latency 12656500 # number of ReadReq miss cycles 333system.cpu.icache.demand_miss_latency 12656500 # number of demand (read+write) miss cycles 334system.cpu.icache.overall_miss_latency 12656500 # number of overall miss cycles 335system.cpu.icache.ReadReq_accesses 2054 # number of ReadReq accesses(hits+misses) 336system.cpu.icache.demand_accesses 2054 # number of demand (read+write) accesses 337system.cpu.icache.overall_accesses 2054 # number of overall (read+write) accesses 338system.cpu.icache.ReadReq_miss_rate 0.178189 # miss rate for ReadReq accesses 339system.cpu.icache.demand_miss_rate 0.178189 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate 0.178189 # miss rate for overall accesses 341system.cpu.icache.ReadReq_avg_miss_latency 34580.601093 # average ReadReq miss latency 342system.cpu.icache.demand_avg_miss_latency 34580.601093 # average overall miss latency 343system.cpu.icache.overall_avg_miss_latency 34580.601093 # average overall miss latency 344system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 349system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 350system.cpu.icache.fast_writes 0 # number of fast writes performed 351system.cpu.icache.cache_copies 0 # number of cache copies performed 352system.cpu.icache.writebacks 0 # number of writebacks 353system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits 354system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits 355system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits 356system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses 357system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses 358system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses 359system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 360system.cpu.icache.ReadReq_mshr_miss_latency 9940500 # number of ReadReq MSHR miss cycles 361system.cpu.icache.demand_mshr_miss_latency 9940500 # number of demand (read+write) MSHR miss cycles 362system.cpu.icache.overall_mshr_miss_latency 9940500 # number of overall MSHR miss cycles 363system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 364system.cpu.icache.ReadReq_mshr_miss_rate 0.144109 # mshr miss rate for ReadReq accesses 365system.cpu.icache.demand_mshr_miss_rate 0.144109 # mshr miss rate for demand accesses 366system.cpu.icache.overall_mshr_miss_rate 0.144109 # mshr miss rate for overall accesses 367system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270 # average ReadReq mshr miss latency 368system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency 369system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency 370system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 371system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 372system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 373system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 374system.cpu.dcache.replacements 0 # number of replacements 375system.cpu.dcache.tagsinuse 92.281770 # Cycle average of tags in use 376system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. 377system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. 378system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. 379system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 380system.cpu.dcache.occ_blocks::0 92.281770 # Average occupied blocks per context 381system.cpu.dcache.occ_percent::0 0.022530 # Average percentage of cache occupancy 382system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits 383system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits 384system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits 385system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits 386system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits 387system.cpu.dcache.overall_hits 2400 # number of overall hits 388system.cpu.dcache.ReadReq_misses 178 # number of ReadReq misses 389system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses 390system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses 391system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses 392system.cpu.dcache.overall_misses 482 # number of overall misses 393system.cpu.dcache.ReadReq_miss_latency 5526000 # number of ReadReq miss cycles 394system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles 395system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles 396system.cpu.dcache.demand_miss_latency 16231500 # number of demand (read+write) miss cycles 397system.cpu.dcache.overall_miss_latency 16231500 # number of overall miss cycles 398system.cpu.dcache.ReadReq_accesses 1969 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) 401system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) 402system.cpu.dcache.demand_accesses 2882 # number of demand (read+write) accesses 403system.cpu.dcache.overall_accesses 2882 # number of overall (read+write) accesses 404system.cpu.dcache.ReadReq_miss_rate 0.090401 # miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses 406system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses 407system.cpu.dcache.demand_miss_rate 0.167245 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate 0.167245 # miss rate for overall accesses 409system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820 # average ReadReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency 411system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency 412system.cpu.dcache.demand_avg_miss_latency 33675.311203 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency 33675.311203 # average overall miss latency 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed 422system.cpu.dcache.writebacks 0 # number of writebacks 423system.cpu.dcache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits 424system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits 425system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits 426system.cpu.dcache.demand_mshr_hits 326 # number of demand (read+write) MSHR hits 427system.cpu.dcache.overall_mshr_hits 326 # number of overall MSHR hits 428system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses 430system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses 431system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses 432system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 433system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles 434system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles 435system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles 436system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles 437system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 438system.cpu.dcache.ReadReq_mshr_miss_rate 0.057897 # mshr miss rate for ReadReq accesses 439system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses 440system.cpu.dcache.demand_mshr_miss_rate 0.054129 # mshr miss rate for demand accesses 441system.cpu.dcache.overall_mshr_miss_rate 0.054129 # mshr miss rate for overall accesses 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency 443system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency 444system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency 445system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency 446system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 447system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 448system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 449system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 450system.cpu.l2cache.replacements 0 # number of replacements 451system.cpu.l2cache.tagsinuse 190.940380 # Cycle average of tags in use 452system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. 453system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. 454system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. 455system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.l2cache.occ_blocks::0 190.940380 # Average occupied blocks per context 457system.cpu.l2cache.occ_percent::0 0.005827 # Average percentage of cache occupancy 458system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits 459system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits 460system.cpu.l2cache.overall_hits 43 # number of overall hits 461system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses 462system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses 463system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses 464system.cpu.l2cache.overall_misses 409 # number of overall misses 465system.cpu.l2cache.ReadReq_miss_latency 12612500 # number of ReadReq miss cycles 466system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles 467system.cpu.l2cache.demand_miss_latency 14063000 # number of demand (read+write) miss cycles 468system.cpu.l2cache.overall_miss_latency 14063000 # number of overall miss cycles 469system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) 470system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) 471system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses 472system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses 473system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses 474system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 475system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses 476system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses 477system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014 # average ReadReq miss latency 478system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency 479system.cpu.l2cache.demand_avg_miss_latency 34383.863081 # average overall miss latency 480system.cpu.l2cache.overall_avg_miss_latency 34383.863081 # average overall miss latency 481system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 482system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 483system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 484system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 485system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 486system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 487system.cpu.l2cache.fast_writes 0 # number of fast writes performed 488system.cpu.l2cache.cache_copies 0 # number of cache copies performed 489system.cpu.l2cache.writebacks 0 # number of writebacks 490system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits 491system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits 492system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits 493system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses 494system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses 495system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses 496system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses 497system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 498system.cpu.l2cache.ReadReq_mshr_miss_latency 11305500 # number of ReadReq MSHR miss cycles 499system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles 500system.cpu.l2cache.demand_mshr_miss_latency 12622500 # number of demand (read+write) MSHR miss cycles 501system.cpu.l2cache.overall_mshr_miss_latency 12622500 # number of overall MSHR miss cycles 502system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 503system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses 504system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 505system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses 506system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses 507system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31230.662983 # average ReadReq mshr miss latency 508system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency 509system.cpu.l2cache.demand_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency 510system.cpu.l2cache.overall_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency 511system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 512system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 513system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 514system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 515 516---------- End Simulation Statistics ---------- 517