stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 117635 # Simulator instruction rate (inst/s) 4host_mem_usage 212912 # Number of bytes of host memory used 5host_seconds 0.05 # Real time elapsed on the host 6host_tick_rate 220680920 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 5739 # Number of instructions simulated 9sim_seconds 0.000011 # Number of seconds simulated 10sim_ticks 10803500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 701 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 406 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 1671 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 2180 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. 19system.cpu.commit.branchMispredicts 317 # The number of times a branch was mispredicted 20system.cpu.commit.branches 945 # Number of branches committed 21system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached 22system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 23system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions 24system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards 25system.cpu.commit.commitSquashedInsts 4490 # The number of squashed insts skipped by commit 26system.cpu.commit.committed_per_cycle::samples 11008 # Number of insts commited each cycle 27system.cpu.commit.committed_per_cycle::mean 0.521348 # Number of insts commited each cycle 28system.cpu.commit.committed_per_cycle::stdev 1.245214 # Number of insts commited each cycle 29system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 30system.cpu.commit.committed_per_cycle::0 8442 76.69% 76.69% # Number of insts commited each cycle 31system.cpu.commit.committed_per_cycle::1 1229 11.16% 87.85% # Number of insts commited each cycle 32system.cpu.commit.committed_per_cycle::2 550 5.00% 92.85% # Number of insts commited each cycle 33system.cpu.commit.committed_per_cycle::3 321 2.92% 95.77% # Number of insts commited each cycle 34system.cpu.commit.committed_per_cycle::4 184 1.67% 97.44% # Number of insts commited each cycle 35system.cpu.commit.committed_per_cycle::5 137 1.24% 98.68% # Number of insts commited each cycle 36system.cpu.commit.committed_per_cycle::6 51 0.46% 99.15% # Number of insts commited each cycle 37system.cpu.commit.committed_per_cycle::7 32 0.29% 99.44% # Number of insts commited each cycle 38system.cpu.commit.committed_per_cycle::8 62 0.56% 100.00% # Number of insts commited each cycle 39system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 40system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 41system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 42system.cpu.commit.committed_per_cycle::total 11008 # Number of insts commited each cycle 43system.cpu.commit.count 5739 # Number of instructions committed 44system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 45system.cpu.commit.function_calls 82 # Number of function calls committed. 46system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 47system.cpu.commit.loads 1201 # Number of loads committed 48system.cpu.commit.membars 12 # Number of memory barriers committed 49system.cpu.commit.refs 2139 # Number of memory references committed 50system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 51system.cpu.committedInsts 5739 # Number of Instructions Simulated 52system.cpu.committedInsts_total 5739 # Number of Instructions Simulated 53system.cpu.cpi 3.765116 # CPI: Cycles Per Instruction 54system.cpu.cpi_total 3.765116 # CPI: Total CPI of All Threads 55system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) 56system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency 57system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits 58system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles 59system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses 60system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses 61system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits 62system.cpu.dcache.ReadReq_accesses 1818 # number of ReadReq accesses(hits+misses) 63system.cpu.dcache.ReadReq_avg_miss_latency 33323.717949 # average ReadReq miss latency 64system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30423.809524 # average ReadReq mshr miss latency 65system.cpu.dcache.ReadReq_hits 1662 # number of ReadReq hits 66system.cpu.dcache.ReadReq_miss_latency 5198500 # number of ReadReq miss cycles 67system.cpu.dcache.ReadReq_miss_rate 0.085809 # miss rate for ReadReq accesses 68system.cpu.dcache.ReadReq_misses 156 # number of ReadReq misses 69system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits 70system.cpu.dcache.ReadReq_mshr_miss_latency 3194500 # number of ReadReq MSHR miss cycles 71system.cpu.dcache.ReadReq_mshr_miss_rate 0.057756 # mshr miss rate for ReadReq accesses 72system.cpu.dcache.ReadReq_mshr_misses 105 # number of ReadReq MSHR misses 73system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) 74system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits 75system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) 76system.cpu.dcache.WriteReq_avg_miss_latency 35788.659794 # average WriteReq miss latency 77system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency 78system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits 79system.cpu.dcache.WriteReq_miss_latency 10414500 # number of WriteReq miss cycles 80system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses 81system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses 82system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits 83system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles 84system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses 85system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses 86system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 87system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 88system.cpu.dcache.avg_refs 15.673469 # Average number of references to valid blocks. 89system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 90system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 91system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93system.cpu.dcache.cache_copies 0 # number of cache copies performed 94system.cpu.dcache.demand_accesses 2731 # number of demand (read+write) accesses 95system.cpu.dcache.demand_avg_miss_latency 34928.411633 # average overall miss latency 96system.cpu.dcache.demand_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency 97system.cpu.dcache.demand_hits 2284 # number of demand (read+write) hits 98system.cpu.dcache.demand_miss_latency 15613000 # number of demand (read+write) miss cycles 99system.cpu.dcache.demand_miss_rate 0.163676 # miss rate for demand accesses 100system.cpu.dcache.demand_misses 447 # number of demand (read+write) misses 101system.cpu.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency 4699500 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_rate 0.053826 # mshr miss rate for demand accesses 104system.cpu.dcache.demand_mshr_misses 147 # number of demand (read+write) MSHR misses 105system.cpu.dcache.fast_writes 0 # number of fast writes performed 106system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 107system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 108system.cpu.dcache.occ_blocks::0 89.381733 # Average occupied blocks per context 109system.cpu.dcache.occ_percent::0 0.021822 # Average percentage of cache occupancy 110system.cpu.dcache.overall_accesses 2731 # number of overall (read+write) accesses 111system.cpu.dcache.overall_avg_miss_latency 34928.411633 # average overall miss latency 112system.cpu.dcache.overall_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency 113system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 114system.cpu.dcache.overall_hits 2284 # number of overall hits 115system.cpu.dcache.overall_miss_latency 15613000 # number of overall miss cycles 116system.cpu.dcache.overall_miss_rate 0.163676 # miss rate for overall accesses 117system.cpu.dcache.overall_misses 447 # number of overall misses 118system.cpu.dcache.overall_mshr_hits 300 # number of overall MSHR hits 119system.cpu.dcache.overall_mshr_miss_latency 4699500 # number of overall MSHR miss cycles 120system.cpu.dcache.overall_mshr_miss_rate 0.053826 # mshr miss rate for overall accesses 121system.cpu.dcache.overall_mshr_misses 147 # number of overall MSHR misses 122system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 123system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 124system.cpu.dcache.replacements 0 # number of replacements 125system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. 126system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 127system.cpu.dcache.tagsinuse 89.381733 # Cycle average of tags in use 128system.cpu.dcache.total_refs 2304 # Total number of references to valid blocks. 129system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 130system.cpu.dcache.writebacks 0 # number of writebacks 131system.cpu.decode.BlockedCycles 1281 # Number of cycles decode is blocked 132system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction 133system.cpu.decode.BranchResolved 346 # Number of times decode resolved a branch 134system.cpu.decode.DecodedInsts 12207 # Number of instructions handled by decode 135system.cpu.decode.IdleCycles 7419 # Number of cycles decode is idle 136system.cpu.decode.RunCycles 2259 # Number of cycles decode is running 137system.cpu.decode.SquashCycles 770 # Number of cycles decode is squashing 138system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode 139system.cpu.decode.UnblockCycles 48 # Number of cycles decode is unblocking 140system.cpu.dtb.accesses 0 # DTB accesses 141system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 142system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 143system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 144system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 145system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 146system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 147system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu.dtb.hits 0 # DTB hits 149system.cpu.dtb.inst_accesses 0 # ITB inst accesses 150system.cpu.dtb.inst_hits 0 # ITB inst hits 151system.cpu.dtb.inst_misses 0 # ITB inst misses 152system.cpu.dtb.misses 0 # DTB misses 153system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 155system.cpu.dtb.read_accesses 0 # DTB read accesses 156system.cpu.dtb.read_hits 0 # DTB read hits 157system.cpu.dtb.read_misses 0 # DTB read misses 158system.cpu.dtb.write_accesses 0 # DTB write accesses 159system.cpu.dtb.write_hits 0 # DTB write hits 160system.cpu.dtb.write_misses 0 # DTB write misses 161system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered 162system.cpu.fetch.CacheLines 1601 # Number of cache lines fetched 163system.cpu.fetch.Cycles 2402 # Number of cycles fetch has run and was not squashing or blocked 164system.cpu.fetch.IcacheSquashes 236 # Number of outstanding Icache misses that were squashed 165system.cpu.fetch.Insts 11132 # Number of instructions fetch has processed 166system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 167system.cpu.fetch.SquashCycles 496 # Number of cycles fetch has spent squashing 168system.cpu.fetch.branchRate 0.100889 # Number of branch fetches per cycle 169system.cpu.fetch.icacheStallCycles 1601 # Number of cycles fetch is stalled on an Icache miss 170system.cpu.fetch.predictedBranches 943 # Number of branches that fetch has predicted taken 171system.cpu.fetch.rate 0.515180 # Number of inst fetches per cycle 172system.cpu.fetch.rateDist::samples 11777 # Number of instructions fetched each cycle (Total) 173system.cpu.fetch.rateDist::mean 1.177210 # Number of instructions fetched each cycle (Total) 174system.cpu.fetch.rateDist::stdev 2.592697 # Number of instructions fetched each cycle (Total) 175system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 176system.cpu.fetch.rateDist::0 9375 79.60% 79.60% # Number of instructions fetched each cycle (Total) 177system.cpu.fetch.rateDist::1 224 1.90% 81.51% # Number of instructions fetched each cycle (Total) 178system.cpu.fetch.rateDist::2 149 1.27% 82.77% # Number of instructions fetched each cycle (Total) 179system.cpu.fetch.rateDist::3 204 1.73% 84.50% # Number of instructions fetched each cycle (Total) 180system.cpu.fetch.rateDist::4 190 1.61% 86.12% # Number of instructions fetched each cycle (Total) 181system.cpu.fetch.rateDist::5 260 2.21% 88.32% # Number of instructions fetched each cycle (Total) 182system.cpu.fetch.rateDist::6 117 0.99% 89.32% # Number of instructions fetched each cycle (Total) 183system.cpu.fetch.rateDist::7 96 0.82% 90.13% # Number of instructions fetched each cycle (Total) 184system.cpu.fetch.rateDist::8 1162 9.87% 100.00% # Number of instructions fetched each cycle (Total) 185system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 186system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 187system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 188system.cpu.fetch.rateDist::total 11777 # Number of instructions fetched each cycle (Total) 189system.cpu.fp_regfile_reads 16 # number of floating regfile reads 190system.cpu.icache.ReadReq_accesses 1601 # number of ReadReq accesses(hits+misses) 191system.cpu.icache.ReadReq_avg_miss_latency 34737.313433 # average ReadReq miss latency 192system.cpu.icache.ReadReq_avg_mshr_miss_latency 33334.494774 # average ReadReq mshr miss latency 193system.cpu.icache.ReadReq_hits 1266 # number of ReadReq hits 194system.cpu.icache.ReadReq_miss_latency 11637000 # number of ReadReq miss cycles 195system.cpu.icache.ReadReq_miss_rate 0.209244 # miss rate for ReadReq accesses 196system.cpu.icache.ReadReq_misses 335 # number of ReadReq misses 197system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits 198system.cpu.icache.ReadReq_mshr_miss_latency 9567000 # number of ReadReq MSHR miss cycles 199system.cpu.icache.ReadReq_mshr_miss_rate 0.179263 # mshr miss rate for ReadReq accesses 200system.cpu.icache.ReadReq_mshr_misses 287 # number of ReadReq MSHR misses 201system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 202system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 203system.cpu.icache.avg_refs 4.411150 # Average number of references to valid blocks. 204system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 205system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 206system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208system.cpu.icache.cache_copies 0 # number of cache copies performed 209system.cpu.icache.demand_accesses 1601 # number of demand (read+write) accesses 210system.cpu.icache.demand_avg_miss_latency 34737.313433 # average overall miss latency 211system.cpu.icache.demand_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency 212system.cpu.icache.demand_hits 1266 # number of demand (read+write) hits 213system.cpu.icache.demand_miss_latency 11637000 # number of demand (read+write) miss cycles 214system.cpu.icache.demand_miss_rate 0.209244 # miss rate for demand accesses 215system.cpu.icache.demand_misses 335 # number of demand (read+write) misses 216system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits 217system.cpu.icache.demand_mshr_miss_latency 9567000 # number of demand (read+write) MSHR miss cycles 218system.cpu.icache.demand_mshr_miss_rate 0.179263 # mshr miss rate for demand accesses 219system.cpu.icache.demand_mshr_misses 287 # number of demand (read+write) MSHR misses 220system.cpu.icache.fast_writes 0 # number of fast writes performed 221system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 222system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 223system.cpu.icache.occ_blocks::0 145.986730 # Average occupied blocks per context 224system.cpu.icache.occ_percent::0 0.071283 # Average percentage of cache occupancy 225system.cpu.icache.overall_accesses 1601 # number of overall (read+write) accesses 226system.cpu.icache.overall_avg_miss_latency 34737.313433 # average overall miss latency 227system.cpu.icache.overall_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency 228system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 229system.cpu.icache.overall_hits 1266 # number of overall hits 230system.cpu.icache.overall_miss_latency 11637000 # number of overall miss cycles 231system.cpu.icache.overall_miss_rate 0.209244 # miss rate for overall accesses 232system.cpu.icache.overall_misses 335 # number of overall misses 233system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits 234system.cpu.icache.overall_mshr_miss_latency 9567000 # number of overall MSHR miss cycles 235system.cpu.icache.overall_mshr_miss_rate 0.179263 # mshr miss rate for overall accesses 236system.cpu.icache.overall_mshr_misses 287 # number of overall MSHR misses 237system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 238system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 239system.cpu.icache.replacements 2 # number of replacements 240system.cpu.icache.sampled_refs 287 # Sample count of references to valid blocks. 241system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 242system.cpu.icache.tagsinuse 145.986730 # Cycle average of tags in use 243system.cpu.icache.total_refs 1266 # Total number of references to valid blocks. 244system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 245system.cpu.icache.writebacks 0 # number of writebacks 246system.cpu.idleCycles 9831 # Total number of cycles that the CPU has spent unscheduled due to idling 247system.cpu.iew.branchMispredicts 365 # Number of branch mispredicts detected at execute 248system.cpu.iew.exec_branches 1296 # Number of branches executed 249system.cpu.iew.exec_nop 3 # number of nop insts executed 250system.cpu.iew.exec_rate 0.372316 # Inst execution rate 251system.cpu.iew.exec_refs 3091 # number of memory reference insts executed 252system.cpu.iew.exec_stores 1139 # Number of stores executed 253system.cpu.iew.exec_swp 0 # number of swp insts executed 254system.cpu.iew.iewBlockCycles 209 # Number of cycles IEW is blocking 255system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions 256system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions 257system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch 258system.cpu.iew.iewDispStoreInsts 1498 # Number of dispatched store instructions 259system.cpu.iew.iewDispatchedInsts 10370 # Number of instructions dispatched to IQ 260system.cpu.iew.iewExecLoadInsts 1952 # Number of load instructions executed 261system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute 262system.cpu.iew.iewExecutedInsts 8045 # Number of executed instructions 263system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall 264system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 265system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.iewSquashCycles 770 # Number of cycles IEW is squashing 267system.cpu.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking 268system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 269system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 270system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores 271system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 272system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 273system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 274system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations 275system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled 276system.cpu.iew.lsq.thread.0.squashedLoads 1171 # Number of loads squashed 277system.cpu.iew.lsq.thread.0.squashedStores 560 # Number of stores squashed 278system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 279system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly 280system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.wb_consumers 7215 # num instructions consuming a value 282system.cpu.iew.wb_count 7676 # cumulative count of insts written-back 283system.cpu.iew.wb_fanout 0.492862 # average fanout of values written-back 284system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 285system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 286system.cpu.iew.wb_producers 3556 # num instructions producing a value 287system.cpu.iew.wb_rate 0.355239 # insts written-back per cycle 288system.cpu.iew.wb_sent 7793 # cumulative count of insts sent to commit 289system.cpu.int_regfile_reads 18334 # number of integer regfile reads 290system.cpu.int_regfile_writes 5503 # number of integer regfile writes 291system.cpu.ipc 0.265596 # IPC: Instructions Per Cycle 292system.cpu.ipc_total 0.265596 # IPC: Total IPC of All Threads 293system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 294system.cpu.iq.FU_type_0::IntAlu 5116 61.06% 61.06% # Type of FU issued 295system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.13% # Type of FU issued 296system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.13% # Type of FU issued 297system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.13% # Type of FU issued 298system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.13% # Type of FU issued 299system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.13% # Type of FU issued 300system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.13% # Type of FU issued 301system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.13% # Type of FU issued 302system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.13% # Type of FU issued 303system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.13% # Type of FU issued 304system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.13% # Type of FU issued 305system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.13% # Type of FU issued 306system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.13% # Type of FU issued 307system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.13% # Type of FU issued 308system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.13% # Type of FU issued 309system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.13% # Type of FU issued 310system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.13% # Type of FU issued 311system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.13% # Type of FU issued 312system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.13% # Type of FU issued 313system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.13% # Type of FU issued 314system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.13% # Type of FU issued 315system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.13% # Type of FU issued 316system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.13% # Type of FU issued 317system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.13% # Type of FU issued 318system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.13% # Type of FU issued 319system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.16% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.16% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.16% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.16% # Type of FU issued 323system.cpu.iq.FU_type_0::MemRead 2082 24.85% 86.01% # Type of FU issued 324system.cpu.iq.FU_type_0::MemWrite 1172 13.99% 100.00% # Type of FU issued 325system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 326system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 327system.cpu.iq.FU_type_0::total 8379 # Type of FU issued 328system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 329system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 330system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 331system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 332system.cpu.iq.fu_busy_cnt 180 # FU busy when requested 333system.cpu.iq.fu_busy_rate 0.021482 # FU busy rate (busy events/executed inst) 334system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 335system.cpu.iq.fu_full::IntAlu 2 1.11% 1.11% # attempts to use FU when none available 336system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available 338system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available 364system.cpu.iq.fu_full::MemRead 119 66.11% 67.22% # attempts to use FU when none available 365system.cpu.iq.fu_full::MemWrite 59 32.78% 100.00% # attempts to use FU when none available 366system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 367system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 368system.cpu.iq.int_alu_accesses 8539 # Number of integer alu accesses 369system.cpu.iq.int_inst_queue_reads 28698 # Number of integer instruction queue reads 370system.cpu.iq.int_inst_queue_wakeup_accesses 7660 # Number of integer instruction queue wakeup accesses 371system.cpu.iq.int_inst_queue_writes 14568 # Number of integer instruction queue writes 372system.cpu.iq.iqInstsAdded 10342 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqInstsIssued 8379 # Number of instructions issued 374system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ 375system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling 376system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued 377system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 378system.cpu.iq.iqSquashedOperandsExamined 6956 # Number of squashed operands that are examined and possibly removed from graph 379system.cpu.iq.issued_per_cycle::samples 11777 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 0.711472 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 1.348484 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::0 8190 69.54% 69.54% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 1436 12.19% 81.74% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 830 7.05% 88.78% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 533 4.53% 93.31% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 422 3.58% 96.89% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 239 2.03% 98.92% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 96 0.82% 99.74% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 23 0.20% 99.93% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::total 11777 # Number of insts issued each cycle 396system.cpu.iq.rate 0.387773 # Inst issue rate 397system.cpu.itb.accesses 0 # DTB accesses 398system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 399system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 401system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 402system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu.itb.hits 0 # DTB hits 406system.cpu.itb.inst_accesses 0 # ITB inst accesses 407system.cpu.itb.inst_hits 0 # ITB inst hits 408system.cpu.itb.inst_misses 0 # ITB inst misses 409system.cpu.itb.misses 0 # DTB misses 410system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.read_accesses 0 # DTB read accesses 413system.cpu.itb.read_hits 0 # DTB read hits 414system.cpu.itb.read_misses 0 # DTB read misses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.write_hits 0 # DTB write hits 417system.cpu.itb.write_misses 0 # DTB write misses 418system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) 419system.cpu.l2cache.ReadExReq_avg_miss_latency 34392.857143 # average ReadExReq miss latency 420system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.904762 # average ReadExReq mshr miss latency 421system.cpu.l2cache.ReadExReq_miss_latency 1444500 # number of ReadExReq miss cycles 422system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 423system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses 424system.cpu.l2cache.ReadExReq_mshr_miss_latency 1313000 # number of ReadExReq MSHR miss cycles 425system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 426system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses 427system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses) 428system.cpu.l2cache.ReadReq_avg_miss_latency 34365.168539 # average ReadReq miss latency 429system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31250.716332 # average ReadReq mshr miss latency 430system.cpu.l2cache.ReadReq_hits 36 # number of ReadReq hits 431system.cpu.l2cache.ReadReq_miss_latency 12234000 # number of ReadReq miss cycles 432system.cpu.l2cache.ReadReq_miss_rate 0.908163 # miss rate for ReadReq accesses 433system.cpu.l2cache.ReadReq_misses 356 # number of ReadReq misses 434system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits 435system.cpu.l2cache.ReadReq_mshr_miss_latency 10906500 # number of ReadReq MSHR miss cycles 436system.cpu.l2cache.ReadReq_mshr_miss_rate 0.890306 # mshr miss rate for ReadReq accesses 437system.cpu.l2cache.ReadReq_mshr_misses 349 # number of ReadReq MSHR misses 438system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 439system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 440system.cpu.l2cache.avg_refs 0.103152 # Average number of references to valid blocks. 441system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 442system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 443system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 444system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu.l2cache.cache_copies 0 # number of cache copies performed 446system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses 447system.cpu.l2cache.demand_avg_miss_latency 34368.090452 # average overall miss latency 448system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency 449system.cpu.l2cache.demand_hits 36 # number of demand (read+write) hits 450system.cpu.l2cache.demand_miss_latency 13678500 # number of demand (read+write) miss cycles 451system.cpu.l2cache.demand_miss_rate 0.917051 # miss rate for demand accesses 452system.cpu.l2cache.demand_misses 398 # number of demand (read+write) misses 453system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits 454system.cpu.l2cache.demand_mshr_miss_latency 12219500 # number of demand (read+write) MSHR miss cycles 455system.cpu.l2cache.demand_mshr_miss_rate 0.900922 # mshr miss rate for demand accesses 456system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses 457system.cpu.l2cache.fast_writes 0 # number of fast writes performed 458system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 459system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 460system.cpu.l2cache.occ_blocks::0 185.350735 # Average occupied blocks per context 461system.cpu.l2cache.occ_percent::0 0.005656 # Average percentage of cache occupancy 462system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses 463system.cpu.l2cache.overall_avg_miss_latency 34368.090452 # average overall miss latency 464system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency 465system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 466system.cpu.l2cache.overall_hits 36 # number of overall hits 467system.cpu.l2cache.overall_miss_latency 13678500 # number of overall miss cycles 468system.cpu.l2cache.overall_miss_rate 0.917051 # miss rate for overall accesses 469system.cpu.l2cache.overall_misses 398 # number of overall misses 470system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits 471system.cpu.l2cache.overall_mshr_miss_latency 12219500 # number of overall MSHR miss cycles 472system.cpu.l2cache.overall_mshr_miss_rate 0.900922 # mshr miss rate for overall accesses 473system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses 474system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 475system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 476system.cpu.l2cache.replacements 0 # number of replacements 477system.cpu.l2cache.sampled_refs 349 # Sample count of references to valid blocks. 478system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 479system.cpu.l2cache.tagsinuse 185.350735 # Cycle average of tags in use 480system.cpu.l2cache.total_refs 36 # Total number of references to valid blocks. 481system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 482system.cpu.l2cache.writebacks 0 # number of writebacks 483system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. 484system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 485system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. 486system.cpu.memDep0.insertedStores 1498 # Number of stores inserted to the mem dependence unit. 487system.cpu.misc_regfile_reads 13982 # number of misc regfile reads 488system.cpu.misc_regfile_writes 24 # number of misc regfile writes 489system.cpu.numCycles 21608 # number of cpu cycles simulated 490system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 491system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 492system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 493system.cpu.rename.CommittedMaps 4124 # Number of HB maps that are committed 494system.cpu.rename.IQFullEvents 48 # Number of times rename has blocked due to IQ full 495system.cpu.rename.IdleCycles 7684 # Number of cycles rename is idle 496system.cpu.rename.LSQFullEvents 118 # Number of times rename has blocked due to LSQ full 497system.cpu.rename.RenameLookups 30009 # Number of register rename lookups that rename has made 498system.cpu.rename.RenamedInsts 11406 # Number of instructions processed by rename 499system.cpu.rename.RenamedOperands 8239 # Number of destination operands rename has renamed 500system.cpu.rename.RunCycles 2041 # Number of cycles rename is running 501system.cpu.rename.SquashCycles 770 # Number of cycles rename is squashing 502system.cpu.rename.UnblockCycles 193 # Number of cycles rename is unblocking 503system.cpu.rename.UndoneMaps 4112 # Number of HB maps that are undone due to squashing 504system.cpu.rename.fp_rename_lookups 390 # Number of floating rename lookups 505system.cpu.rename.int_rename_lookups 29619 # Number of integer rename lookups 506system.cpu.rename.serializeStallCycles 760 # count of cycles rename stalled for serializing inst 507system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 508system.cpu.rename.skidInsts 508 # count of insts added to the skid buffer 509system.cpu.rename.tempSerializingInsts 14 # count of temporary serializing insts renamed 510system.cpu.rob.rob_reads 21018 # The number of ROB reads 511system.cpu.rob.rob_writes 21240 # The number of ROB writes 512system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself 513system.cpu.workload.num_syscalls 13 # Number of system calls 514 515---------- End Simulation Statistics ---------- 516