stats.txt revision 10628
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310628Sandreas.hansson@arm.comsim_seconds 0.000016 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 16487000 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 33036 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 38686 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 118603969 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 248576 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 0.14 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 5377 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 1710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory 1810628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 1910628Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 26048 # Number of bytes read from this memory 2010628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 2110628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 2210628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 2310628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory 2410628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 2510628Sandreas.hansson@arm.comsystem.physmem.num_reads::total 407 # Number of read requests responded to by this memory 2610628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) 2710628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) 2810628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) 2910628Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) 3010628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) 3110628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) 3210628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) 3310628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) 3410628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) 3510628Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) 3610628Sandreas.hansson@arm.comsystem.physmem.readReqs 408 # Number of read requests accepted 379978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3810628Sandreas.hansson@arm.comsystem.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue 399978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 4010628Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM 419978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 429978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4310628Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 26112 # Total read bytes from the system interface side 449978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 459978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 469978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 479978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 88 # Per bank write bursts 4910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 5010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 19 # Per bank write bursts 5110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 45 # Per bank write bursts 5210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 5310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 5410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 37 # Per bank write bursts 5510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 5610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 7 # Per bank write bursts 5810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 26 # Per bank write bursts 5910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 47 # Per bank write bursts 6010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 17 # Per bank write bursts 6110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 7 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 6310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 789978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 799978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 809978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 819978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8210628Sandreas.hansson@arm.comsystem.physmem.totGap 16473500 # Total gap between requests 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8910628Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 408 # Read request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see 9810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see 9910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see 10010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 10110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 10210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 10310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 10410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 10510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 10610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 10710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 19410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation 19510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation 19610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation 19710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation 19810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation 19910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation 20010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation 20110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation 20210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation 20310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation 20410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation 20510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 20610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 20710628Sandreas.hansson@arm.comsystem.physmem.totQLat 3192729 # Total ticks spent queuing 20810628Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM 20910628Sandreas.hansson@arm.comsystem.physmem.totBusLat 2040000 # Total ticks spent in databus transfers 21010628Sandreas.hansson@arm.comsystem.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst 2119978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 21210628Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst 21310628Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21510628Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s 2169978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2179978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21810628Sandreas.hansson@arm.comsystem.physmem.busUtil 12.37 # Data bus utilization in percentage 21910628Sandreas.hansson@arm.comsystem.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads 2209978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 22110628Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing 2229978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22310628Sandreas.hansson@arm.comsystem.physmem.readRowHits 342 # Number of row buffer hits during reads 2249312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22510628Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads 2269312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22710628Sandreas.hansson@arm.comsystem.physmem.avgGap 40376.23 # Average gap between requests 22810628Sandreas.hansson@arm.comsystem.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined 22910628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) 23010628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) 23110628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) 23210628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23310628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23410628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) 23510628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) 23610628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) 23710628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 918.403600 # Core power per rank (mW) 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states 23910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 24010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 24110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states 24210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 24310628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 24410628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 24510628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) 24610628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24710628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24810628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) 24910628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) 25010628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) 25110628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 817.101847 # Core power per rank (mW) 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states 25310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states 25610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25710628Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2361 # Number of BP lookups 25810628Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted 25910628Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect 26010628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 871 # Number of BTB lookups 26110628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 473 # Number of BTB hits 26210628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26310628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage 26410628Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. 26510628Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. 26610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 28710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 28810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 28910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 29710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3048317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3058317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3068317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3078317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3088317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3098317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3107860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3117860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3127860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3138317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3148317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3158317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3168317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3178317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3188317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3198317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3208317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3218317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3227860SN/Asystem.cpu.dtb.hits 0 # DTB hits 3237860SN/Asystem.cpu.dtb.misses 0 # DTB misses 3248317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 32510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 32610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 35510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3628317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3638317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3648317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3658317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3668317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3678317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3688317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3698317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3708317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3718317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3728317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3738317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3748317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3758317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3768317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3778317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3788317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3798317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3808317SN/Asystem.cpu.itb.hits 0 # DTB hits 3818317SN/Asystem.cpu.itb.misses 0 # DTB misses 3828317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3838317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 38410628Sandreas.hansson@arm.comsystem.cpu.numCycles 32975 # number of cpu cycles simulated 3858317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3868317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38710628Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss 38810628Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 11322 # Number of instructions fetch has processed 38910628Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2361 # Number of branches that fetch encountered 39010628Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken 39110628Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked 39210628Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing 39310628Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39410628Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps 39510628Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR 39610628Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 3848 # Number of cache lines fetched 39710628Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed 39810628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) 39910628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) 40010628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) 4017860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40210628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) 40310628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) 40410628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) 40510628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) 4067860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4077860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 40810409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 40910628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) 41010628Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle 41110628Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle 41210628Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle 41310628Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked 41410628Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 5035 # Number of cycles decode is running 41510628Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 41610628Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing 41710628Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch 41810628Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 41910628Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode 42010628Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode 42110628Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing 42210628Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle 42310628Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking 42410628Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst 42510628Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 4080 # Number of cycles rename is running 42610628Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking 42710628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename 42810628Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename 42910628Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full 43010628Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 43110628Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full 43210628Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full 43310628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed 43410628Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made 43510628Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups 43610409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups 43710352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 43810628Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing 43910409Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 31 # count of serializing insts renamed 44010628Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed 44110628Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 320 # count of insts added to the skid buffer 44210628Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. 44310628Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. 44410409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 44510409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 44610628Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) 44710628Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ 44810628Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 7157 # Number of instructions issued 44910628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued 45010628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling 45110628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph 45210628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 45310628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle 45410628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle 45510628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle 4568241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 45710628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle 45810628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle 45910628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle 46010628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle 46110628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle 46210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 46310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 46410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 46510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4668241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4678241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 46810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 46910628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle 4708317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available 47210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available 47310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available 47410628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available 47510628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available 47610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available 47710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available 47810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available 47910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available 48010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available 48110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available 48210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available 48310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available 48410628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available 48510628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available 48610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available 48710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available 48810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available 48910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available 49010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available 49110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available 49210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available 49310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available 49410628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available 49510628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available 49610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available 49710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available 49810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available 49910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available 50010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available 50110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available 5028317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5038317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5048317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 50510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued 50610628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued 50710628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued 50810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued 50910628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued 51010628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued 51110628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued 51210628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued 51310628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued 51410628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued 51510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued 51610628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued 51710628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued 51810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued 51910628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued 52010628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued 52110628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued 52210628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued 52310628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued 52410628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued 52510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued 52610628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued 52710628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued 52810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued 52910628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued 53010628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued 53110628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued 53210628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued 53310628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued 53410628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued 53510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued 5368317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5378317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 53810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 7157 # Type of FU issued 53910628Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.217043 # Inst issue rate 54010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 1432 # FU busy when requested 54110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) 54210628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads 54310628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes 54410628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses 54510628Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 54610409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes 54710409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 54810628Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses 54910628Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 55010628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores 5518317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55210628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed 55310628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 55410409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 55510628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed 5568317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5578317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 55810628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 55910628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked 5608317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56110628Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing 56210628Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking 56310628Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking 56410628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ 56510409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 56610628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions 56710628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions 56810628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 56910628Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 57010628Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall 57110409Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 57210628Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly 57310628Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly 57410628Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute 57510628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions 57610628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed 57710628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute 5788317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 57910409Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 14 # number of nop insts executed 58010628Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 2417 # number of memory reference insts executed 58110628Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1277 # Number of branches executed 58210628Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1017 # Number of stores executed 58310628Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.205034 # Inst execution rate 58410628Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit 58510628Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 6587 # cumulative count of insts written-back 58610628Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 2990 # num instructions producing a value 58710628Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 5391 # num instructions consuming a value 5888317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 58910628Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.199757 # insts written-back per cycle 59010628Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back 5918317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 59210628Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit 5939459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 59410628Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted 59510628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle 59610628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle 59710628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle 5988317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 59910628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle 60010628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle 60110628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle 60210628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle 60310628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle 60410628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle 60510628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle 60610628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle 60710628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle 6088317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6098317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6108317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61110628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle 6129459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 4591 # Number of instructions committed 61310352Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 6148317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 61510352Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 61610352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 6178317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 6189459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 1007 # Number of branches committed 6198317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 62010352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 6218317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 62210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction 62410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction 62510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction 62610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction 62710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction 62810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction 62910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction 63010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction 63110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction 63210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction 63310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction 63410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction 63510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction 63610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction 63710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction 63810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction 63910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction 64010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction 64110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction 64210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction 64310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction 64410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction 64510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction 64610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction 64710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction 64810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 64910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 65010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 65110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 65210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 65310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 65410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5377 # Class of committed instruction 65710628Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached 6588317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 65910628Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 22003 # The number of ROB reads 66010628Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 16441 # The number of ROB writes 66110628Sandreas.hansson@arm.comsystem.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself 66210628Sandreas.hansson@arm.comsystem.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling 6639459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 4591 # Number of Instructions Simulated 66410352Sandreas.hansson@arm.comsystem.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 66510628Sandreas.hansson@arm.comsystem.cpu.cpi 7.182531 # CPI: Cycles Per Instruction 66610628Sandreas.hansson@arm.comsystem.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads 66710628Sandreas.hansson@arm.comsystem.cpu.ipc 0.139227 # IPC: Instructions Per Cycle 66810628Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads 66910628Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 6737 # number of integer regfile reads 67010628Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 3765 # number of integer regfile writes 67110409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 67210628Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 24010 # number of cc regfile reads 67310628Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 2910 # number of cc regfile writes 67410628Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 2599 # number of misc regfile reads 6759459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 67610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1 # number of replacements 67710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use 67810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. 67910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 68010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. 68110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 68210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor 68310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy 68410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy 68510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 68610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 68710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id 68810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id 68910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses 69010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 4676 # Number of data accesses 69110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits 69210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits 69310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 69410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 69510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 69610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 69710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 69810628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 69910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits 70010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits 70110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits 70210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 1876 # number of overall hits 70310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses 70410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses 70510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 70610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 70710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 70810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 70910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses 71010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses 71110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses 71210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 369 # number of overall misses 71310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles 71410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles 71510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles 71610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles 71710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles 71810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles 71910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles 72010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles 72110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles 72210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles 72310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) 72410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) 72510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 72610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 72710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 72810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 72910628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 73010628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 73110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses 73210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses 73310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses 73410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses 73510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses 73610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses 73710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 73810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 73910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 74010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 74110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses 74210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses 74310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses 74410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses 74510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency 74610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency 74710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency 74810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency 74910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency 75010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency 75110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency 75210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency 75310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency 75410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency 75510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 75610628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked 75710628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 75810628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 75910628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 76010628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked 76110628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 76210628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 76310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits 76410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 76510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 76610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 76710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 76810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 76910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits 77010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits 77110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits 77210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits 77310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 77410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 77510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 77610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 77710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 77810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 77910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 78010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses 78110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles 78210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles 78310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles 78410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles 78510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles 78610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles 78710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles 78810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles 78910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses 79010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses 79110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 79210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 79310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses 79410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses 79510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses 79610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses 79710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency 79810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency 79910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency 80010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency 80110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency 80210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency 80310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency 80410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency 80510628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 42 # number of replacements 80710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use 80810628Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. 80910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. 81010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. 81110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 81210628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor 81310628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy 81410628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy 81510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id 81610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id 81710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 81810628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id 81910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses 82010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 7990 # Number of data accesses 82110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits 82210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits 82310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits 82410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits 82510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits 82610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 3485 # number of overall hits 82710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses 82810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses 82910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses 83010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 83110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses 83210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 362 # number of overall misses 83310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles 83410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles 83510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles 83610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles 83710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles 83810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles 83910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) 84010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) 84110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses 84210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses 84310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses 84410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses 84510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses 84610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses 84710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses 84810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses 84910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses 85010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses 85110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency 85210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency 85310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency 85410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency 85510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency 85610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency 85710628Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked 85810628Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked 85910628Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked 86010628Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 86110628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked 86210628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked 86310628Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 86410628Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 86510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits 86610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 86710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits 86810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits 86910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits 87010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits 87110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 87210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 87310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 87410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 87510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 87610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 87710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16894743 # number of ReadReq MSHR miss cycles 87810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 16894743 # number of ReadReq MSHR miss cycles 87910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 16894743 # number of demand (read+write) MSHR miss cycles 88010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 16894743 # number of demand (read+write) MSHR miss cycles 88110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 16894743 # number of overall MSHR miss cycles 88210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 16894743 # number of overall MSHR miss cycles 88310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for ReadReq accesses 88410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.077203 # mshr miss rate for ReadReq accesses 88510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for demand accesses 88610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.077203 # mshr miss rate for demand accesses 88710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for overall accesses 88810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.077203 # mshr miss rate for overall accesses 88910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566 # average ReadReq mshr miss latency 89010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency 89110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency 89210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency 89310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency 89410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency 89510628Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 89610628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 89710628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 89810628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 89910628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 90010628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 90110628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 90210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 90310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 195.136661 # Cycle average of tags in use 90410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. 90510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 365 # Sample count of references to valid blocks. 90610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.115068 # Average number of references to valid blocks. 90710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 90810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 140.591914 # Average occupied blocks per requestor 90910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 45.333856 # Average occupied blocks per requestor 91010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.210892 # Average occupied blocks per requestor 91110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.008581 # Average percentage of cache occupancy 91210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.002767 # Average percentage of cache occupancy 91310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy 91410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.011910 # Average percentage of cache occupancy 91510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 91610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 91710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id 91810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 91910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 92010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 92110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 92210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # Percentage of cache occupancy per task id 92310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 7446 # Number of tag accesses 92410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 7446 # Number of data accesses 92510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 92610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits 92710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits 92810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 92910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 93010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits 93110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits 93210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits 93310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits 93410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits 93510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 53 # number of overall hits 93610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses 93710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses 93810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses 93910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 94010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses 94110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses 94210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses 94310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 387 # number of demand (read+write) misses 94410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses 94510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses 94610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 387 # number of overall misses 94710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles 94810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles 94910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles 95010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles 95110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles 95210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles 95310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles 95410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles 95510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles 95610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # number of overall miss cycles 95710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 23756500 # number of overall miss cycles 95810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) 95910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 96010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 96110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 96210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 96310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses 96410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses 96510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 96610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses 96710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses 96810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 96910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922559 # miss rate for ReadReq accesses 97010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses 97110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses 97210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 97310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses 97410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses 97510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses 97610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses 97710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses 97810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses 97910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses 98010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency 98110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency 98210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency 98310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency 98410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency 98510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency 98610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency 98710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency 98810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency 98910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency 99010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency 99110628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 99210628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 99310628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 99410628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 99510628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 99610628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 99710628Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 99810628Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 99910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 100010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 100110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 100210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 100310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 100410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 100510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 100610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 100710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 100810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses 100910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses 101010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 101110628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses 101210628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses 101310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 101410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses 101510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses 101610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses 101710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses 101810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses 101910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses 102010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses 102110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses 102210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles 102310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles 102410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles 102510628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles 102610628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles 102710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles 102810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles 102910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles 103010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles 103110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles 103210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles 103310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles 103410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles 103510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles 103610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses 103710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses 103810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses 103910628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 104010628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 104110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 104210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 104310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses 104410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses 104510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses 104610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses 104710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses 104810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 104910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses 105010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency 105110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency 105210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency 105310628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency 105410628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency 105510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency 105610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency 105710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency 105810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency 105910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency 106010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency 106110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency 106210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency 106310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency 106410628Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 106510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 106610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution 106710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution 106810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 106910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 107010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) 107110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) 107210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) 107310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 107410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 107510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) 107610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 67 # Total snoops (count) 107710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram 107810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram 107910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram 108010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 108110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 108210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 108310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 108410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 108510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 108610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram 108710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram 108810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 108910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 109010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 109110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram 109210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) 109310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 109410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) 109510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 109610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) 109710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 109810628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 378 # Transaction distribution 109910628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 376 # Transaction distribution 110010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 30 # Transaction distribution 110110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 30 # Transaction distribution 110210628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) 110310628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) 110410628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) 110510628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) 110610628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 110710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 408 # Request fanout histogram 110810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 110910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 111010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 111110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram 111210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 111310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 111410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 111510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 111610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 408 # Request fanout histogram 111710628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) 111810628Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 3.1 # Layer utilization (%) 111910628Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) 112010628Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 23.0 # Layer utilization (%) 11217860SN/A 11227860SN/A---------- End Simulation Statistics ---------- 1123