stats.txt revision 10220
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39978Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 16955000 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 52426 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 65410 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 193552438 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 308400 # Number of bytes of host memory used 1110148Sandreas.hansson@arm.comhost_seconds 0.09 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 5729 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169978Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 179312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 189978Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25088 # Number of bytes read from this memory 199978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 209978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 219978Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 229312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 239978Sandreas.hansson@arm.comsystem.physmem.num_reads::total 392 # Number of read requests responded to by this memory 2410220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) 2510220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) 2610220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) 2710220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) 2810220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) 2910220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) 3010220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 392 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 86 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 46 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 42 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 17 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 34 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 7 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810220Sandreas.hansson@arm.comsystem.physmem.totGap 16897500 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 392 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see 9410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 9510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 969978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 979797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 989348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 999348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 19010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation 19110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation 19210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation 19310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation 19410220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation 19510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation 19610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation 19710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation 19810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation 19910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation 20010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation 20310220Sandreas.hansson@arm.comsystem.physmem.totQLat 3795000 # Total ticks spent queuing 20410220Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM 2059978Sandreas.hansson@arm.comsystem.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 20610220Sandreas.hansson@arm.comsystem.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810220Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst 20910220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110220Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410220Sandreas.hansson@arm.comsystem.physmem.busUtil 11.56 # Data bus utilization in percentage 21510220Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710220Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910148Sandreas.hansson@arm.comsystem.physmem.readRowHits 326 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310220Sandreas.hansson@arm.comsystem.physmem.avgGap 43105.87 # Average gap between requests 22410148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined 22510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 11000 # Time in different power states 22610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22810220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 15324750 # Time in different power states 22910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23010220Sandreas.hansson@arm.comsystem.membus.throughput 1475906812 # Throughput (bytes/s) 2319978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 351 # Transaction distribution 2329978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 350 # Transaction distribution 2339729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 41 # Transaction distribution 2349729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 41 # Transaction distribution 2359978Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 2369978Sandreas.hansson@arm.comsystem.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 2379978Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 2389978Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 2399978Sandreas.hansson@arm.comsystem.membus.data_through_bus 25024 # Total data (bytes) 2409729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 24110148Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 24210220Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 24310220Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) 24410220Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 21.5 # Layer utilization (%) 24510036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2469978Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2481 # Number of BP lookups 2479978Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 2489620Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 2499978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 2509797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 697 # Number of BTB hits 2519481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2529978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 2539797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 2549481Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 25510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 25610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 25710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 25810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 25910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 26010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 26110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 26210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 26310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 26410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 26510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 26610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 26710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 26810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 26910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 27010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 27110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 27210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 27310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 27410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 27510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2768317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 2778317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 2788317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2798317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2808317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2818317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2827860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2837860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2847860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2858317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2868317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2878317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2888317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2898317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2908317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2918317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2928317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2938317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 2947860SN/Asystem.cpu.dtb.hits 0 # DTB hits 2957860SN/Asystem.cpu.dtb.misses 0 # DTB misses 2968317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 29710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 30210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 30810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 31610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 31710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3188317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3198317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3208317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3218317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3228317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3238317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3248317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3258317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3268317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3278317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3288317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3298317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3308317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3318317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3328317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3338317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3348317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3358317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3368317SN/Asystem.cpu.itb.hits 0 # DTB hits 3378317SN/Asystem.cpu.itb.misses 0 # DTB misses 3388317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3398317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 34010220Sandreas.hansson@arm.comsystem.cpu.numCycles 33911 # number of cpu cycles simulated 3418317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3428317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34310220Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss 3449978Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 3459978Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 3469797Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 3479978Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 3489797Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 34910220Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked 3509797Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 3519978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 35210220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) 35310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) 35410220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) 3557860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 35610220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) 35710220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) 35810220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) 35910220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) 36010220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) 36110220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) 36210220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) 36310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) 36410220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) 3657860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3667860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3677860SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 36810220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) 36910220Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle 37010220Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle 37110220Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle 37210220Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked 3739978Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2426 # Number of cycles decode is running 3749978Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 3759797Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 3769797Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 3779729Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 3789978Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 3799348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 3809797Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 38110220Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle 3829978Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 38310220Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst 3849978Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2227 # Number of cycles rename is running 3859978Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 3869978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 3879729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 3889978Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 3899978Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 3909978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 39110038SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made 3929978Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 3939924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 3949459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 3959978Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 3969459Ssaidi@eecs.umich.edusystem.cpu.rename.serializingInsts 41 # count of serializing insts renamed 3979459Ssaidi@eecs.umich.edusystem.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 39810148Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 666 # count of insts added to the skid buffer 3999978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 4009978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 4019459Ssaidi@eecs.umich.edusystem.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 4029729Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 4039978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 4049459Ssaidi@eecs.umich.edusystem.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 4059978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 4069978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 4079978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 40810038SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph 4099459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 41010220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle 41110220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle 41210220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle 4138241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 41410220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle 41510220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle 41610220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle 41710220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle 41810148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle 41910220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle 42010220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle 4219978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 4229729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 4238241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4248241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4258241SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 42610220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle 4278317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 4289978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 4299978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 4309978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 4319978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 4329978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 4339978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 4349978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 4359978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 4369978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 4379978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 4389978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 4399978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 4409978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 4419978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 4429978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 4439978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 4449978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 4459978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 4469978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 4479978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 4489978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 4499978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 4509978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 4519978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 4529978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 4539978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 4549978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 4559978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 4569978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 4579978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 4589978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 4598317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4608317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4618317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 4629978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 4639978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 4649978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 4659978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 4669978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 4679978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 4689978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 4699978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 4709978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 4719978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 4729978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 4739978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 4749978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 4759978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 4769978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 4779978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 4789978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 4799978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 4809978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 4819978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 4829978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 4839978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 4849978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 4859978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 4869978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 4879978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 4889978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 4899978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 4909978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 4919978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 4929978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 4938317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4948317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4959978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8921 # Type of FU issued 49610220Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.263071 # Inst issue rate 4979978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 224 # FU busy when requested 4989978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 49910220Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads 5009978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 5019978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 5028632SN/Asystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 5039322Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 5048317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 5059978Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 5068632SN/Asystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 5079729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 5088317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 5099978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 5109312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 5119729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 5129978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 5138317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5148317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5158632SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 5169348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 5178317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 5189797Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 5199797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 5209978Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 5219978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 5229978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 5239978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 5249978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 5259459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 5269978Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 5279285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 5289729Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 5299620Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 5309797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 5319797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 53210220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions 53310220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed 53410220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 5358317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 5369348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 53710220Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3300 # number of memory reference insts executed 5389797Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1437 # Number of branches executed 5399729Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1160 # Number of stores executed 54010220Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.251364 # Inst execution rate 5419978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 5429978Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 8068 # cumulative count of insts written-back 5439978Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 3883 # num instructions producing a value 54410220Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7789 # num instructions consuming a value 5458317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 54610220Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.237917 # insts written-back per cycle 54710220Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back 5488317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 5499978Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 5509459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 5519620Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 55210220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle 55310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle 55410220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle 5558317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 55610220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle 55710220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle 55810220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle 55910148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle 56010220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle 5619978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 5629978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 56310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 56410220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 5658317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5668317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5678317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 56810220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle 5699459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 4591 # Number of instructions committed 5709459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 5718317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5729459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 2138 # Number of memory references committed 5739459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 1200 # Number of loads committed 5748317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 5759459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 1007 # Number of branches committed 5768317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 5779459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 5788317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 57910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 58010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction 58110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction 58210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction 58310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction 58410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction 58510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction 58610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction 58710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction 58810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction 58910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction 59010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction 59110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction 59210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction 59310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction 59410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction 59510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction 59610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction 59710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction 59810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction 59910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction 60010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction 60110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction 60210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction 60310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction 60410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction 60510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction 60610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction 60710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction 60810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction 60910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction 61010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction 61110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 61210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 61310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5729 # Class of committed instruction 6149978Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 6158317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 61610220Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 23248 # The number of ROB reads 6179978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 23415 # The number of ROB writes 61810220Sandreas.hansson@arm.comsystem.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 61910220Sandreas.hansson@arm.comsystem.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling 6209459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 4591 # Number of Instructions Simulated 6219459Ssaidi@eecs.umich.edusystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 6229459Ssaidi@eecs.umich.edusystem.cpu.committedInsts_total 4591 # Number of Instructions Simulated 62310220Sandreas.hansson@arm.comsystem.cpu.cpi 7.386408 # CPI: Cycles Per Instruction 62410220Sandreas.hansson@arm.comsystem.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads 62510220Sandreas.hansson@arm.comsystem.cpu.ipc 0.135384 # IPC: Instructions Per Cycle 62610220Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads 62710220Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 39214 # number of integer regfile reads 6289978Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7985 # number of integer regfile writes 6298632SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 63010038SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 3239 # number of misc regfile reads 6319459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 63210220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) 6339978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 6349978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 6359729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 6369729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 6379978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 6389838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 6399978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 6409978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 6419838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 6429978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 6439978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 6449729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 6459978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 6469729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 64710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) 6489978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 64910220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) 65010220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 6519838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 4 # number of replacements 65210220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use 6539978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 6549978Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 6559978Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 6569838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 65710220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor 65810220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy 65910220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy 66010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 66110220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 66210220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 66310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 66410036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 66510036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 4184 # Number of data accesses 6669978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 6679978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 6689978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 6699978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 6709978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 6719978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1584 # number of overall hits 6729978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 6739978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 6749978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 6759978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 6769978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 6779978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 363 # number of overall misses 67810220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles 67910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles 68010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles 68110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles 68210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles 68310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles 6849797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 6859797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 6869797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 6879797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 6889797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 6899797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 6909978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 6919978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 6929978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 6939978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 6949978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 6959978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 69610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency 69710220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency 69810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 69910220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency 70010220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 70110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency 7029978Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 7038317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7049978Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 7058317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 7069978Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 7078983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7088317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7098317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 7109729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 7119729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 7129729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 7139729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 7149729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 7159729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 7169978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 7179978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 7189978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 7199978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 7209978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 7219978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 72210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles 72310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles 72410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles 72510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles 72610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles 72710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles 7289978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 7299978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 7309978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 7319978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 7329978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 7339978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 73410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency 73510220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency 73610220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 73710220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 73810220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 73910220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 7408317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7419838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 74210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use 7439838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 7449978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 7459978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 7469838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 74710220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor 74810220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor 74910220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy 75010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy 75110220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy 75210036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 75310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 75410220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 75510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 75610036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 75710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 7589729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 7599449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 7609729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 7619729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 7629449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 7639729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 7649729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 7659449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 7669729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 40 # number of overall hits 7679978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 7689449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 7699978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 7709449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 7719449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 7729978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 7739449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 7749978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 7759978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 7769449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 7779978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 397 # number of overall misses 77810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles 77910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles 78010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles 78110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles 78210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles 78310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles 78410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles 78510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles 78610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles 78710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles 78810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles 7899978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 7909449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 7919978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 7929449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 7939449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 7949978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 7959449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 7969978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 7979978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 7989449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 7999978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 8009978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 8019449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 8029978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 8039449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8049449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 8059978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 8069449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 8079978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 8089978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 8099449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 8109978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 81110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency 81210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency 81310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency 81410148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency 81510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency 81610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 81710220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 81810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency 81910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 82010220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 82110220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency 8229449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8239449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8249449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8259449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8269449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8279449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8289449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8299449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8309449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 8319449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 8329449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 8339449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 8349449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 8359449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 8369978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 8379449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 8389978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 8399449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 8409449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 8419978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 8429449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 8439978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 8449978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 8459449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 8469978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 84710220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles 84810220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles 84910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles 85010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles 85110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles 85210220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles 85310220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles 85410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles 85510220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles 85610220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles 85710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles 8589978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 8599449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 8609978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 8619449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8629449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 8639978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 8649449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 8659978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 8669978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 8679449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 8689978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 86910220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency 87010220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency 87110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency 87210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency 87310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency 87410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 87510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 87610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 87710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 87810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 87910220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 8809449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8819838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 88210220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use 88310220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 8849838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 88510220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. 8869838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 88710220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor 88810220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy 88910220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy 89010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 89110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 89210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 89310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 89410220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses 89510220Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 5932 # Number of data accesses 8969978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 8979978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 8989378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 8999378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 90010220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 90110220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 9029459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 9039459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 9049978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 9059978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 9069978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 9079978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2373 # number of overall hits 9089978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 9099978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 9109378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 9119378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 9129378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 9139378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 9149978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 9159978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 9169978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 9179978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 496 # number of overall misses 91810220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles 91910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles 92010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles 92110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles 9229797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 9239797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 92410220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles 92510220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles 92610220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles 92710220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles 9289978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 9299978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 9309378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 9319378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 93210220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 93310220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 9349459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 9359459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 9369978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 9379978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 9389978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 9399978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 9409978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 9419978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 9429378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 9439378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 94410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 94510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 9469978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 9479978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 9489978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 9499978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 95010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency 95110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency 95210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency 95310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency 9549797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 9559797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 95610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 95710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency 95810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 95910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency 9609797Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 9619378Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9629378Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 9639378Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 9649797Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 9659378Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9669378Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 9679378Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 9689978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 9699978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 9709378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 9719378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 9729378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 9739378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 9749978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 9759978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 9769978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 9779978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 9789378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 9799378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 9809378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 9819378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 9829378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 9839378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 9849378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 9859378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 98610220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles 98710220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles 98810148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles 98910148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles 99010220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles 99110220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles 99210220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles 99310220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles 9949978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 9959978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 9969378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 9979378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 9989978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 9999978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 10009978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 10019978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 100210220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency 100310220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency 100410148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency 100510148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency 100610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 100710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 100810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 100910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 10109378Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10117860SN/A 10127860SN/A---------- End Simulation Statistics ---------- 1013