config.ini revision 8802:ef66a9083bc4
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12memories=system.physmem 13num_work_ids=16 14physmem=system.physmem 15work_begin_ckpt_count=0 16work_begin_cpu_id_exit=-1 17work_begin_exit_count=0 18work_cpus_ckpt_count=0 19work_end_ckpt_count=0 20work_end_exit_count=0 21work_item_id=-1 22system_port=system.membus.port[0] 23 24[system.cpu] 25type=DerivO3CPU 26children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 27BTBEntries=4096 28BTBTagSize=16 29LFSTSize=1024 30LQEntries=32 31LSQCheckLoads=true 32LSQDepCheckShift=4 33RASSize=16 34SQEntries=32 35SSITSize=1024 36activity=0 37backComSize=5 38cachePorts=200 39checker=Null 40choiceCtrBits=2 41choicePredictorSize=8192 42clock=500 43commitToDecodeDelay=1 44commitToFetchDelay=1 45commitToIEWDelay=1 46commitToRenameDelay=1 47commitWidth=8 48cpu_id=0 49decodeToFetchDelay=1 50decodeToRenameDelay=1 51decodeWidth=8 52defer_registration=false 53dispatchWidth=8 54do_checkpoint_insts=true 55do_statistics_insts=true 56dtb=system.cpu.dtb 57fetchToDecodeDelay=1 58fetchTrapLatency=1 59fetchWidth=8 60forwardComSize=5 61fuPool=system.cpu.fuPool 62function_trace=false 63function_trace_start=0 64globalCtrBits=2 65globalHistoryBits=13 66globalPredictorSize=8192 67iewToCommitDelay=1 68iewToDecodeDelay=1 69iewToFetchDelay=1 70iewToRenameDelay=1 71instShiftAmt=2 72issueToExecuteDelay=1 73issueWidth=8 74itb=system.cpu.itb 75localCtrBits=2 76localHistoryBits=11 77localHistoryTableSize=2048 78localPredictorSize=2048 79max_insts_all_threads=0 80max_insts_any_thread=0 81max_loads_all_threads=0 82max_loads_any_thread=0 83numIQEntries=64 84numPhysFloatRegs=256 85numPhysIntRegs=256 86numROBEntries=192 87numRobs=1 88numThreads=1 89phase=0 90predType=tournament 91progress_interval=0 92renameToDecodeDelay=1 93renameToFetchDelay=1 94renameToIEWDelay=2 95renameToROBDelay=1 96renameWidth=8 97smtCommitPolicy=RoundRobin 98smtFetchPolicy=SingleThread 99smtIQPolicy=Partitioned 100smtIQThreshold=100 101smtLSQPolicy=Partitioned 102smtLSQThreshold=100 103smtNumFetchingThreads=1 104smtROBPolicy=Partitioned 105smtROBThreshold=100 106squashWidth=8 107store_set_clear_period=250000 108system=system 109tracer=system.cpu.tracer 110trapLatency=13 111wbDepth=1 112wbWidth=8 113workload=system.cpu.workload 114dcache_port=system.cpu.dcache.cpu_side 115icache_port=system.cpu.icache.cpu_side 116 117[system.cpu.dcache] 118type=BaseCache 119addr_range=0:18446744073709551615 120assoc=2 121block_size=64 122forward_snoops=true 123hash_delay=1 124is_top_level=true 125latency=1000 126max_miss_count=0 127mshrs=10 128num_cpus=1 129prefetch_data_accesses_only=false 130prefetch_degree=1 131prefetch_latency=10000 132prefetch_on_access=false 133prefetch_past_page=false 134prefetch_policy=none 135prefetch_serial_squash=false 136prefetch_use_cpu_id=true 137prefetcher_size=100 138prioritizeRequests=false 139repl=Null 140size=262144 141subblock_size=0 142tgts_per_mshr=20 143trace_addr=0 144two_queue=false 145write_buffers=8 146cpu_side=system.cpu.dcache_port 147mem_side=system.cpu.toL2Bus.port[1] 148 149[system.cpu.dtb] 150type=ArmTLB 151size=64 152 153[system.cpu.fuPool] 154type=FUPool 155children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 156FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 157 158[system.cpu.fuPool.FUList0] 159type=FUDesc 160children=opList 161count=6 162opList=system.cpu.fuPool.FUList0.opList 163 164[system.cpu.fuPool.FUList0.opList] 165type=OpDesc 166issueLat=1 167opClass=IntAlu 168opLat=1 169 170[system.cpu.fuPool.FUList1] 171type=FUDesc 172children=opList0 opList1 173count=2 174opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 175 176[system.cpu.fuPool.FUList1.opList0] 177type=OpDesc 178issueLat=1 179opClass=IntMult 180opLat=3 181 182[system.cpu.fuPool.FUList1.opList1] 183type=OpDesc 184issueLat=19 185opClass=IntDiv 186opLat=20 187 188[system.cpu.fuPool.FUList2] 189type=FUDesc 190children=opList0 opList1 opList2 191count=4 192opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 193 194[system.cpu.fuPool.FUList2.opList0] 195type=OpDesc 196issueLat=1 197opClass=FloatAdd 198opLat=2 199 200[system.cpu.fuPool.FUList2.opList1] 201type=OpDesc 202issueLat=1 203opClass=FloatCmp 204opLat=2 205 206[system.cpu.fuPool.FUList2.opList2] 207type=OpDesc 208issueLat=1 209opClass=FloatCvt 210opLat=2 211 212[system.cpu.fuPool.FUList3] 213type=FUDesc 214children=opList0 opList1 opList2 215count=2 216opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 217 218[system.cpu.fuPool.FUList3.opList0] 219type=OpDesc 220issueLat=1 221opClass=FloatMult 222opLat=4 223 224[system.cpu.fuPool.FUList3.opList1] 225type=OpDesc 226issueLat=12 227opClass=FloatDiv 228opLat=12 229 230[system.cpu.fuPool.FUList3.opList2] 231type=OpDesc 232issueLat=24 233opClass=FloatSqrt 234opLat=24 235 236[system.cpu.fuPool.FUList4] 237type=FUDesc 238children=opList 239count=0 240opList=system.cpu.fuPool.FUList4.opList 241 242[system.cpu.fuPool.FUList4.opList] 243type=OpDesc 244issueLat=1 245opClass=MemRead 246opLat=1 247 248[system.cpu.fuPool.FUList5] 249type=FUDesc 250children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 251count=4 252opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 253 254[system.cpu.fuPool.FUList5.opList00] 255type=OpDesc 256issueLat=1 257opClass=SimdAdd 258opLat=1 259 260[system.cpu.fuPool.FUList5.opList01] 261type=OpDesc 262issueLat=1 263opClass=SimdAddAcc 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList02] 267type=OpDesc 268issueLat=1 269opClass=SimdAlu 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList03] 273type=OpDesc 274issueLat=1 275opClass=SimdCmp 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList04] 279type=OpDesc 280issueLat=1 281opClass=SimdCvt 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList05] 285type=OpDesc 286issueLat=1 287opClass=SimdMisc 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList06] 291type=OpDesc 292issueLat=1 293opClass=SimdMult 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList07] 297type=OpDesc 298issueLat=1 299opClass=SimdMultAcc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList08] 303type=OpDesc 304issueLat=1 305opClass=SimdShift 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList09] 309type=OpDesc 310issueLat=1 311opClass=SimdShiftAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList10] 315type=OpDesc 316issueLat=1 317opClass=SimdSqrt 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList11] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAdd 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList12] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatAlu 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList13] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCmp 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList14] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatCvt 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList15] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatDiv 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList16] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMisc 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList17] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMult 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList18] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMultAcc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList19] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatSqrt 372opLat=1 373 374[system.cpu.fuPool.FUList6] 375type=FUDesc 376children=opList 377count=0 378opList=system.cpu.fuPool.FUList6.opList 379 380[system.cpu.fuPool.FUList6.opList] 381type=OpDesc 382issueLat=1 383opClass=MemWrite 384opLat=1 385 386[system.cpu.fuPool.FUList7] 387type=FUDesc 388children=opList0 opList1 389count=4 390opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 391 392[system.cpu.fuPool.FUList7.opList0] 393type=OpDesc 394issueLat=1 395opClass=MemRead 396opLat=1 397 398[system.cpu.fuPool.FUList7.opList1] 399type=OpDesc 400issueLat=1 401opClass=MemWrite 402opLat=1 403 404[system.cpu.fuPool.FUList8] 405type=FUDesc 406children=opList 407count=1 408opList=system.cpu.fuPool.FUList8.opList 409 410[system.cpu.fuPool.FUList8.opList] 411type=OpDesc 412issueLat=3 413opClass=IprAccess 414opLat=3 415 416[system.cpu.icache] 417type=BaseCache 418addr_range=0:18446744073709551615 419assoc=2 420block_size=64 421forward_snoops=true 422hash_delay=1 423is_top_level=true 424latency=1000 425max_miss_count=0 426mshrs=10 427num_cpus=1 428prefetch_data_accesses_only=false 429prefetch_degree=1 430prefetch_latency=10000 431prefetch_on_access=false 432prefetch_past_page=false 433prefetch_policy=none 434prefetch_serial_squash=false 435prefetch_use_cpu_id=true 436prefetcher_size=100 437prioritizeRequests=false 438repl=Null 439size=131072 440subblock_size=0 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.port[0] 447 448[system.cpu.itb] 449type=ArmTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache 454addr_range=0:18446744073709551615 455assoc=2 456block_size=64 457forward_snoops=true 458hash_delay=1 459is_top_level=false 460latency=1000 461max_miss_count=0 462mshrs=10 463num_cpus=1 464prefetch_data_accesses_only=false 465prefetch_degree=1 466prefetch_latency=10000 467prefetch_on_access=false 468prefetch_past_page=false 469prefetch_policy=none 470prefetch_serial_squash=false 471prefetch_use_cpu_id=true 472prefetcher_size=100 473prioritizeRequests=false 474repl=Null 475size=2097152 476subblock_size=0 477tgts_per_mshr=5 478trace_addr=0 479two_queue=false 480write_buffers=8 481cpu_side=system.cpu.toL2Bus.port[2] 482mem_side=system.membus.port[2] 483 484[system.cpu.toL2Bus] 485type=Bus 486block_size=64 487bus_id=0 488clock=1000 489header_cycles=1 490use_default_range=false 491width=64 492port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 493 494[system.cpu.tracer] 495type=ExeTracer 496 497[system.cpu.workload] 498type=LiveProcess 499cmd=hello 500cwd= 501egid=100 502env= 503errout=cerr 504euid=100 505executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 506gid=100 507input=cin 508max_stack_size=67108864 509output=cout 510pid=100 511ppid=99 512simpoint=0 513system=system 514uid=100 515 516[system.membus] 517type=Bus 518block_size=64 519bus_id=0 520clock=1000 521header_cycles=1 522use_default_range=false 523width=64 524port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side 525 526[system.physmem] 527type=PhysicalMemory 528file= 529latency=30000 530latency_var=0 531null=false 532range=0:134217727 533zero=false 534port=system.membus.port[1] 535 536