config.ini revision 11268:8b4b55d79ddd
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.clk_domain] 41type=SrcClockDomain 42clock=1000 43domain_id=-1 44eventq_index=0 45init_perf_level=0 46voltage_domain=system.voltage_domain 47 48[system.cpu] 49type=DerivO3CPU 50children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 51LFSTSize=1024 52LQEntries=16 53LSQCheckLoads=true 54LSQDepCheckShift=0 55SQEntries=16 56SSITSize=1024 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=2 71decodeWidth=3 72dispatchWidth=6 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dstage2_mmu=system.cpu.dstage2_mmu 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=16 80fetchQueueSize=32 81fetchToDecodeDelay=3 82fetchTrapLatency=1 83fetchWidth=3 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96istage2_mmu=system.cpu.istage2_mmu 97itb=system.cpu.itb 98max_insts_all_threads=0 99max_insts_any_thread=0 100max_loads_all_threads=0 101max_loads_any_thread=0 102needsTSO=false 103numIQEntries=32 104numPhysCCRegs=640 105numPhysFloatRegs=192 106numPhysIntRegs=128 107numROBEntries=40 108numRobs=1 109numThreads=1 110profile=0 111progress_interval=0 112renameToDecodeDelay=1 113renameToFetchDelay=1 114renameToIEWDelay=1 115renameToROBDelay=1 116renameWidth=3 117simpoint_start_insts= 118smtCommitPolicy=RoundRobin 119smtFetchPolicy=SingleThread 120smtIQPolicy=Partitioned 121smtIQThreshold=100 122smtLSQPolicy=Partitioned 123smtLSQThreshold=100 124smtNumFetchingThreads=1 125smtROBPolicy=Partitioned 126smtROBThreshold=100 127socket_id=0 128squashWidth=8 129store_set_clear_period=250000 130switched_out=false 131system=system 132tracer=system.cpu.tracer 133trapLatency=13 134wbWidth=8 135workload=system.cpu.workload 136dcache_port=system.cpu.dcache.cpu_side 137icache_port=system.cpu.icache.cpu_side 138 139[system.cpu.branchPred] 140type=BiModeBP 141BTBEntries=2048 142BTBTagSize=18 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 146eventq_index=0 147globalCtrBits=2 148globalPredictorSize=8192 149instShiftAmt=2 150numThreads=1 151 152[system.cpu.dcache] 153type=Cache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=2 157clk_domain=system.cpu_clk_domain 158clusivity=mostly_incl 159demand_mshr_reserve=1 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_read_only=false 164max_miss_count=0 165mshrs=6 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=32768 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=8 174write_buffers=16 175writeback_clean=true 176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=32768 188 189[system.cpu.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 194sys=system 195tlb=system.cpu.dtb 196 197[system.cpu.dstage2_mmu.stage2_tlb] 198type=ArmTLB 199children=walker 200eventq_index=0 201is_stage2=true 202size=32 203walker=system.cpu.dstage2_mmu.stage2_tlb.walker 204 205[system.cpu.dstage2_mmu.stage2_tlb.walker] 206type=ArmTableWalker 207clk_domain=system.cpu_clk_domain 208eventq_index=0 209is_stage2=true 210num_squash_per_cycle=2 211sys=system 212 213[system.cpu.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.dtb.walker 220 221[system.cpu.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system 228port=system.cpu.toL2Bus.slave[3] 229 230[system.cpu.fuPool] 231type=FUPool 232children=FUList0 FUList1 FUList2 FUList3 FUList4 233FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 234eventq_index=0 235 236[system.cpu.fuPool.FUList0] 237type=FUDesc 238children=opList 239count=2 240eventq_index=0 241opList=system.cpu.fuPool.FUList0.opList 242 243[system.cpu.fuPool.FUList0.opList] 244type=OpDesc 245eventq_index=0 246opClass=IntAlu 247opLat=1 248pipelined=true 249 250[system.cpu.fuPool.FUList1] 251type=FUDesc 252children=opList0 opList1 opList2 253count=1 254eventq_index=0 255opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 256 257[system.cpu.fuPool.FUList1.opList0] 258type=OpDesc 259eventq_index=0 260opClass=IntMult 261opLat=3 262pipelined=true 263 264[system.cpu.fuPool.FUList1.opList1] 265type=OpDesc 266eventq_index=0 267opClass=IntDiv 268opLat=12 269pipelined=false 270 271[system.cpu.fuPool.FUList1.opList2] 272type=OpDesc 273eventq_index=0 274opClass=IprAccess 275opLat=3 276pipelined=true 277 278[system.cpu.fuPool.FUList2] 279type=FUDesc 280children=opList 281count=1 282eventq_index=0 283opList=system.cpu.fuPool.FUList2.opList 284 285[system.cpu.fuPool.FUList2.opList] 286type=OpDesc 287eventq_index=0 288opClass=MemRead 289opLat=2 290pipelined=true 291 292[system.cpu.fuPool.FUList3] 293type=FUDesc 294children=opList 295count=1 296eventq_index=0 297opList=system.cpu.fuPool.FUList3.opList 298 299[system.cpu.fuPool.FUList3.opList] 300type=OpDesc 301eventq_index=0 302opClass=MemWrite 303opLat=2 304pipelined=true 305 306[system.cpu.fuPool.FUList4] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 309count=2 310eventq_index=0 311opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 312 313[system.cpu.fuPool.FUList4.opList00] 314type=OpDesc 315eventq_index=0 316opClass=SimdAdd 317opLat=4 318pipelined=true 319 320[system.cpu.fuPool.FUList4.opList01] 321type=OpDesc 322eventq_index=0 323opClass=SimdAddAcc 324opLat=4 325pipelined=true 326 327[system.cpu.fuPool.FUList4.opList02] 328type=OpDesc 329eventq_index=0 330opClass=SimdAlu 331opLat=4 332pipelined=true 333 334[system.cpu.fuPool.FUList4.opList03] 335type=OpDesc 336eventq_index=0 337opClass=SimdCmp 338opLat=4 339pipelined=true 340 341[system.cpu.fuPool.FUList4.opList04] 342type=OpDesc 343eventq_index=0 344opClass=SimdCvt 345opLat=3 346pipelined=true 347 348[system.cpu.fuPool.FUList4.opList05] 349type=OpDesc 350eventq_index=0 351opClass=SimdMisc 352opLat=3 353pipelined=true 354 355[system.cpu.fuPool.FUList4.opList06] 356type=OpDesc 357eventq_index=0 358opClass=SimdMult 359opLat=5 360pipelined=true 361 362[system.cpu.fuPool.FUList4.opList07] 363type=OpDesc 364eventq_index=0 365opClass=SimdMultAcc 366opLat=5 367pipelined=true 368 369[system.cpu.fuPool.FUList4.opList08] 370type=OpDesc 371eventq_index=0 372opClass=SimdShift 373opLat=3 374pipelined=true 375 376[system.cpu.fuPool.FUList4.opList09] 377type=OpDesc 378eventq_index=0 379opClass=SimdShiftAcc 380opLat=3 381pipelined=true 382 383[system.cpu.fuPool.FUList4.opList10] 384type=OpDesc 385eventq_index=0 386opClass=SimdSqrt 387opLat=9 388pipelined=true 389 390[system.cpu.fuPool.FUList4.opList11] 391type=OpDesc 392eventq_index=0 393opClass=SimdFloatAdd 394opLat=5 395pipelined=true 396 397[system.cpu.fuPool.FUList4.opList12] 398type=OpDesc 399eventq_index=0 400opClass=SimdFloatAlu 401opLat=5 402pipelined=true 403 404[system.cpu.fuPool.FUList4.opList13] 405type=OpDesc 406eventq_index=0 407opClass=SimdFloatCmp 408opLat=3 409pipelined=true 410 411[system.cpu.fuPool.FUList4.opList14] 412type=OpDesc 413eventq_index=0 414opClass=SimdFloatCvt 415opLat=3 416pipelined=true 417 418[system.cpu.fuPool.FUList4.opList15] 419type=OpDesc 420eventq_index=0 421opClass=SimdFloatDiv 422opLat=3 423pipelined=true 424 425[system.cpu.fuPool.FUList4.opList16] 426type=OpDesc 427eventq_index=0 428opClass=SimdFloatMisc 429opLat=3 430pipelined=true 431 432[system.cpu.fuPool.FUList4.opList17] 433type=OpDesc 434eventq_index=0 435opClass=SimdFloatMult 436opLat=3 437pipelined=true 438 439[system.cpu.fuPool.FUList4.opList18] 440type=OpDesc 441eventq_index=0 442opClass=SimdFloatMultAcc 443opLat=1 444pipelined=true 445 446[system.cpu.fuPool.FUList4.opList19] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatSqrt 450opLat=9 451pipelined=true 452 453[system.cpu.fuPool.FUList4.opList20] 454type=OpDesc 455eventq_index=0 456opClass=FloatAdd 457opLat=5 458pipelined=true 459 460[system.cpu.fuPool.FUList4.opList21] 461type=OpDesc 462eventq_index=0 463opClass=FloatCmp 464opLat=5 465pipelined=true 466 467[system.cpu.fuPool.FUList4.opList22] 468type=OpDesc 469eventq_index=0 470opClass=FloatCvt 471opLat=5 472pipelined=true 473 474[system.cpu.fuPool.FUList4.opList23] 475type=OpDesc 476eventq_index=0 477opClass=FloatDiv 478opLat=9 479pipelined=false 480 481[system.cpu.fuPool.FUList4.opList24] 482type=OpDesc 483eventq_index=0 484opClass=FloatSqrt 485opLat=33 486pipelined=false 487 488[system.cpu.fuPool.FUList4.opList25] 489type=OpDesc 490eventq_index=0 491opClass=FloatMult 492opLat=4 493pipelined=true 494 495[system.cpu.icache] 496type=Cache 497children=tags 498addr_ranges=0:18446744073709551615 499assoc=2 500clk_domain=system.cpu_clk_domain 501clusivity=mostly_incl 502demand_mshr_reserve=1 503eventq_index=0 504forward_snoops=false 505hit_latency=1 506is_read_only=true 507max_miss_count=0 508mshrs=2 509prefetch_on_access=false 510prefetcher=Null 511response_latency=1 512sequential_access=false 513size=32768 514system=system 515tags=system.cpu.icache.tags 516tgts_per_mshr=8 517write_buffers=8 518writeback_clean=true 519cpu_side=system.cpu.icache_port 520mem_side=system.cpu.toL2Bus.slave[0] 521 522[system.cpu.icache.tags] 523type=LRU 524assoc=2 525block_size=64 526clk_domain=system.cpu_clk_domain 527eventq_index=0 528hit_latency=1 529sequential_access=false 530size=32768 531 532[system.cpu.interrupts] 533type=ArmInterrupts 534eventq_index=0 535 536[system.cpu.isa] 537type=ArmISA 538decoderFlavour=Generic 539eventq_index=0 540fpsid=1090793632 541id_aa64afr0_el1=0 542id_aa64afr1_el1=0 543id_aa64dfr0_el1=1052678 544id_aa64dfr1_el1=0 545id_aa64isar0_el1=0 546id_aa64isar1_el1=0 547id_aa64mmfr0_el1=15728642 548id_aa64mmfr1_el1=0 549id_aa64pfr0_el1=17 550id_aa64pfr1_el1=0 551id_isar0=34607377 552id_isar1=34677009 553id_isar2=555950401 554id_isar3=17899825 555id_isar4=268501314 556id_isar5=0 557id_mmfr0=270536963 558id_mmfr1=0 559id_mmfr2=19070976 560id_mmfr3=34611729 561id_pfr0=49 562id_pfr1=4113 563midr=1091551472 564pmu=Null 565system=system 566 567[system.cpu.istage2_mmu] 568type=ArmStage2MMU 569children=stage2_tlb 570eventq_index=0 571stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 572sys=system 573tlb=system.cpu.itb 574 575[system.cpu.istage2_mmu.stage2_tlb] 576type=ArmTLB 577children=walker 578eventq_index=0 579is_stage2=true 580size=32 581walker=system.cpu.istage2_mmu.stage2_tlb.walker 582 583[system.cpu.istage2_mmu.stage2_tlb.walker] 584type=ArmTableWalker 585clk_domain=system.cpu_clk_domain 586eventq_index=0 587is_stage2=true 588num_squash_per_cycle=2 589sys=system 590 591[system.cpu.itb] 592type=ArmTLB 593children=walker 594eventq_index=0 595is_stage2=false 596size=64 597walker=system.cpu.itb.walker 598 599[system.cpu.itb.walker] 600type=ArmTableWalker 601clk_domain=system.cpu_clk_domain 602eventq_index=0 603is_stage2=false 604num_squash_per_cycle=2 605sys=system 606port=system.cpu.toL2Bus.slave[2] 607 608[system.cpu.l2cache] 609type=Cache 610children=prefetcher tags 611addr_ranges=0:18446744073709551615 612assoc=16 613clk_domain=system.cpu_clk_domain 614clusivity=mostly_excl 615demand_mshr_reserve=1 616eventq_index=0 617forward_snoops=true 618hit_latency=12 619is_read_only=false 620max_miss_count=0 621mshrs=16 622prefetch_on_access=true 623prefetcher=system.cpu.l2cache.prefetcher 624response_latency=12 625sequential_access=false 626size=1048576 627system=system 628tags=system.cpu.l2cache.tags 629tgts_per_mshr=8 630write_buffers=8 631writeback_clean=false 632cpu_side=system.cpu.toL2Bus.master[0] 633mem_side=system.membus.slave[1] 634 635[system.cpu.l2cache.prefetcher] 636type=StridePrefetcher 637cache_snoop=false 638clk_domain=system.cpu_clk_domain 639degree=8 640eventq_index=0 641latency=1 642max_conf=7 643min_conf=0 644on_data=true 645on_inst=true 646on_miss=false 647on_read=true 648on_write=true 649queue_filter=true 650queue_size=32 651queue_squash=true 652start_conf=4 653sys=system 654table_assoc=4 655table_sets=16 656tag_prefetch=true 657thresh_conf=4 658use_master_id=true 659 660[system.cpu.l2cache.tags] 661type=RandomRepl 662assoc=16 663block_size=64 664clk_domain=system.cpu_clk_domain 665eventq_index=0 666hit_latency=12 667sequential_access=false 668size=1048576 669 670[system.cpu.toL2Bus] 671type=CoherentXBar 672children=snoop_filter 673clk_domain=system.cpu_clk_domain 674eventq_index=0 675forward_latency=0 676frontend_latency=1 677response_latency=1 678snoop_filter=system.cpu.toL2Bus.snoop_filter 679snoop_response_latency=1 680system=system 681use_default_range=false 682width=32 683master=system.cpu.l2cache.cpu_side 684slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 685 686[system.cpu.toL2Bus.snoop_filter] 687type=SnoopFilter 688eventq_index=0 689lookup_latency=0 690max_capacity=8388608 691system=system 692 693[system.cpu.tracer] 694type=ExeTracer 695eventq_index=0 696 697[system.cpu.workload] 698type=LiveProcess 699cmd=hello 700cwd= 701drivers= 702egid=100 703env= 704errout=cerr 705euid=100 706eventq_index=0 707executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello 708gid=100 709input=cin 710kvmInSE=false 711max_stack_size=67108864 712output=cout 713pid=100 714ppid=99 715simpoint=0 716system=system 717uid=100 718useArchPT=false 719 720[system.cpu_clk_domain] 721type=SrcClockDomain 722clock=500 723domain_id=-1 724eventq_index=0 725init_perf_level=0 726voltage_domain=system.voltage_domain 727 728[system.dvfs_handler] 729type=DVFSHandler 730domains= 731enable=false 732eventq_index=0 733sys_clk_domain=system.clk_domain 734transition_latency=100000000 735 736[system.membus] 737type=CoherentXBar 738clk_domain=system.clk_domain 739eventq_index=0 740forward_latency=4 741frontend_latency=3 742response_latency=2 743snoop_filter=Null 744snoop_response_latency=4 745system=system 746use_default_range=false 747width=16 748master=system.physmem.port 749slave=system.system_port system.cpu.l2cache.mem_side 750 751[system.physmem] 752type=DRAMCtrl 753IDD0=0.075000 754IDD02=0.000000 755IDD2N=0.050000 756IDD2N2=0.000000 757IDD2P0=0.000000 758IDD2P02=0.000000 759IDD2P1=0.000000 760IDD2P12=0.000000 761IDD3N=0.057000 762IDD3N2=0.000000 763IDD3P0=0.000000 764IDD3P02=0.000000 765IDD3P1=0.000000 766IDD3P12=0.000000 767IDD4R=0.187000 768IDD4R2=0.000000 769IDD4W=0.165000 770IDD4W2=0.000000 771IDD5=0.220000 772IDD52=0.000000 773IDD6=0.000000 774IDD62=0.000000 775VDD=1.500000 776VDD2=0.000000 777activation_limit=4 778addr_mapping=RoRaBaCoCh 779bank_groups_per_rank=0 780banks_per_rank=8 781burst_length=8 782channels=1 783clk_domain=system.clk_domain 784conf_table_reported=true 785device_bus_width=8 786device_rowbuffer_size=1024 787device_size=536870912 788devices_per_rank=8 789dll=true 790eventq_index=0 791in_addr_map=true 792max_accesses_per_row=16 793mem_sched_policy=frfcfs 794min_writes_per_switch=16 795null=false 796page_policy=open_adaptive 797range=0:134217727 798ranks_per_channel=2 799read_buffer_size=32 800static_backend_latency=10000 801static_frontend_latency=10000 802tBURST=5000 803tCCD_L=0 804tCK=1250 805tCL=13750 806tCS=2500 807tRAS=35000 808tRCD=13750 809tREFI=7800000 810tRFC=260000 811tRP=13750 812tRRD=6000 813tRRD_L=0 814tRTP=7500 815tRTW=2500 816tWR=15000 817tWTR=7500 818tXAW=30000 819tXP=0 820tXPDLL=0 821tXS=0 822tXSDLL=0 823write_buffer_size=64 824write_high_thresh_perc=85 825write_low_thresh_perc=50 826port=system.membus.master[0] 827 828[system.voltage_domain] 829type=VoltageDomain 830eventq_index=0 831voltage=1.000000 832 833