stats.txt revision 9978
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 41552 # Simulator instruction rate (inst/s) 8host_op_rate 51840 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 153628168 # Simulator tick rate (ticks/s) 10host_mem_usage 240508 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 392 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 392 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 86 # Per bank write bursts 43system.physmem.perBankRdBursts::1 46 # Per bank write bursts 44system.physmem.perBankRdBursts::2 20 # Per bank write bursts 45system.physmem.perBankRdBursts::3 42 # Per bank write bursts 46system.physmem.perBankRdBursts::4 17 # Per bank write bursts 47system.physmem.perBankRdBursts::5 34 # Per bank write bursts 48system.physmem.perBankRdBursts::6 35 # Per bank write bursts 49system.physmem.perBankRdBursts::7 10 # Per bank write bursts 50system.physmem.perBankRdBursts::8 4 # Per bank write bursts 51system.physmem.perBankRdBursts::9 7 # Per bank write bursts 52system.physmem.perBankRdBursts::10 28 # Per bank write bursts 53system.physmem.perBankRdBursts::11 42 # Per bank write bursts 54system.physmem.perBankRdBursts::12 9 # Per bank write bursts 55system.physmem.perBankRdBursts::13 6 # Per bank write bursts 56system.physmem.perBankRdBursts::14 0 # Per bank write bursts 57system.physmem.perBankRdBursts::15 6 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 16923500 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 392 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 155system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 178system.physmem.totQLat 3153000 # Total ticks spent queuing 179system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM 180system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 181system.physmem.totBankLat 5403750 # Total ticks spent accessing banks 182system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst 183system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst 184system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 185system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst 186system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s 187system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 188system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s 189system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 190system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 191system.physmem.busUtil 11.54 # Data bus utilization in percentage 192system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads 193system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 194system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing 195system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 196system.physmem.readRowHits 332 # Number of row buffer hits during reads 197system.physmem.writeRowHits 0 # Number of row buffer hits during writes 198system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads 199system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 200system.physmem.avgGap 43172.19 # Average gap between requests 201system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined 202system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state 203system.membus.throughput 1473647017 # Throughput (bytes/s) 204system.membus.trans_dist::ReadReq 351 # Transaction distribution 205system.membus.trans_dist::ReadResp 350 # Transaction distribution 206system.membus.trans_dist::ReadExReq 41 # Transaction distribution 207system.membus.trans_dist::ReadExResp 41 # Transaction distribution 208system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 209system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 210system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 211system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 212system.membus.data_through_bus 25024 # Total data (bytes) 213system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 214system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) 215system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 216system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) 217system.membus.respLayer1.utilization 21.5 # Layer utilization (%) 218system.cpu.branchPred.lookups 2481 # Number of BP lookups 219system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 220system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 221system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 222system.cpu.branchPred.BTBHits 697 # Number of BTB hits 223system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 224system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 225system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 226system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 227system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 228system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 229system.cpu.checker.dtb.read_hits 0 # DTB read hits 230system.cpu.checker.dtb.read_misses 0 # DTB read misses 231system.cpu.checker.dtb.write_hits 0 # DTB write hits 232system.cpu.checker.dtb.write_misses 0 # DTB write misses 233system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 234system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 235system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 236system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 237system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 238system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 239system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 240system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 241system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 242system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 243system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 244system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 245system.cpu.checker.dtb.hits 0 # DTB hits 246system.cpu.checker.dtb.misses 0 # DTB misses 247system.cpu.checker.dtb.accesses 0 # DTB accesses 248system.cpu.checker.itb.inst_hits 0 # ITB inst hits 249system.cpu.checker.itb.inst_misses 0 # ITB inst misses 250system.cpu.checker.itb.read_hits 0 # DTB read hits 251system.cpu.checker.itb.read_misses 0 # DTB read misses 252system.cpu.checker.itb.write_hits 0 # DTB write hits 253system.cpu.checker.itb.write_misses 0 # DTB write misses 254system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 255system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 256system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 257system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 258system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 259system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 260system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 261system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 262system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 263system.cpu.checker.itb.read_accesses 0 # DTB read accesses 264system.cpu.checker.itb.write_accesses 0 # DTB write accesses 265system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 266system.cpu.checker.itb.hits 0 # DTB hits 267system.cpu.checker.itb.misses 0 # DTB misses 268system.cpu.checker.itb.accesses 0 # DTB accesses 269system.cpu.workload.num_syscalls 13 # Number of system calls 270system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 271system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu.dtb.inst_hits 0 # ITB inst hits 274system.cpu.dtb.inst_misses 0 # ITB inst misses 275system.cpu.dtb.read_hits 0 # DTB read hits 276system.cpu.dtb.read_misses 0 # DTB read misses 277system.cpu.dtb.write_hits 0 # DTB write hits 278system.cpu.dtb.write_misses 0 # DTB write misses 279system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 280system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 281system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 282system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 283system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 286system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 287system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 288system.cpu.dtb.read_accesses 0 # DTB read accesses 289system.cpu.dtb.write_accesses 0 # DTB write accesses 290system.cpu.dtb.inst_accesses 0 # ITB inst accesses 291system.cpu.dtb.hits 0 # DTB hits 292system.cpu.dtb.misses 0 # DTB misses 293system.cpu.dtb.accesses 0 # DTB accesses 294system.cpu.itb.inst_hits 0 # ITB inst hits 295system.cpu.itb.inst_misses 0 # ITB inst misses 296system.cpu.itb.read_hits 0 # DTB read hits 297system.cpu.itb.read_misses 0 # DTB read misses 298system.cpu.itb.write_hits 0 # DTB write hits 299system.cpu.itb.write_misses 0 # DTB write misses 300system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 301system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 302system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 303system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 304system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 305system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 306system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 307system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 308system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 309system.cpu.itb.read_accesses 0 # DTB read accesses 310system.cpu.itb.write_accesses 0 # DTB write accesses 311system.cpu.itb.inst_accesses 0 # ITB inst accesses 312system.cpu.itb.hits 0 # DTB hits 313system.cpu.itb.misses 0 # DTB misses 314system.cpu.itb.accesses 0 # DTB accesses 315system.cpu.numCycles 33963 # number of cpu cycles simulated 316system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 317system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 318system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss 319system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 320system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 321system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 322system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 323system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 324system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked 325system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 326system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 327system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle 345system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle 346system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle 347system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked 348system.cpu.decode.RunCycles 2426 # Number of cycles decode is running 349system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 350system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 351system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 352system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 353system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 354system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 355system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 356system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle 357system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 358system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 359system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 360system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 361system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 362system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 363system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 364system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 365system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 368system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 370system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 371system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 378system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 379system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 380system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 381system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 382system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph 384system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 385system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 432system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 433system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 436system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 437system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 438system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 439system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 466system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 467system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 468system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 469system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 470system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 471system.cpu.iq.rate 0.262668 # Inst issue rate 472system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 473system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 474system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads 475system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 476system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 477system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 478system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 479system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 480system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 481system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 482system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 483system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 484system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 485system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 486system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 487system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 488system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 489system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 490system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 491system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 492system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 493system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 494system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 495system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 496system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 497system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 498system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 499system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 500system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 501system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 502system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 503system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 504system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 505system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 506system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 507system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions 508system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed 509system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 510system.cpu.iew.exec_swp 0 # number of swp insts executed 511system.cpu.iew.exec_nop 0 # number of nop insts executed 512system.cpu.iew.exec_refs 3299 # number of memory reference insts executed 513system.cpu.iew.exec_branches 1437 # Number of branches executed 514system.cpu.iew.exec_stores 1160 # Number of stores executed 515system.cpu.iew.exec_rate 0.250950 # Inst execution rate 516system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 517system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 518system.cpu.iew.wb_producers 3883 # num instructions producing a value 519system.cpu.iew.wb_consumers 7788 # num instructions consuming a value 520system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 521system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle 522system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back 523system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 524system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 525system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 526system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 527system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle 544system.cpu.commit.committedInsts 4591 # Number of instructions committed 545system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 546system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 547system.cpu.commit.refs 2138 # Number of memory references committed 548system.cpu.commit.loads 1200 # Number of loads committed 549system.cpu.commit.membars 12 # Number of memory barriers committed 550system.cpu.commit.branches 1007 # Number of branches committed 551system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 552system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 553system.cpu.commit.function_calls 82 # Number of function calls committed. 554system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 555system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 556system.cpu.rob.rob_reads 23234 # The number of ROB reads 557system.cpu.rob.rob_writes 23415 # The number of ROB writes 558system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 559system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling 560system.cpu.committedInsts 4591 # Number of Instructions Simulated 561system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 562system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 563system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 564system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 565system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 566system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 567system.cpu.int_regfile_reads 39210 # number of integer regfile reads 568system.cpu.int_regfile_writes 7985 # number of integer regfile writes 569system.cpu.fp_regfile_reads 16 # number of floating regfile reads 570system.cpu.misc_regfile_reads 2977 # number of misc regfile reads 571system.cpu.misc_regfile_writes 24 # number of misc regfile writes 572system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 573system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 584system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 585system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 586system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 587system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) 588system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 589system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) 590system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 591system.cpu.icache.tags.replacements 4 # number of replacements 592system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use 593system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 594system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 595system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 596system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 597system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor 598system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy 599system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy 600system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 601system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 602system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 603system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 604system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 605system.cpu.icache.overall_hits::total 1584 # number of overall hits 606system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 607system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 608system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 609system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 610system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 611system.cpu.icache.overall_misses::total 363 # number of overall misses 612system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles 613system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles 614system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles 615system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles 616system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles 617system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles 618system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 619system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 620system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 621system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 622system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 623system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 624system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 625system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 626system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 627system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 628system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 629system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 630system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency 631system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency 632system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 633system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency 634system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency 636system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 637system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 639system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 641system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.icache.fast_writes 0 # number of fast writes performed 643system.cpu.icache.cache_copies 0 # number of cache copies performed 644system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 645system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 646system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 647system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 648system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 649system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 650system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 651system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 653system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 654system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 655system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 656system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles 657system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 664system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 665system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 666system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 667system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 674system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cpu.l2cache.tags.replacements 0 # number of replacements 676system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use 677system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 678system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 679system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 680system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor 682system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy 686system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 687system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 688system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 689system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 690system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 691system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 692system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 693system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 694system.cpu.l2cache.overall_hits::total 40 # number of overall hits 695system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 696system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 697system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 698system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 699system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 700system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 701system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 702system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 703system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 704system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 705system.cpu.l2cache.overall_misses::total 397 # number of overall misses 706system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles 707system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles 708system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles 709system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles 710system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles 711system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles 712system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles 713system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles 714system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles 715system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles 716system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles 717system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 718system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 719system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 720system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 721system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 722system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 723system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 724system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 725system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 726system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 727system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 730system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 731system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 732system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 733system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 734system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 735system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 736system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 737system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 738system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency 740system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency 741system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency 742system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency 743system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 746system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency 750system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.l2cache.fast_writes 0 # number of fast writes performed 757system.cpu.l2cache.cache_copies 0 # number of cache copies performed 758system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 759system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 760system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 761system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 762system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 763system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 764system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 765system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 766system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 767system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 768system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 769system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 770system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 771system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 772system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 773system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 774system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 775system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles 776system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles 777system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles 778system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles 779system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles 780system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles 782system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles 783system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles 784system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles 785system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles 786system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 788system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 789system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 791system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 792system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 793system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 794system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 795system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 796system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 797system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency 798system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency 799system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency 800system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency 801system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 804system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 807system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 808system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 809system.cpu.dcache.tags.replacements 0 # number of replacements 810system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. 812system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 813system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. 814system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 815system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy 818system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 819system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 820system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 821system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 822system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 823system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 824system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 825system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 826system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 827system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 828system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 829system.cpu.dcache.overall_hits::total 2373 # number of overall hits 830system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 831system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 832system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 833system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 834system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 835system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 836system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 839system.cpu.dcache.overall_misses::total 496 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles 844system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 845system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 846system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles 847system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles 848system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles 849system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles 850system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 851system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 852system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 853system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 854system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 855system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 856system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 857system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 858system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 859system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 860system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 861system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 862system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 863system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 864system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 865system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 866system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 867system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 868system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 869system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 870system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 871system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 872system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency 873system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency 874system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency 875system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency 876system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 877system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 878system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 879system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency 880system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 881system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency 882system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 883system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 884system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 885system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 886system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 887system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 888system.cpu.dcache.fast_writes 0 # number of fast writes performed 889system.cpu.dcache.cache_copies 0 # number of cache copies performed 890system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 891system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 892system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 893system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 894system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 895system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 896system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 897system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 898system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 899system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 900system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 901system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 902system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 903system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 904system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 905system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 906system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 907system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 908system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles 909system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles 910system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles 911system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles 912system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles 913system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles 914system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles 915system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles 916system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 917system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 918system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 919system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 920system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 921system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 922system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 923system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 924system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency 925system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency 926system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency 927system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency 928system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 929system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 930system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 931system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 932system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 933 934---------- End Simulation Statistics ---------- 935