stats.txt revision 9620:89aa34e10625
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000014 # Number of seconds simulated 4sim_ticks 13706000 # Number of ticks simulated 5final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 599 # Simulator instruction rate (inst/s) 8host_op_rate 748 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1788642 # Simulator tick rate (ticks/s) 10host_mem_usage 284080 # Number of bytes of host memory used 11host_seconds 7.66 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 394 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 13648500 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 394 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.totQLat 2507750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests 154system.physmem.totBusLat 1970000 # Total cycles spent in databus access 155system.physmem.totBankLat 7273750 # Total cycles spent in bank access 156system.physmem.avgQLat 6364.85 # Average queueing delay per request 157system.physmem.avgBankLat 18461.29 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request 159system.physmem.avgMemAccLat 29826.14 # Average memory access latency 160system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 14.37 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.86 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 294 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 172system.physmem.avgGap 34640.86 # Average gap between requests 173system.cpu.branchPred.lookups 2491 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 700 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 182system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 183system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 184system.cpu.checker.dtb.read_hits 0 # DTB read hits 185system.cpu.checker.dtb.read_misses 0 # DTB read misses 186system.cpu.checker.dtb.write_hits 0 # DTB write hits 187system.cpu.checker.dtb.write_misses 0 # DTB write misses 188system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 189system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 190system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 191system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 192system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 193system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 194system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 195system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 196system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 197system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 198system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 199system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 200system.cpu.checker.dtb.hits 0 # DTB hits 201system.cpu.checker.dtb.misses 0 # DTB misses 202system.cpu.checker.dtb.accesses 0 # DTB accesses 203system.cpu.checker.itb.inst_hits 0 # ITB inst hits 204system.cpu.checker.itb.inst_misses 0 # ITB inst misses 205system.cpu.checker.itb.read_hits 0 # DTB read hits 206system.cpu.checker.itb.read_misses 0 # DTB read misses 207system.cpu.checker.itb.write_hits 0 # DTB write hits 208system.cpu.checker.itb.write_misses 0 # DTB write misses 209system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 210system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 211system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 212system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 213system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 214system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 215system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 216system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 217system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 218system.cpu.checker.itb.read_accesses 0 # DTB read accesses 219system.cpu.checker.itb.write_accesses 0 # DTB write accesses 220system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 221system.cpu.checker.itb.hits 0 # DTB hits 222system.cpu.checker.itb.misses 0 # DTB misses 223system.cpu.checker.itb.accesses 0 # DTB accesses 224system.cpu.workload.num_syscalls 13 # Number of system calls 225system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 226system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 227system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 228system.cpu.dtb.inst_hits 0 # ITB inst hits 229system.cpu.dtb.inst_misses 0 # ITB inst misses 230system.cpu.dtb.read_hits 0 # DTB read hits 231system.cpu.dtb.read_misses 0 # DTB read misses 232system.cpu.dtb.write_hits 0 # DTB write hits 233system.cpu.dtb.write_misses 0 # DTB write misses 234system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 235system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 236system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 237system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 238system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 239system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 240system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 241system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 242system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 243system.cpu.dtb.read_accesses 0 # DTB read accesses 244system.cpu.dtb.write_accesses 0 # DTB write accesses 245system.cpu.dtb.inst_accesses 0 # ITB inst accesses 246system.cpu.dtb.hits 0 # DTB hits 247system.cpu.dtb.misses 0 # DTB misses 248system.cpu.dtb.accesses 0 # DTB accesses 249system.cpu.itb.inst_hits 0 # ITB inst hits 250system.cpu.itb.inst_misses 0 # ITB inst misses 251system.cpu.itb.read_hits 0 # DTB read hits 252system.cpu.itb.read_misses 0 # DTB read misses 253system.cpu.itb.write_hits 0 # DTB write hits 254system.cpu.itb.write_misses 0 # DTB write misses 255system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 256system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 257system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 258system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 259system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 260system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 261system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 262system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 263system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 264system.cpu.itb.read_accesses 0 # DTB read accesses 265system.cpu.itb.write_accesses 0 # DTB write accesses 266system.cpu.itb.inst_accesses 0 # ITB inst accesses 267system.cpu.itb.hits 0 # DTB hits 268system.cpu.itb.misses 0 # DTB misses 269system.cpu.itb.accesses 0 # DTB accesses 270system.cpu.numCycles 27413 # number of cpu cycles simulated 271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss 274system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed 275system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered 276system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken 277system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked 278system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing 279system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked 280system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched 281system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed 282system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle 300system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle 301system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle 302system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked 303system.cpu.decode.RunCycles 2438 # Number of cycles decode is running 304system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 305system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing 306system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch 307system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 308system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode 309system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 310system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing 311system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle 312system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking 313system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst 314system.cpu.rename.RunCycles 2238 # Number of cycles rename is running 315system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 316system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename 317system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 318system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 319system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full 320system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed 321system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made 322system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups 323system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 324system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 325system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing 326system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 327system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 328system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer 329system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. 330system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. 331system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 332system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 333system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) 334system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 335system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued 336system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued 337system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling 338system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph 339system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 340system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle 357system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 358system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available 359system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available 387system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available 388system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available 389system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 390system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 391system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 392system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued 393system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued 394system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued 421system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued 422system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued 423system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 424system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::total 8967 # Type of FU issued 426system.cpu.iq.rate 0.327108 # Inst issue rate 427system.cpu.iq.fu_busy_cnt 230 # FU busy when requested 428system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) 429system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads 430system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes 431system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses 432system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 433system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 434system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 435system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses 436system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 437system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 438system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 439system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed 440system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 441system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations 442system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed 443system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 444system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 445system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 446system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 447system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 448system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing 449system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 450system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 451system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ 452system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch 453system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions 454system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions 455system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 456system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 457system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 458system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations 459system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 460system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly 461system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute 462system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions 463system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed 464system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute 465system.cpu.iew.exec_swp 0 # number of swp insts executed 466system.cpu.iew.exec_nop 0 # number of nop insts executed 467system.cpu.iew.exec_refs 3301 # number of memory reference insts executed 468system.cpu.iew.exec_branches 1438 # Number of branches executed 469system.cpu.iew.exec_stores 1167 # Number of stores executed 470system.cpu.iew.exec_rate 0.311713 # Inst execution rate 471system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit 472system.cpu.iew.wb_count 8089 # cumulative count of insts written-back 473system.cpu.iew.wb_producers 3894 # num instructions producing a value 474system.cpu.iew.wb_consumers 7825 # num instructions consuming a value 475system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 476system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle 477system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back 478system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 479system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit 480system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 481system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 482system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle 499system.cpu.commit.committedInsts 4591 # Number of instructions committed 500system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 501system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 502system.cpu.commit.refs 2138 # Number of memory references committed 503system.cpu.commit.loads 1200 # Number of loads committed 504system.cpu.commit.membars 12 # Number of memory barriers committed 505system.cpu.commit.branches 1007 # Number of branches committed 506system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 507system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 508system.cpu.commit.function_calls 82 # Number of function calls committed. 509system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 510system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 511system.cpu.rob.rob_reads 23047 # The number of ROB reads 512system.cpu.rob.rob_writes 23560 # The number of ROB writes 513system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself 514system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling 515system.cpu.committedInsts 4591 # Number of Instructions Simulated 516system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 517system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 518system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction 519system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads 520system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle 521system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads 522system.cpu.int_regfile_reads 39296 # number of integer regfile reads 523system.cpu.int_regfile_writes 8001 # number of integer regfile writes 524system.cpu.fp_regfile_reads 16 # number of floating regfile reads 525system.cpu.misc_regfile_reads 2981 # number of misc regfile reads 526system.cpu.misc_regfile_writes 24 # number of misc regfile writes 527system.cpu.icache.replacements 3 # number of replacements 528system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use 529system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. 530system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. 531system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. 532system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 533system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor 534system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy 535system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy 536system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits 537system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits 538system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits 539system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits 540system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits 541system.cpu.icache.overall_hits::total 1590 # number of overall hits 542system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses 543system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses 544system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses 545system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses 546system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses 547system.cpu.icache.overall_misses::total 360 # number of overall misses 548system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles 549system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles 550system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles 551system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles 552system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles 553system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles 554system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) 555system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) 556system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses 557system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses 558system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses 559system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses 560system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses 561system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses 562system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses 563system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses 564system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses 565system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses 566system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency 567system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency 568system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency 569system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency 570system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency 571system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency 572system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked 573system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 574system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 575system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 576system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked 577system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 578system.cpu.icache.fast_writes 0 # number of fast writes performed 579system.cpu.icache.cache_copies 0 # number of cache copies performed 580system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits 581system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 582system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits 583system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 584system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits 585system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits 586system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 587system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 588system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 589system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 590system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 591system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses 592system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles 593system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles 594system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles 595system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles 596system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles 597system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles 598system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses 599system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses 600system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses 601system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses 602system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses 603system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses 604system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency 605system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency 606system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency 607system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency 608system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency 609system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency 610system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 611system.cpu.l2cache.replacements 0 # number of replacements 612system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use 613system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. 614system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 615system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. 616system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 617system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor 618system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor 619system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy 620system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy 621system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy 622system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 623system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 624system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 625system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 626system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 627system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 628system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 629system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 630system.cpu.l2cache.overall_hits::total 39 # number of overall hits 631system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 632system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 633system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 634system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 635system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 636system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 637system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 638system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 639system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 640system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 641system.cpu.l2cache.overall_misses::total 399 # number of overall misses 642system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles 643system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles 644system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # number of ReadReq miss cycles 645system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles 646system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles 647system.cpu.l2cache.demand_miss_latency::cpu.inst 14110000 # number of demand (read+write) miss cycles 648system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles 649system.cpu.l2cache.demand_miss_latency::total 21480500 # number of demand (read+write) miss cycles 650system.cpu.l2cache.overall_miss_latency::cpu.inst 14110000 # number of overall miss cycles 651system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles 652system.cpu.l2cache.overall_miss_latency::total 21480500 # number of overall miss cycles 653system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 654system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 655system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 656system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 657system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 658system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 659system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 660system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 661system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 662system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 663system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses 664system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 666system.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses 667system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 668system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 669system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses 670system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 671system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses 672system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses 673system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 674system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses 675system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency 676system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency 677system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # average ReadReq miss latency 678system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency 679system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency 680system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51875 # average overall miss latency 681system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency 682system.cpu.l2cache.demand_avg_miss_latency::total 53835.839599 # average overall miss latency 683system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51875 # average overall miss latency 684system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency 685system.cpu.l2cache.overall_avg_miss_latency::total 53835.839599 # average overall miss latency 686system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 687system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 688system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 689system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 690system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 691system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 692system.cpu.l2cache.fast_writes 0 # number of fast writes performed 693system.cpu.l2cache.cache_copies 0 # number of cache copies performed 694system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 695system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 696system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 697system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 698system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 699system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 700system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 701system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 702system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 703system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 704system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 705system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 706system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 707system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 708system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 709system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 710system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 711system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735459 # number of ReadReq MSHR miss cycles 712system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles 713system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14491743 # number of ReadReq MSHR miss cycles 714system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles 715system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles 716system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735459 # number of demand (read+write) MSHR miss cycles 717system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles 718system.cpu.l2cache.demand_mshr_miss_latency::total 16388514 # number of demand (read+write) MSHR miss cycles 719system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735459 # number of overall MSHR miss cycles 720system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles 721system.cpu.l2cache.overall_mshr_miss_latency::total 16388514 # number of overall MSHR miss cycles 722system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses 723system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 724system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses 725system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 726system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 727system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses 728system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 729system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses 730system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses 731system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 732system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39468.599265 # average ReadReq mshr miss latency 734system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency 735system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41053.096317 # average ReadReq mshr miss latency 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.dcache.replacements 0 # number of replacements 746system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use 747system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. 750system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 762system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits 765system.cpu.dcache.overall_hits::total 2369 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 772system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses 775system.cpu.dcache.overall_misses::total 500 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 794system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed 826system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits 827system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits 828system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 829system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 830system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 831system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 832system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits 833system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits 834system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits 835system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits 836system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 837system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 838system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 839system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 840system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 841system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 842system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 843system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 844system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles 845system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles 846system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles 847system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles 848system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles 849system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles 850system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles 851system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles 852system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 857system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 858system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 859system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency 861system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency 862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency 863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency 864system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency 865system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency 866system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency 867system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency 868system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 869 870---------- End Simulation Statistics ---------- 871