stats.txt revision 9285:9901180cd573
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10412000 # Number of ticks simulated 5final_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 32172 # Simulator instruction rate (inst/s) 8host_op_rate 40134 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 72868464 # Simulator tick rate (ticks/s) 10host_mem_usage 233868 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host 12sim_insts 4596 # Number of instructions simulated 13sim_ops 5734 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25600 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 400 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 31system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 32system.cpu.checker.dtb.read_hits 0 # DTB read hits 33system.cpu.checker.dtb.read_misses 0 # DTB read misses 34system.cpu.checker.dtb.write_hits 0 # DTB write hits 35system.cpu.checker.dtb.write_misses 0 # DTB write misses 36system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 46system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 47system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.checker.dtb.hits 0 # DTB hits 49system.cpu.checker.dtb.misses 0 # DTB misses 50system.cpu.checker.dtb.accesses 0 # DTB accesses 51system.cpu.checker.itb.inst_hits 0 # ITB inst hits 52system.cpu.checker.itb.inst_misses 0 # ITB inst misses 53system.cpu.checker.itb.read_hits 0 # DTB read hits 54system.cpu.checker.itb.read_misses 0 # DTB read misses 55system.cpu.checker.itb.write_hits 0 # DTB write hits 56system.cpu.checker.itb.write_misses 0 # DTB write misses 57system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.checker.itb.read_accesses 0 # DTB read accesses 67system.cpu.checker.itb.write_accesses 0 # DTB write accesses 68system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.checker.itb.hits 0 # DTB hits 70system.cpu.checker.itb.misses 0 # DTB misses 71system.cpu.checker.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 13 # Number of system calls 73system.cpu.checker.numCycles 5747 # number of cpu cycles simulated 74system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.dtb.inst_hits 0 # ITB inst hits 77system.cpu.dtb.inst_misses 0 # ITB inst misses 78system.cpu.dtb.read_hits 0 # DTB read hits 79system.cpu.dtb.read_misses 0 # DTB read misses 80system.cpu.dtb.write_hits 0 # DTB write hits 81system.cpu.dtb.write_misses 0 # DTB write misses 82system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 84system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 86system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 87system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 88system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 89system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.dtb.read_accesses 0 # DTB read accesses 92system.cpu.dtb.write_accesses 0 # DTB write accesses 93system.cpu.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.dtb.hits 0 # DTB hits 95system.cpu.dtb.misses 0 # DTB misses 96system.cpu.dtb.accesses 0 # DTB accesses 97system.cpu.itb.inst_hits 0 # ITB inst hits 98system.cpu.itb.inst_misses 0 # ITB inst misses 99system.cpu.itb.read_hits 0 # DTB read hits 100system.cpu.itb.read_misses 0 # DTB read misses 101system.cpu.itb.write_hits 0 # DTB write hits 102system.cpu.itb.write_misses 0 # DTB write misses 103system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 104system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 105system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 106system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 107system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 108system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 109system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 110system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 111system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 112system.cpu.itb.read_accesses 0 # DTB read accesses 113system.cpu.itb.write_accesses 0 # DTB write accesses 114system.cpu.itb.inst_accesses 0 # ITB inst accesses 115system.cpu.itb.hits 0 # DTB hits 116system.cpu.itb.misses 0 # DTB misses 117system.cpu.itb.accesses 0 # DTB accesses 118system.cpu.numCycles 20825 # number of cpu cycles simulated 119system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 120system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 121system.cpu.BPredUnit.lookups 2492 # Number of BP lookups 122system.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted 123system.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect 124system.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups 125system.cpu.BPredUnit.BTBHits 699 # Number of BTB hits 126system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 127system.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. 128system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. 129system.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss 130system.cpu.fetch.Insts 12176 # Number of instructions fetch has processed 131system.cpu.fetch.Branches 2492 # Number of branches that fetch encountered 132system.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken 133system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked 134system.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing 135system.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked 136system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 137system.cpu.fetch.CacheLines 1932 # Number of cache lines fetched 138system.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed 139system.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) 140system.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) 141system.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) 142system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 143system.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) 144system.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) 145system.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) 146system.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) 147system.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) 148system.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) 149system.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) 150system.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) 151system.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) 152system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 153system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 154system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 155system.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) 156system.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle 157system.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle 158system.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle 159system.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked 160system.cpu.decode.RunCycles 2432 # Number of cycles decode is running 161system.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking 162system.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing 163system.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch 164system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 165system.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode 166system.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode 167system.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing 168system.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle 169system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking 170system.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst 171system.cpu.rename.RunCycles 2229 # Number of cycles rename is running 172system.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking 173system.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename 174system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full 175system.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full 176system.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed 177system.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made 178system.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups 179system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups 180system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 181system.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing 182system.cpu.rename.serializingInsts 47 # count of serializing insts renamed 183system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed 184system.cpu.rename.skidInsts 672 # count of insts added to the skid buffer 185system.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. 186system.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. 187system.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. 188system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. 189system.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) 190system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ 191system.cpu.iq.iqInstsIssued 8838 # Number of instructions issued 192system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 193system.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling 194system.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph 195system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 196system.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle 197system.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle 198system.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle 199system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 200system.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle 201system.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle 202system.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle 203system.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle 204system.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle 205system.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle 206system.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle 207system.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle 208system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle 209system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 210system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 211system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 212system.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle 213system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 214system.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available 215system.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available 216system.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available 217system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available 218system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available 219system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available 220system.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available 221system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available 222system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available 223system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available 224system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available 225system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available 226system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available 227system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available 228system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available 229system.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available 230system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available 231system.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available 232system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available 233system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available 234system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available 235system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available 236system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available 237system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available 238system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available 239system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available 240system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available 241system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available 242system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available 243system.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available 244system.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available 245system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 246system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 247system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 248system.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued 249system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued 250system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued 251system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued 252system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued 253system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued 254system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued 255system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued 256system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued 257system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued 258system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued 259system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued 260system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued 261system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued 262system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued 263system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued 264system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued 265system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued 266system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued 267system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued 268system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued 269system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued 270system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued 271system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued 272system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued 273system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued 274system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued 275system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued 276system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued 277system.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued 278system.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued 279system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 280system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 281system.cpu.iq.FU_type_0::total 8838 # Type of FU issued 282system.cpu.iq.rate 0.424394 # Inst issue rate 283system.cpu.iq.fu_busy_cnt 221 # FU busy when requested 284system.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) 285system.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads 286system.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes 287system.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses 288system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 289system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 290system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 291system.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses 292system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 293system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores 294system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 295system.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed 296system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 297system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 298system.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed 299system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 300system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 301system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 302system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 303system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 304system.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing 305system.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking 306system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking 307system.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ 308system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch 309system.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions 310system.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions 311system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions 312system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall 313system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 314system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 315system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 316system.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly 317system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute 318system.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions 319system.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed 320system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute 321system.cpu.iew.exec_swp 0 # number of swp insts executed 322system.cpu.iew.exec_nop 0 # number of nop insts executed 323system.cpu.iew.exec_refs 3246 # number of memory reference insts executed 324system.cpu.iew.exec_branches 1415 # Number of branches executed 325system.cpu.iew.exec_stores 1167 # Number of stores executed 326system.cpu.iew.exec_rate 0.404994 # Inst execution rate 327system.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit 328system.cpu.iew.wb_count 7997 # cumulative count of insts written-back 329system.cpu.iew.wb_producers 3850 # num instructions producing a value 330system.cpu.iew.wb_consumers 7766 # num instructions consuming a value 331system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 332system.cpu.iew.wb_rate 0.384010 # insts written-back per cycle 333system.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back 334system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 335system.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit 336system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 337system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 338system.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle 339system.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle 340system.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle 341system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 342system.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle 343system.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle 344system.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle 345system.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle 346system.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle 347system.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle 348system.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle 349system.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle 350system.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle 351system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 352system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 353system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 354system.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle 355system.cpu.commit.committedInsts 4596 # Number of instructions committed 356system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed 357system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 358system.cpu.commit.refs 2140 # Number of memory references committed 359system.cpu.commit.loads 1201 # Number of loads committed 360system.cpu.commit.membars 12 # Number of memory barriers committed 361system.cpu.commit.branches 1008 # Number of branches committed 362system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 363system.cpu.commit.int_insts 4980 # Number of committed integer instructions. 364system.cpu.commit.function_calls 82 # Number of function calls committed. 365system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached 366system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 367system.cpu.rob.rob_reads 22290 # The number of ROB reads 368system.cpu.rob.rob_writes 23328 # The number of ROB writes 369system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself 370system.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling 371system.cpu.committedInsts 4596 # Number of Instructions Simulated 372system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 373system.cpu.committedInsts_total 4596 # Number of Instructions Simulated 374system.cpu.cpi 4.531114 # CPI: Cycles Per Instruction 375system.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads 376system.cpu.ipc 0.220696 # IPC: Instructions Per Cycle 377system.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads 378system.cpu.int_regfile_reads 38756 # number of integer regfile reads 379system.cpu.int_regfile_writes 7886 # number of integer regfile writes 380system.cpu.fp_regfile_reads 16 # number of floating regfile reads 381system.cpu.misc_regfile_reads 15116 # number of misc regfile reads 382system.cpu.misc_regfile_writes 26 # number of misc regfile writes 383system.cpu.icache.replacements 3 # number of replacements 384system.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use 385system.cpu.icache.total_refs 1564 # Total number of references to valid blocks. 386system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 387system.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. 388system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 389system.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor 390system.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy 391system.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy 392system.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits 393system.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits 394system.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits 395system.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits 396system.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits 397system.cpu.icache.overall_hits::total 1564 # number of overall hits 398system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 399system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 400system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 401system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 402system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 403system.cpu.icache.overall_misses::total 368 # number of overall misses 404system.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles 405system.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles 406system.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles 407system.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles 408system.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles 409system.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles 410system.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) 411system.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) 412system.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses 413system.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses 414system.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses 415system.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses 416system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses 417system.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses 418system.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses 419system.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses 420system.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses 421system.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses 422system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency 423system.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency 424system.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency 425system.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency 426system.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency 427system.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency 428system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 429system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 430system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 431system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 432system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 433system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 434system.cpu.icache.fast_writes 0 # number of fast writes performed 435system.cpu.icache.cache_copies 0 # number of cache copies performed 436system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits 437system.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 438system.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits 439system.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 440system.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits 441system.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits 442system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 443system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 444system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 445system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 446system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 447system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 448system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles 449system.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles 450system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles 451system.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles 452system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles 453system.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles 454system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses 455system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses 456system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses 457system.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses 458system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses 459system.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses 460system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency 461system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency 462system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency 463system.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency 464system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency 465system.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency 466system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 467system.cpu.dcache.replacements 0 # number of replacements 468system.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use 469system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. 470system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. 471system.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. 472system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 473system.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor 474system.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy 475system.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy 476system.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits 477system.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits 478system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 479system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 480system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 481system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 482system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 483system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 484system.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits 485system.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits 486system.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits 487system.cpu.dcache.overall_hits::total 2306 # number of overall hits 488system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses 489system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses 490system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 491system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 492system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 493system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 494system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses 495system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses 496system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses 497system.cpu.dcache.overall_misses::total 502 # number of overall misses 498system.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles 499system.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles 500system.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles 501system.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles 502system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles 503system.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles 504system.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles 505system.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles 506system.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles 507system.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles 508system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) 509system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) 510system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 511system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 512system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 513system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 514system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 515system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 516system.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses 517system.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses 518system.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses 519system.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses 520system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses 521system.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses 522system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 523system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 524system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 525system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 526system.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses 527system.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses 528system.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses 529system.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses 530system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency 531system.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency 532system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency 533system.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency 534system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency 535system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency 536system.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency 537system.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency 538system.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency 539system.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency 540system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 541system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 542system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 543system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 544system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 545system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 546system.cpu.dcache.fast_writes 0 # number of fast writes performed 547system.cpu.dcache.cache_copies 0 # number of cache copies performed 548system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 549system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 550system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 551system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 552system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 553system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 554system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 555system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 556system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 557system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 558system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 559system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 560system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 561system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 562system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 563system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 564system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 565system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 566system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles 567system.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles 568system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles 569system.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles 570system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles 571system.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles 572system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles 573system.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles 574system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses 575system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses 576system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 577system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 578system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses 579system.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses 580system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses 581system.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses 582system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency 583system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency 584system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency 585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency 586system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency 587system.cpu.dcache.demand_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency 588system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency 589system.cpu.dcache.overall_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency 590system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 591system.cpu.l2cache.replacements 0 # number of replacements 592system.cpu.l2cache.tagsinuse 188.003042 # Cycle average of tags in use 593system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. 594system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. 595system.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks. 596system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 597system.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor 598system.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor 599system.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy 600system.cpu.l2cache.occ_percent::cpu.data 0.001413 # Average percentage of cache occupancy 601system.cpu.l2cache.occ_percent::total 0.005737 # Average percentage of cache occupancy 602system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 603system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 604system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits 605system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 606system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 607system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits 608system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 609system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 610system.cpu.l2cache.overall_hits::total 37 # number of overall hits 611system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 612system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 613system.cpu.l2cache.ReadReq_misses::total 364 # number of ReadReq misses 614system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 615system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 616system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 617system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 618system.cpu.l2cache.demand_misses::total 406 # number of demand (read+write) misses 619system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses 620system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 621system.cpu.l2cache.overall_misses::total 406 # number of overall misses 622system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10097000 # number of ReadReq miss cycles 623system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3413000 # number of ReadReq miss cycles 624system.cpu.l2cache.ReadReq_miss_latency::total 13510000 # number of ReadReq miss cycles 625system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1657000 # number of ReadExReq miss cycles 626system.cpu.l2cache.ReadExReq_miss_latency::total 1657000 # number of ReadExReq miss cycles 627system.cpu.l2cache.demand_miss_latency::cpu.inst 10097000 # number of demand (read+write) miss cycles 628system.cpu.l2cache.demand_miss_latency::cpu.data 5070000 # number of demand (read+write) miss cycles 629system.cpu.l2cache.demand_miss_latency::total 15167000 # number of demand (read+write) miss cycles 630system.cpu.l2cache.overall_miss_latency::cpu.inst 10097000 # number of overall miss cycles 631system.cpu.l2cache.overall_miss_latency::cpu.data 5070000 # number of overall miss cycles 632system.cpu.l2cache.overall_miss_latency::total 15167000 # number of overall miss cycles 633system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 634system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 635system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 636system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 637system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 638system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 639system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 640system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses 641system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 642system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 643system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses 644system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses 645system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses 647system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 648system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 649system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses 650system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 651system.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses 652system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses 653system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 654system.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses 655system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency 656system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency 657system.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency 658system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency 659system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency 660system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency 661system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency 662system.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency 663system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency 664system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency 665system.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency 666system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 667system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 668system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 669system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 670system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 671system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 672system.cpu.l2cache.fast_writes 0 # number of fast writes performed 673system.cpu.l2cache.cache_copies 0 # number of cache copies performed 674system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 675system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 676system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 677system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 678system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 679system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 680system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 681system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 682system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 683system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses 684system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 685system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses 686system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 687system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 688system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 689system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses 690system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses 691system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 692system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses 693system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses 694system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles 695system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles 696system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles 697system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles 698system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles 699system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles 700system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles 701system.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles 702system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles 703system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles 704system.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles 705system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses 706system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses 707system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses 708system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 709system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 710system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses 711system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses 712system.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses 713system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses 714system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses 715system.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses 716system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency 717system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency 718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency 719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency 720system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency 721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency 722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency 723system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency 724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency 725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency 726system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency 727system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 728 729---------- End Simulation Statistics ---------- 730