stats.txt revision 8889:2e38fd9937a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10389500 # Number of ticks simulated 5final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3665 # Simulator instruction rate (inst/s) 8host_op_rate 4572 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8277068 # Simulator tick rate (ticks/s) 10host_mem_usage 225396 # Number of bytes of host memory used 11host_seconds 1.26 # Real time elapsed on the host 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 25600 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 400 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 24system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 25system.cpu.checker.dtb.read_hits 0 # DTB read hits 26system.cpu.checker.dtb.read_misses 0 # DTB read misses 27system.cpu.checker.dtb.write_hits 0 # DTB write hits 28system.cpu.checker.dtb.write_misses 0 # DTB write misses 29system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 34system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 37system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 39system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 40system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 41system.cpu.checker.dtb.hits 0 # DTB hits 42system.cpu.checker.dtb.misses 0 # DTB misses 43system.cpu.checker.dtb.accesses 0 # DTB accesses 44system.cpu.checker.itb.inst_hits 0 # ITB inst hits 45system.cpu.checker.itb.inst_misses 0 # ITB inst misses 46system.cpu.checker.itb.read_hits 0 # DTB read hits 47system.cpu.checker.itb.read_misses 0 # DTB read misses 48system.cpu.checker.itb.write_hits 0 # DTB write hits 49system.cpu.checker.itb.write_misses 0 # DTB write misses 50system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.checker.itb.read_accesses 0 # DTB read accesses 60system.cpu.checker.itb.write_accesses 0 # DTB write accesses 61system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 62system.cpu.checker.itb.hits 0 # DTB hits 63system.cpu.checker.itb.misses 0 # DTB misses 64system.cpu.checker.itb.accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 13 # Number of system calls 66system.cpu.checker.numCycles 5752 # number of cpu cycles simulated 67system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.dtb.inst_hits 0 # ITB inst hits 70system.cpu.dtb.inst_misses 0 # ITB inst misses 71system.cpu.dtb.read_hits 0 # DTB read hits 72system.cpu.dtb.read_misses 0 # DTB read misses 73system.cpu.dtb.write_hits 0 # DTB write hits 74system.cpu.dtb.write_misses 0 # DTB write misses 75system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dtb.read_accesses 0 # DTB read accesses 85system.cpu.dtb.write_accesses 0 # DTB write accesses 86system.cpu.dtb.inst_accesses 0 # ITB inst accesses 87system.cpu.dtb.hits 0 # DTB hits 88system.cpu.dtb.misses 0 # DTB misses 89system.cpu.dtb.accesses 0 # DTB accesses 90system.cpu.itb.inst_hits 0 # ITB inst hits 91system.cpu.itb.inst_misses 0 # ITB inst misses 92system.cpu.itb.read_hits 0 # DTB read hits 93system.cpu.itb.read_misses 0 # DTB read misses 94system.cpu.itb.write_hits 0 # DTB write hits 95system.cpu.itb.write_misses 0 # DTB write misses 96system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.itb.read_accesses 0 # DTB read accesses 106system.cpu.itb.write_accesses 0 # DTB write accesses 107system.cpu.itb.inst_accesses 0 # ITB inst accesses 108system.cpu.itb.hits 0 # DTB hits 109system.cpu.itb.misses 0 # DTB misses 110system.cpu.itb.accesses 0 # DTB accesses 111system.cpu.numCycles 20780 # number of cpu cycles simulated 112system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 113system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 114system.cpu.BPredUnit.lookups 2550 # Number of BP lookups 115system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted 116system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect 117system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups 118system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits 119system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 120system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. 121system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. 122system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss 123system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed 124system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered 125system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken 126system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked 127system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing 128system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked 129system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 130system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 131system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched 132system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed 133system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) 134system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) 135system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) 136system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 137system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) 138system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) 139system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) 140system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) 141system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) 142system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) 143system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) 144system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) 145system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) 146system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 147system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 148system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 149system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) 150system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle 151system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle 152system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle 153system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked 154system.cpu.decode.RunCycles 2634 # Number of cycles decode is running 155system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking 156system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing 157system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch 158system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction 159system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode 160system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode 161system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing 162system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle 163system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking 164system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst 165system.cpu.rename.RunCycles 2397 # Number of cycles rename is running 166system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking 167system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename 168system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full 169system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full 170system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed 171system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made 172system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups 173system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups 174system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed 175system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing 176system.cpu.rename.serializingInsts 48 # count of serializing insts renamed 177system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed 178system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer 179system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. 180system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. 181system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. 182system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. 183system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) 184system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ 185system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued 186system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued 187system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling 188system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph 189system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed 190system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle 191system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle 192system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle 193system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 194system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle 195system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle 196system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle 197system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle 198system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle 199system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle 200system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle 201system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle 202system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle 203system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 204system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 205system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 206system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle 207system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 208system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available 209system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available 210system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available 211system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available 212system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available 213system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available 214system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available 215system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available 216system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available 217system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available 218system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available 219system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available 220system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available 221system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available 222system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available 223system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available 224system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available 225system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available 226system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available 227system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available 228system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available 229system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available 230system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available 231system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available 232system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available 233system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available 234system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available 235system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available 236system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available 237system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available 238system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available 239system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 240system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 241system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 242system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued 243system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued 244system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued 245system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued 246system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued 247system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued 248system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued 249system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued 250system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued 251system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued 252system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued 253system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued 254system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued 255system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued 256system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued 257system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued 258system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued 259system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued 260system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued 261system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued 262system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued 263system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued 264system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued 265system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued 266system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued 267system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued 268system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued 269system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued 270system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued 271system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued 272system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued 273system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 274system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 275system.cpu.iq.FU_type_0::total 9138 # Type of FU issued 276system.cpu.iq.rate 0.439750 # Inst issue rate 277system.cpu.iq.fu_busy_cnt 215 # FU busy when requested 278system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) 279system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads 280system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes 281system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses 282system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 283system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 284system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 285system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses 286system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 287system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 288system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 289system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed 290system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 291system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 292system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed 293system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 294system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 295system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 296system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 297system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 298system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing 299system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking 300system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking 301system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ 302system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch 303system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions 304system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions 305system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions 306system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 307system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 308system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 309system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly 310system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly 311system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute 312system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions 313system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed 314system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute 315system.cpu.iew.exec_swp 0 # number of swp insts executed 316system.cpu.iew.exec_nop 1 # number of nop insts executed 317system.cpu.iew.exec_refs 3325 # number of memory reference insts executed 318system.cpu.iew.exec_branches 1404 # Number of branches executed 319system.cpu.iew.exec_stores 1195 # Number of stores executed 320system.cpu.iew.exec_rate 0.415544 # Inst execution rate 321system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit 322system.cpu.iew.wb_count 8156 # cumulative count of insts written-back 323system.cpu.iew.wb_producers 3863 # num instructions producing a value 324system.cpu.iew.wb_consumers 7813 # num instructions consuming a value 325system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 326system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle 327system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back 328system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 329system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions 330system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions 331system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit 332system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 333system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted 334system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle 335system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle 336system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle 337system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 338system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle 339system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle 340system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle 341system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle 342system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle 343system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle 344system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle 345system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle 346system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle 347system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 348system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 349system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 350system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle 351system.cpu.commit.committedInsts 4600 # Number of instructions committed 352system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed 353system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 354system.cpu.commit.refs 2139 # Number of memory references committed 355system.cpu.commit.loads 1201 # Number of loads committed 356system.cpu.commit.membars 12 # Number of memory barriers committed 357system.cpu.commit.branches 945 # Number of branches committed 358system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 359system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 360system.cpu.commit.function_calls 82 # Number of function calls committed. 361system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached 362system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 363system.cpu.rob.rob_reads 22664 # The number of ROB reads 364system.cpu.rob.rob_writes 24737 # The number of ROB writes 365system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself 366system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling 367system.cpu.committedInsts 4600 # Number of Instructions Simulated 368system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated 369system.cpu.committedInsts_total 4600 # Number of Instructions Simulated 370system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction 371system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads 372system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle 373system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads 374system.cpu.int_regfile_reads 39570 # number of integer regfile reads 375system.cpu.int_regfile_writes 8020 # number of integer regfile writes 376system.cpu.fp_regfile_reads 16 # number of floating regfile reads 377system.cpu.misc_regfile_reads 16023 # number of misc regfile reads 378system.cpu.misc_regfile_writes 24 # number of misc regfile writes 379system.cpu.icache.replacements 2 # number of replacements 380system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use 381system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. 382system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 383system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. 384system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 385system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor 386system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy 387system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy 388system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits 389system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits 390system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits 391system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits 392system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits 393system.cpu.icache.overall_hits::total 1663 # number of overall hits 394system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 395system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 396system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 397system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 398system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 399system.cpu.icache.overall_misses::total 365 # number of overall misses 400system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles 401system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles 402system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles 403system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles 404system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles 405system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles 406system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) 407system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) 408system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses 409system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses 410system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses 411system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses 412system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses 413system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses 414system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses 415system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency 416system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency 417system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency 418system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 419system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 420system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 421system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 422system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 423system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 424system.cpu.icache.fast_writes 0 # number of fast writes performed 425system.cpu.icache.cache_copies 0 # number of cache copies performed 426system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits 427system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 428system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits 429system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 430system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits 431system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits 432system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 433system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 434system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 435system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 436system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 437system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 438system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles 439system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles 440system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles 441system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles 442system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles 443system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles 444system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses 445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses 446system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses 447system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency 448system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency 449system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency 450system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 451system.cpu.dcache.replacements 0 # number of replacements 452system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use 453system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. 454system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. 455system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. 456system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 457system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor 458system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy 459system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy 460system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits 461system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits 462system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits 463system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits 464system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 465system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 466system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 467system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 468system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits 469system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits 470system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits 471system.cpu.dcache.overall_hits::total 2389 # number of overall hits 472system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 473system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses 474system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses 475system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses 476system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 477system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 478system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses 479system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses 480system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses 481system.cpu.dcache.overall_misses::total 474 # number of overall misses 482system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles 483system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles 484system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles 485system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles 486system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 487system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles 488system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles 489system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles 490system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles 491system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles 492system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) 494system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 496system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 499system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 500system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses 501system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses 502system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses 503system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses 504system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses 505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses 506system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses 508system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses 509system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency 510system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency 511system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 512system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency 513system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency 514system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 518system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 519system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 520system.cpu.dcache.fast_writes 0 # number of fast writes performed 521system.cpu.dcache.cache_copies 0 # number of cache copies performed 522system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 523system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 524system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 526system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 527system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 528system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits 529system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits 530system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits 531system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits 532system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses 533system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses 534system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 535system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 536system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 537system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses 538system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 539system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses 540system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles 545system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles 546system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles 547system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles 548system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses 549system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 550system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses 551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency 553system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency 556system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 557system.cpu.l2cache.replacements 0 # number of replacements 558system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use 559system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. 560system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. 561system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. 562system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 563system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor 564system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor 565system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy 566system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy 567system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy 568system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 569system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits 570system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits 571system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits 573system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits 574system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 575system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits 576system.cpu.l2cache.overall_hits::total 41 # number of overall hits 577system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 578system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 579system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses 580system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 581system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 582system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 583system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses 585system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 586system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses 587system.cpu.l2cache.overall_misses::total 404 # number of overall misses 588system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles 589system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles 590system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles 591system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles 592system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles 593system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles 594system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles 595system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles 597system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles 598system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles 599system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 600system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) 601system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) 602system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 603system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 604system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 605system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 606system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses 607system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 608system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 609system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses 610system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses 611system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses 612system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 613system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses 614system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses 615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses 616system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses 617system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency 618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency 619system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency 620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency 621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency 624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 628system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 630system.cpu.l2cache.fast_writes 0 # number of fast writes performed 631system.cpu.l2cache.cache_copies 0 # number of cache copies performed 632system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 633system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 634system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 635system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 636system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 637system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses 641system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 642system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 643system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 644system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 647system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses 648system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses 649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses 661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses 662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 663system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses 664system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses 665system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses 666system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses 667system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency 668system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency 669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency 670system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 671system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency 672system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 673system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency 674system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 675 676---------- End Simulation Statistics ---------- 677