stats.txt revision 11589:af2f7fef4875
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17232500 # Number of ticks simulated 5final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 74373 # Simulator instruction rate (inst/s) 8host_op_rate 87086 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 279001739 # Simulator tick rate (ticks/s) 10host_mem_usage 265896 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 397 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 397 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 89 # Per bank write bursts 46system.physmem.perBankRdBursts::1 45 # Per bank write bursts 47system.physmem.perBankRdBursts::2 20 # Per bank write bursts 48system.physmem.perBankRdBursts::3 43 # Per bank write bursts 49system.physmem.perBankRdBursts::4 18 # Per bank write bursts 50system.physmem.perBankRdBursts::5 32 # Per bank write bursts 51system.physmem.perBankRdBursts::6 35 # Per bank write bursts 52system.physmem.perBankRdBursts::7 10 # Per bank write bursts 53system.physmem.perBankRdBursts::8 4 # Per bank write bursts 54system.physmem.perBankRdBursts::9 9 # Per bank write bursts 55system.physmem.perBankRdBursts::10 28 # Per bank write bursts 56system.physmem.perBankRdBursts::11 42 # Per bank write bursts 57system.physmem.perBankRdBursts::12 10 # Per bank write bursts 58system.physmem.perBankRdBursts::13 6 # Per bank write bursts 59system.physmem.perBankRdBursts::14 0 # Per bank write bursts 60system.physmem.perBankRdBursts::15 6 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 17147000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 397 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 204system.physmem.totQLat 3287250 # Total ticks spent queuing 205system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 11.52 # Data bus utilization in percentage 216system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 331 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 43191.44 # Average gap between requests 225system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) 234system.physmem_0.averagePower 910.249171 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states 236system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 238system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) 248system.physmem_1.averagePower 808.014211 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states 250system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 254system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 2837 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 865 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks 269system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 270system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 278system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 279system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 280system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 281system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 282system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 283system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 284system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 286system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 287system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 288system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 289system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 290system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 299system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 300system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 308system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 309system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 310system.cpu.checker.dtb.read_hits 0 # DTB read hits 311system.cpu.checker.dtb.read_misses 0 # DTB read misses 312system.cpu.checker.dtb.write_hits 0 # DTB write hits 313system.cpu.checker.dtb.write_misses 0 # DTB write misses 314system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 315system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 316system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 317system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 318system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 319system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 320system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 321system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 324system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 325system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.checker.dtb.hits 0 # DTB hits 327system.cpu.checker.dtb.misses 0 # DTB misses 328system.cpu.checker.dtb.accesses 0 # DTB accesses 329system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 330system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 338system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 339system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 340system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 341system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 342system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 343system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 344system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 345system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 346system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 347system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 348system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 349system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 350system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 351system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 359system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 360system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 361system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 368system.cpu.checker.itb.inst_hits 0 # ITB inst hits 369system.cpu.checker.itb.inst_misses 0 # ITB inst misses 370system.cpu.checker.itb.read_hits 0 # DTB read hits 371system.cpu.checker.itb.read_misses 0 # DTB read misses 372system.cpu.checker.itb.write_hits 0 # DTB write hits 373system.cpu.checker.itb.write_misses 0 # DTB write misses 374system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 375system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 376system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 377system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 378system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 379system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 380system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 381system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 382system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.checker.itb.read_accesses 0 # DTB read accesses 384system.cpu.checker.itb.write_accesses 0 # DTB write accesses 385system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.checker.itb.hits 0 # DTB hits 387system.cpu.checker.itb.misses 0 # DTB misses 388system.cpu.checker.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 13 # Number of system calls 390system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states 391system.cpu.checker.numCycles 5391 # number of cpu cycles simulated 392system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 395system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 402system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 403system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 404system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 405system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 406system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 407system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 408system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 409system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 410system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 411system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 412system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 413system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 414system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 415system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 416system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 424system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 425system.cpu.dtb.walker.walks 0 # Table walker walks requested 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 432system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 433system.cpu.dtb.inst_hits 0 # ITB inst hits 434system.cpu.dtb.inst_misses 0 # ITB inst misses 435system.cpu.dtb.read_hits 0 # DTB read hits 436system.cpu.dtb.read_misses 0 # DTB read misses 437system.cpu.dtb.write_hits 0 # DTB write hits 438system.cpu.dtb.write_misses 0 # DTB write misses 439system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 440system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 441system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 443system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 444system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 446system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 448system.cpu.dtb.read_accesses 0 # DTB read accesses 449system.cpu.dtb.write_accesses 0 # DTB write accesses 450system.cpu.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu.dtb.hits 0 # DTB hits 452system.cpu.dtb.misses 0 # DTB misses 453system.cpu.dtb.accesses 0 # DTB accesses 454system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 455system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 463system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 464system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 465system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 466system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 467system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 468system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 469system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 470system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 471system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 472system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 473system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 474system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 475system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 476system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 484system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 485system.cpu.itb.walker.walks 0 # Table walker walks requested 486system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 489system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 492system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 493system.cpu.itb.inst_hits 0 # ITB inst hits 494system.cpu.itb.inst_misses 0 # ITB inst misses 495system.cpu.itb.read_hits 0 # DTB read hits 496system.cpu.itb.read_misses 0 # DTB read misses 497system.cpu.itb.write_hits 0 # DTB write hits 498system.cpu.itb.write_misses 0 # DTB write misses 499system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 500system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 501system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 502system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 503system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 504system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 505system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 506system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu.itb.read_accesses 0 # DTB read accesses 509system.cpu.itb.write_accesses 0 # DTB write accesses 510system.cpu.itb.inst_accesses 0 # ITB inst accesses 511system.cpu.itb.hits 0 # DTB hits 512system.cpu.itb.misses 0 # DTB misses 513system.cpu.itb.accesses 0 # DTB accesses 514system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states 515system.cpu.numCycles 34466 # number of cpu cycles simulated 516system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 517system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 518system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss 519system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed 520system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered 521system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken 522system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked 523system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 524system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 525system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps 526system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 527system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 528system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 529system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) 532system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 533system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) 534system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) 535system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) 536system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) 537system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) 538system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) 539system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) 540system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) 541system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) 542system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 543system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 544system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 545system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) 546system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle 547system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle 548system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle 549system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked 550system.cpu.decode.RunCycles 2142 # Number of cycles decode is running 551system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 552system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 553system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 554system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 555system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode 556system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 557system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 558system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle 559system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking 560system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst 561system.cpu.rename.RunCycles 2037 # Number of cycles rename is running 562system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 563system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename 564system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 565system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full 566system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full 567system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full 568system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed 569system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made 570system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups 571system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 572system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 573system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing 574system.cpu.rename.serializingInsts 40 # count of serializing insts renamed 575system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed 576system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer 577system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. 578system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. 579system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 580system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. 581system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) 582system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ 583system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued 584system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued 585system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling 586system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph 587system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 588system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle 589system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle 590system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle 591system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 592system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle 593system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle 594system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle 595system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle 596system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle 597system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle 598system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle 599system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle 600system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle 601system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 602system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 603system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 604system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle 605system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 606system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available 607system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available 608system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available 609system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available 610system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available 611system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available 612system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available 613system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available 614system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available 618system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available 619system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available 620system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available 621system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available 622system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available 623system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available 624system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available 625system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available 626system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available 627system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available 628system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available 629system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available 630system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available 631system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available 632system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available 633system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available 634system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available 635system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available 636system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available 637system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 638system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 639system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 640system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued 641system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued 642system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued 643system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued 644system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued 645system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued 646system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued 647system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued 648system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued 652system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued 653system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued 654system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued 655system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued 656system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued 657system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued 658system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued 659system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued 660system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued 661system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued 662system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued 663system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued 664system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued 665system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued 666system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued 667system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued 668system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued 669system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued 670system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued 671system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 672system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 673system.cpu.iq.FU_type_0::total 8103 # Type of FU issued 674system.cpu.iq.rate 0.235101 # Inst issue rate 675system.cpu.iq.fu_busy_cnt 145 # FU busy when requested 676system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) 677system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads 678system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes 679system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses 680system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads 681system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 682system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 683system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses 684system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 685system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 686system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 687system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed 688system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 689system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 690system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed 691system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 692system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 693system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled 694system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 695system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 696system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing 697system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking 698system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 699system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ 700system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch 701system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions 702system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions 703system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions 704system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 705system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 706system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 707system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly 708system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly 709system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute 710system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions 711system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed 712system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute 713system.cpu.iew.exec_swp 0 # number of swp insts executed 714system.cpu.iew.exec_nop 9 # number of nop insts executed 715system.cpu.iew.exec_refs 2923 # number of memory reference insts executed 716system.cpu.iew.exec_branches 1492 # Number of branches executed 717system.cpu.iew.exec_stores 1151 # Number of stores executed 718system.cpu.iew.exec_rate 0.226716 # Inst execution rate 719system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit 720system.cpu.iew.wb_count 7439 # cumulative count of insts written-back 721system.cpu.iew.wb_producers 3504 # num instructions producing a value 722system.cpu.iew.wb_consumers 6831 # num instructions consuming a value 723system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle 724system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back 725system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit 726system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 727system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted 728system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle 730system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle 731system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 732system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle 733system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle 734system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle 735system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle 736system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle 737system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle 738system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle 739system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle 740system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle 741system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 742system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 743system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 744system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle 745system.cpu.commit.committedInsts 4592 # Number of instructions committed 746system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 747system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 748system.cpu.commit.refs 1965 # Number of memory references committed 749system.cpu.commit.loads 1027 # Number of loads committed 750system.cpu.commit.membars 12 # Number of memory barriers committed 751system.cpu.commit.branches 1008 # Number of branches committed 752system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 753system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 754system.cpu.commit.function_calls 82 # Number of function calls committed. 755system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 756system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 757system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 758system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 759system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 760system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 761system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 762system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 763system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 764system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 765system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 766system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 767system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 768system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 769system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 770system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 771system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 772system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 773system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 774system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 775system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 776system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 777system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 778system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 779system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 780system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 781system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 782system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 783system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 784system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 785system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 786system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 787system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 788system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 789system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 790system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached 791system.cpu.rob.rob_reads 22311 # The number of ROB reads 792system.cpu.rob.rob_writes 21303 # The number of ROB writes 793system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself 794system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling 795system.cpu.committedInsts 4592 # Number of Instructions Simulated 796system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 797system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction 798system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads 799system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle 800system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads 801system.cpu.int_regfile_reads 7659 # number of integer regfile reads 802system.cpu.int_regfile_writes 4270 # number of integer regfile writes 803system.cpu.fp_regfile_reads 32 # number of floating regfile reads 804system.cpu.cc_regfile_reads 27801 # number of cc regfile reads 805system.cpu.cc_regfile_writes 3276 # number of cc regfile writes 806system.cpu.misc_regfile_reads 2980 # number of misc regfile reads 807system.cpu.misc_regfile_writes 24 # number of misc regfile writes 808system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 809system.cpu.dcache.tags.replacements 0 # number of replacements 810system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. 812system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 813system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. 814system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 815system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy 818system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 819system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 820system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 821system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 822system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses 823system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses 824system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 825system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 826system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 827system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 828system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 829system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 830system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 831system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 832system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 833system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits 834system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits 835system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits 836system.cpu.dcache.overall_hits::total 2074 # number of overall hits 837system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 838system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses 839system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 840system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 841system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 842system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 843system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 844system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 845system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 846system.cpu.dcache.overall_misses::total 499 # number of overall misses 847system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles 848system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles 849system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles 850system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles 851system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles 852system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles 853system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles 854system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles 855system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles 856system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles 857system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) 858system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) 859system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 860system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 861system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 862system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 863system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 864system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 865system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses 866system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses 867system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses 868system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses 869system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses 870system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses 871system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 872system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 873system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 874system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 875system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses 876system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses 877system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses 878system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses 879system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency 880system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency 882system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency 883system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency 884system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency 885system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency 886system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency 887system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency 888system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency 889system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked 890system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 892system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked 894system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 896system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 897system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 898system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 899system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 900system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 901system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 902system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 903system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 904system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 905system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 906system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 908system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 909system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 910system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 911system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 912system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 913system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles 920system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles 921system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses 922system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses 923system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 924system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 925system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses 926system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses 927system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses 928system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses 929system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency 930system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency 931system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency 932system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency 933system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 934system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 935system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 936system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 937system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 938system.cpu.icache.tags.replacements 2 # number of replacements 939system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use 940system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 941system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 942system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 943system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 944system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor 945system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy 946system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy 947system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 948system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 949system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 950system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 951system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses 952system.cpu.icache.tags.data_accesses 4216 # Number of data accesses 953system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 954system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 955system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 956system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 957system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 958system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 959system.cpu.icache.overall_hits::total 1577 # number of overall hits 960system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses 961system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses 962system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses 963system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses 964system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses 965system.cpu.icache.overall_misses::total 384 # number of overall misses 966system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles 967system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles 968system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles 969system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles 970system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles 971system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles 972system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) 973system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) 974system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses 975system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses 976system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses 977system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses 978system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses 979system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses 980system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses 981system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses 982system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses 983system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses 984system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency 985system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency 986system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency 987system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency 988system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency 989system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency 990system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked 991system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 992system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 993system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 994system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked 995system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 996system.cpu.icache.writebacks::writebacks 2 # number of writebacks 997system.cpu.icache.writebacks::total 2 # number of writebacks 998system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 999system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 1000system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 1001system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 1002system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 1003system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits 1004system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 1005system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 1006system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 1007system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 1008system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 1009system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 1010system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles 1011system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles 1012system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles 1013system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles 1014system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles 1015system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles 1016system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses 1017system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses 1018system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses 1019system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses 1020system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses 1021system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses 1022system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency 1023system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency 1024system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1025system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 1026system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 1027system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 1028system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 1029system.cpu.l2cache.tags.replacements 0 # number of replacements 1030system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use 1031system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 1032system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 1033system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 1034system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1035system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor 1036system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy 1038system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy 1039system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy 1040system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 1041system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1042system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 1043system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 1044system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 1045system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses 1046system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 1047system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 1048system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 1049system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 1050system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 1051system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 1052system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 1053system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 1054system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 1055system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits 1056system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 1057system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 1058system.cpu.l2cache.overall_hits::total 38 # number of overall hits 1059system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 1060system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 1061system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses 1062system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses 1063system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 1064system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses 1065system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 1066system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 1067system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 1068system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 1069system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 1070system.cpu.l2cache.overall_misses::total 403 # number of overall misses 1071system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles 1072system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles 1073system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles 1074system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles 1075system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles 1076system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles 1077system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles 1078system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles 1079system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles 1080system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles 1081system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles 1082system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles 1083system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 1084system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 1085system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 1086system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 1087system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 1088system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) 1089system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 1090system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) 1091system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 1092system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 1093system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 1094system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 1095system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 1096system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 1097system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1098system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1099system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses 1100system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses 1101system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 1102system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses 1103system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses 1104system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 1105system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 1106system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses 1107system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 1108system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses 1109system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency 1110system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency 1111system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency 1112system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency 1113system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency 1114system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency 1115system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency 1116system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency 1117system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency 1118system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency 1119system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency 1120system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency 1121system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1125system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 1128system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 1129system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 1130system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1131system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 1132system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1133system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1134system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 1135system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses 1136system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses 1137system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 1138system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 1139system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 1140system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 1143system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 1145system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles 1146system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles 1147system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles 1148system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles 1149system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles 1150system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles 1151system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles 1152system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles 1153system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles 1154system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles 1155system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles 1156system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles 1157system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1158system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1159system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 1160system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses 1161system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 1162system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 1163system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses 1164system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 1165system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 1166system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses 1167system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 1168system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 1169system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency 1170system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency 1171system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency 1172system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency 1173system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency 1174system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 1181system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 1188system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 1194system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) 1197system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 1198system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) 1200system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1201system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 1202system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 1203system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1213system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 1214system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1215system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) 1216system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 1217system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 1218system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 1219system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states 1220system.membus.trans_dist::ReadResp 355 # Transaction distribution 1221system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1222system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1223system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 1224system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1225system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1226system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1227system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 1228system.membus.snoops 0 # Total snoops (count) 1229system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1230system.membus.snoop_fanout::samples 397 # Request fanout histogram 1231system.membus.snoop_fanout::mean 0 # Request fanout histogram 1232system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1233system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1234system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 1235system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1236system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1237system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1238system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1239system.membus.snoop_fanout::total 397 # Request fanout histogram 1240system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) 1241system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 1242system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) 1243system.membus.respLayer1.utilization 12.2 # Layer utilization (%) 1244 1245---------- End Simulation Statistics ---------- 1246