stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16223000 # Number of ticks simulated 5final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 32617 # Simulator instruction rate (inst/s) 8host_op_rate 38195 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115221437 # Simulator tick rate (ticks/s) 10host_mem_usage 253076 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 397 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 397 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 90 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 43 # Per bank write bursts 48system.physmem.perBankRdBursts::4 18 # Per bank write bursts 49system.physmem.perBankRdBursts::5 32 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 8 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 16156000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 397 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 202system.physmem.totQLat 2970000 # Total ticks spent queuing 203system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 12.24 # Data bus utilization in percentage 214system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 331 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 40695.21 # Average gap between requests 223system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 229system.membus.throughput 1566171485 # Throughput (bytes/s) 230system.membus.trans_dist::ReadReq 355 # Transaction distribution 231system.membus.trans_dist::ReadResp 355 # Transaction distribution 232system.membus.trans_dist::ReadExReq 42 # Transaction distribution 233system.membus.trans_dist::ReadExResp 42 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 25408 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 240system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 241system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 242system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 243system.membus.respLayer1.utilization 22.8 # Layer utilization (%) 244system.cpu_clk_domain.clock 500 # Clock period in ticks 245system.cpu.branchPred.lookups 2638 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 247system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect 248system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups 249system.cpu.branchPred.BTBHits 783 # Number of BTB hits 250system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 251system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage 252system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. 253system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. 254system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 255system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 256system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 257system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 258system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 259system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 260system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 262system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 263system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 264system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 265system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 266system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 267system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 268system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 269system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 270system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 271system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 272system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 273system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 274system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 275system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 276system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 277system.cpu.checker.dtb.read_hits 0 # DTB read hits 278system.cpu.checker.dtb.read_misses 0 # DTB read misses 279system.cpu.checker.dtb.write_hits 0 # DTB write hits 280system.cpu.checker.dtb.write_misses 0 # DTB write misses 281system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 285system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 286system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 287system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 288system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 291system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 292system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 293system.cpu.checker.dtb.hits 0 # DTB hits 294system.cpu.checker.dtb.misses 0 # DTB misses 295system.cpu.checker.dtb.accesses 0 # DTB accesses 296system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 297system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 298system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 299system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 300system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 301system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 302system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 303system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 304system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 305system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 306system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 307system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 308system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 309system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 310system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 311system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 312system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 313system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 314system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 315system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 316system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 317system.cpu.checker.itb.inst_hits 0 # ITB inst hits 318system.cpu.checker.itb.inst_misses 0 # ITB inst misses 319system.cpu.checker.itb.read_hits 0 # DTB read hits 320system.cpu.checker.itb.read_misses 0 # DTB read misses 321system.cpu.checker.itb.write_hits 0 # DTB write hits 322system.cpu.checker.itb.write_misses 0 # DTB write misses 323system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 324system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 325system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 326system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 327system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 328system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 329system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 330system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 331system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 332system.cpu.checker.itb.read_accesses 0 # DTB read accesses 333system.cpu.checker.itb.write_accesses 0 # DTB write accesses 334system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 335system.cpu.checker.itb.hits 0 # DTB hits 336system.cpu.checker.itb.misses 0 # DTB misses 337system.cpu.checker.itb.accesses 0 # DTB accesses 338system.cpu.workload.num_syscalls 13 # Number of system calls 339system.cpu.checker.numCycles 5390 # number of cpu cycles simulated 340system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 342system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 343system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 344system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 345system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 346system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 347system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 348system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 349system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 350system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 351system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 352system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 353system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 354system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 355system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 363system.cpu.dtb.inst_hits 0 # ITB inst hits 364system.cpu.dtb.inst_misses 0 # ITB inst misses 365system.cpu.dtb.read_hits 0 # DTB read hits 366system.cpu.dtb.read_misses 0 # DTB read misses 367system.cpu.dtb.write_hits 0 # DTB write hits 368system.cpu.dtb.write_misses 0 # DTB write misses 369system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.dtb.read_accesses 0 # DTB read accesses 379system.cpu.dtb.write_accesses 0 # DTB write accesses 380system.cpu.dtb.inst_accesses 0 # ITB inst accesses 381system.cpu.dtb.hits 0 # DTB hits 382system.cpu.dtb.misses 0 # DTB misses 383system.cpu.dtb.accesses 0 # DTB accesses 384system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 385system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 386system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 387system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 388system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 389system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 390system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 393system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 394system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 395system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 396system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 397system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 400system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 401system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 402system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 403system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 404system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 405system.cpu.itb.inst_hits 0 # ITB inst hits 406system.cpu.itb.inst_misses 0 # ITB inst misses 407system.cpu.itb.read_hits 0 # DTB read hits 408system.cpu.itb.read_misses 0 # DTB read misses 409system.cpu.itb.write_hits 0 # DTB write hits 410system.cpu.itb.write_misses 0 # DTB write misses 411system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 412system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 413system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 414system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 415system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 416system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 417system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 418system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 419system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu.itb.read_accesses 0 # DTB read accesses 421system.cpu.itb.write_accesses 0 # DTB write accesses 422system.cpu.itb.inst_accesses 0 # ITB inst accesses 423system.cpu.itb.hits 0 # DTB hits 424system.cpu.itb.misses 0 # DTB misses 425system.cpu.itb.accesses 0 # DTB accesses 426system.cpu.numCycles 32447 # number of cpu cycles simulated 427system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 428system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 429system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss 430system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed 431system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered 432system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken 433system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked 434system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing 435system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 436system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps 437system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR 438system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched 439system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed 440system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle 458system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle 459system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle 460system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked 461system.cpu.decode.RunCycles 2145 # Number of cycles decode is running 462system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking 463system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing 464system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch 465system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 466system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode 467system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode 468system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing 469system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle 470system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking 471system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst 472system.cpu.rename.RunCycles 2064 # Number of cycles rename is running 473system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking 474system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename 475system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full 476system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full 477system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full 478system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed 479system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made 480system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups 481system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 482system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 483system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing 484system.cpu.rename.serializingInsts 43 # count of serializing insts renamed 485system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 486system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer 487system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. 488system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. 489system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 490system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. 491system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) 492system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 493system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued 494system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued 495system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling 496system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph 497system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 498system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle 515system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 516system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available 518system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available 545system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available 546system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 550system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued 551system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued 552system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued 579system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued 580system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued 581system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::total 8358 # Type of FU issued 584system.cpu.iq.rate 0.257589 # Inst issue rate 585system.cpu.iq.fu_busy_cnt 169 # FU busy when requested 586system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) 587system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads 588system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes 589system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses 590system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads 591system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes 592system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses 593system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses 594system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 595system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores 596system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 597system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed 598system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 599system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 600system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed 601system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 602system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 603system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled 604system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 605system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 606system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing 607system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking 608system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking 609system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ 610system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch 611system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions 612system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions 613system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 614system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 615system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 616system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 617system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly 618system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly 619system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute 620system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions 621system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed 622system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute 623system.cpu.iew.exec_swp 0 # number of swp insts executed 624system.cpu.iew.exec_nop 11 # number of nop insts executed 625system.cpu.iew.exec_refs 3148 # number of memory reference insts executed 626system.cpu.iew.exec_branches 1457 # Number of branches executed 627system.cpu.iew.exec_stores 1240 # Number of stores executed 628system.cpu.iew.exec_rate 0.248498 # Inst execution rate 629system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit 630system.cpu.iew.wb_count 7601 # cumulative count of insts written-back 631system.cpu.iew.wb_producers 3572 # num instructions producing a value 632system.cpu.iew.wb_consumers 6998 # num instructions consuming a value 633system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 634system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle 635system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back 636system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 637system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit 638system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 639system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted 640system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle 657system.cpu.commit.committedInsts 4591 # Number of instructions committed 658system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 659system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 660system.cpu.commit.refs 1965 # Number of memory references committed 661system.cpu.commit.loads 1027 # Number of loads committed 662system.cpu.commit.membars 12 # Number of memory barriers committed 663system.cpu.commit.branches 1007 # Number of branches committed 664system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 665system.cpu.commit.int_insts 4624 # Number of committed integer instructions. 666system.cpu.commit.function_calls 82 # Number of function calls committed. 667system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 668system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction 669system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction 670system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 697system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 698system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 701system.cpu.commit.op_class_0::total 5377 # Class of committed instruction 702system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 703system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 704system.cpu.rob.rob_reads 22692 # The number of ROB reads 705system.cpu.rob.rob_writes 21719 # The number of ROB writes 706system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself 707system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling 708system.cpu.committedInsts 4591 # Number of Instructions Simulated 709system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 710system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction 711system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads 712system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle 713system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 714system.cpu.int_regfile_reads 7944 # number of integer regfile reads 715system.cpu.int_regfile_writes 4420 # number of integer regfile writes 716system.cpu.fp_regfile_reads 31 # number of floating regfile reads 717system.cpu.cc_regfile_reads 28734 # number of cc regfile reads 718system.cpu.cc_regfile_writes 3302 # number of cc regfile writes 719system.cpu.misc_regfile_reads 3189 # number of misc regfile reads 720system.cpu.misc_regfile_writes 24 # number of misc regfile writes 721system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) 722system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 723system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 724system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 725system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 726system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 727system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 728system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) 729system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 730system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 731system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 732system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) 733system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 734system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 735system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 736system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 737system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 738system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 739system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 740system.cpu.icache.tags.replacements 1 # number of replacements 741system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use 742system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 743system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 744system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. 745system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 746system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor 747system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy 748system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy 749system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id 750system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 751system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 752system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id 753system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses 754system.cpu.icache.tags.data_accesses 4430 # Number of data accesses 755system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits 756system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits 757system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits 758system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits 759system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits 760system.cpu.icache.overall_hits::total 1666 # number of overall hits 761system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses 762system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses 763system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses 764system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses 765system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses 766system.cpu.icache.overall_misses::total 402 # number of overall misses 767system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles 768system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles 769system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles 770system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles 771system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles 772system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles 773system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 774system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 775system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 776system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 777system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 778system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 779system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses 780system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses 781system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses 782system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses 783system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses 784system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses 785system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency 786system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency 787system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency 788system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency 789system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency 790system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency 791system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked 792system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 794system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked 796system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 797system.cpu.icache.fast_writes 0 # number of fast writes performed 798system.cpu.icache.cache_copies 0 # number of cache copies performed 799system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits 800system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits 801system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits 802system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits 803system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 804system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 805system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 806system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 807system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 808system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 809system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 810system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 811system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles 812system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles 813system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles 814system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles 815system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles 816system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles 817system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses 818system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses 819system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses 820system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses 821system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses 822system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses 823system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency 824system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency 825system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency 826system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency 827system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency 828system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency 829system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 830system.cpu.l2cache.tags.replacements 0 # number of replacements 831system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use 832system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 833system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 834system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 835system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 836system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor 837system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor 838system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy 839system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy 840system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy 841system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 842system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 843system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 844system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 845system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses 846system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses 847system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 848system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 849system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 850system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 851system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 852system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 853system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 854system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 855system.cpu.l2cache.overall_hits::total 39 # number of overall hits 856system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses 857system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 858system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses 859system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 860system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 861system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 862system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 863system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses 864system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 865system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 866system.cpu.l2cache.overall_misses::total 402 # number of overall misses 867system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles 868system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles 869system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles 870system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles 871system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles 872system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles 874system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles 875system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles 876system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles 877system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles 878system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) 879system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 880system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 881system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 882system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 883system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 884system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 885system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 886system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 887system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 888system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 889system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses 892system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 893system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 894system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses 895system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 896system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses 897system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses 898system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 899system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses 900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency 901system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency 902system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency 903system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency 904system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency 905system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency 907system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency 908system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency 909system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency 910system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency 911system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 912system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 914system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 915system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 916system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 917system.cpu.l2cache.fast_writes 0 # number of fast writes performed 918system.cpu.l2cache.cache_copies 0 # number of cache copies performed 919system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 920system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 921system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 922system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 923system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 924system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 925system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 926system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses 927system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses 928system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 929system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 930system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 932system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 933system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 934system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 935system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 936system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles 938system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles 940system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles 941system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles 942system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles 943system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles 944system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles 945system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles 946system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles 947system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses 948system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses 949system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses 950system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 951system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 952system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses 953system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 954system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 955system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses 956system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 957system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 958system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency 959system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency 960system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency 961system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency 962system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency 963system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency 964system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency 965system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 966system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency 967system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency 968system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 969system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 970system.cpu.dcache.tags.replacements 0 # number of replacements 971system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use 972system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 973system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 974system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. 975system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 976system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor 977system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy 978system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy 979system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 980system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 981system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 982system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 983system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 984system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 985system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 986system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits 987system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits 988system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits 989system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 990system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 991system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 992system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 993system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits 994system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits 995system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits 996system.cpu.dcache.overall_hits::total 2146 # number of overall hits 997system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses 998system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses 999system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 1000system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses 1001system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 1002system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 1003system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 1004system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 1005system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 1006system.cpu.dcache.overall_misses::total 521 # number of overall misses 1007system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles 1008system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles 1009system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 1010system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 1011system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 1012system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles 1013system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles 1014system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles 1015system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles 1016system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles 1017system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 1018system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) 1019system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1020system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1021system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 1022system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 1023system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1024system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 1025system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses 1026system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses 1027system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses 1028system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses 1029system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses 1030system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses 1031system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 1032system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 1033system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 1034system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 1035system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 1036system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 1037system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 1038system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses 1039system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency 1040system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency 1041system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 1042system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 1043system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 1044system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency 1045system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency 1046system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency 1047system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency 1048system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency 1049system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 1050system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1051system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 1052system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1053system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 1054system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1055system.cpu.dcache.fast_writes 0 # number of fast writes performed 1056system.cpu.dcache.cache_copies 0 # number of cache copies performed 1057system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits 1058system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits 1059system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits 1060system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits 1061system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1062system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1063system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 1064system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 1065system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 1066system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 1067system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 1068system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 1069system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 1070system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 1071system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1072system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1073system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1074system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 1075system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles 1076system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles 1077system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 1078system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles 1079system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles 1080system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles 1081system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles 1082system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles 1083system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 1084system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 1085system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 1086system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 1087system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 1088system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 1089system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 1090system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses 1091system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency 1092system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency 1093system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 1094system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency 1095system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency 1096system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency 1097system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency 1098system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency 1099system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1100 1101---------- End Simulation Statistics ---------- 1102