stats.txt revision 10038:7eccd14e2610
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 39940 # Simulator instruction rate (inst/s) 8host_op_rate 49834 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 147693403 # Simulator tick rate (ticks/s) 10host_mem_usage 267784 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 392 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1017607915 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 459808021 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1477415935 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1017607915 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1017607915 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1017607915 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 459808021 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1477415935 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 392 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 86 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 42 # Per bank write bursts 48system.physmem.perBankRdBursts::4 17 # Per bank write bursts 49system.physmem.perBankRdBursts::5 34 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 7 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 16923500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 392 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::mean 374.400000 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::gmean 181.494324 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::stdev 535.569369 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::64 25 41.67% 41.67% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::128 8 13.33% 55.00% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::192 5 8.33% 63.33% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::256 3 5.00% 68.33% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::320 3 5.00% 73.33% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::384 1 1.67% 75.00% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::448 2 3.33% 78.33% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::512 1 1.67% 80.00% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::640 2 3.33% 83.33% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::768 2 3.33% 86.67% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::896 1 1.67% 88.33% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1024 1 1.67% 90.00% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1152 1 1.67% 91.67% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::1536 1 1.67% 93.33% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::1664 1 1.67% 95.00% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::1856 1 1.67% 96.67% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::1984 1 1.67% 98.33% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::2432 1 1.67% 100.00% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 180system.physmem.totQLat 3153000 # Total ticks spent queuing 181system.physmem.totMemAccLat 10516750 # Total ticks spent from burst creation until serviced by the DRAM 182system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 183system.physmem.totBankLat 5403750 # Total ticks spent accessing banks 184system.physmem.avgQLat 8043.37 # Average queueing delay per DRAM burst 185system.physmem.avgBankLat 13785.08 # Average bank access latency per DRAM burst 186system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 187system.physmem.avgMemAccLat 26828.44 # Average memory access latency per DRAM burst 188system.physmem.avgRdBW 1477.42 # Average DRAM read bandwidth in MiByte/s 189system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 190system.physmem.avgRdBWSys 1477.42 # Average system read bandwidth in MiByte/s 191system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 192system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 193system.physmem.busUtil 11.54 # Data bus utilization in percentage 194system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads 195system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 196system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing 197system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 198system.physmem.readRowHits 332 # Number of row buffer hits during reads 199system.physmem.writeRowHits 0 # Number of row buffer hits during writes 200system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads 201system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 202system.physmem.avgGap 43172.19 # Average gap between requests 203system.physmem.pageHitRate 84.69 # Row buffer hit rate, read and write combined 204system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state 205system.membus.throughput 1473647017 # Throughput (bytes/s) 206system.membus.trans_dist::ReadReq 351 # Transaction distribution 207system.membus.trans_dist::ReadResp 350 # Transaction distribution 208system.membus.trans_dist::ReadExReq 41 # Transaction distribution 209system.membus.trans_dist::ReadExResp 41 # Transaction distribution 210system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 211system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 212system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 213system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 214system.membus.data_through_bus 25024 # Total data (bytes) 215system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 216system.membus.reqLayer0.occupancy 483500 # Layer occupancy (ticks) 217system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 218system.membus.respLayer1.occupancy 3646500 # Layer occupancy (ticks) 219system.membus.respLayer1.utilization 21.5 # Layer utilization (%) 220system.cpu_clk_domain.clock 500 # Clock period in ticks 221system.cpu.branchPred.lookups 2481 # Number of BP lookups 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 230system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 231system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 232system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 233system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 234system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 235system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 236system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 238system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 239system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 240system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 241system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 242system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 243system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 246system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 247system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 248system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 249system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 250system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 251system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 252system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 253system.cpu.checker.dtb.read_hits 0 # DTB read hits 254system.cpu.checker.dtb.read_misses 0 # DTB read misses 255system.cpu.checker.dtb.write_hits 0 # DTB write hits 256system.cpu.checker.dtb.write_misses 0 # DTB write misses 257system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 259system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 260system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 261system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 262system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 263system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 264system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 265system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 266system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 267system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 268system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 269system.cpu.checker.dtb.hits 0 # DTB hits 270system.cpu.checker.dtb.misses 0 # DTB misses 271system.cpu.checker.dtb.accesses 0 # DTB accesses 272system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 273system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 274system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 275system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 276system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 277system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 278system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 279system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 280system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 281system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 282system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 283system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 284system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 285system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 287system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 288system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 289system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 290system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 291system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 292system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 293system.cpu.checker.itb.inst_hits 0 # ITB inst hits 294system.cpu.checker.itb.inst_misses 0 # ITB inst misses 295system.cpu.checker.itb.read_hits 0 # DTB read hits 296system.cpu.checker.itb.read_misses 0 # DTB read misses 297system.cpu.checker.itb.write_hits 0 # DTB write hits 298system.cpu.checker.itb.write_misses 0 # DTB write misses 299system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 300system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 301system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 302system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 303system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 304system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 305system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 306system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 308system.cpu.checker.itb.read_accesses 0 # DTB read accesses 309system.cpu.checker.itb.write_accesses 0 # DTB write accesses 310system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 311system.cpu.checker.itb.hits 0 # DTB hits 312system.cpu.checker.itb.misses 0 # DTB misses 313system.cpu.checker.itb.accesses 0 # DTB accesses 314system.cpu.workload.num_syscalls 13 # Number of system calls 315system.cpu.checker.numCycles 5742 # number of cpu cycles simulated 316system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 317system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 318system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 319system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 320system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 321system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 322system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 323system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 324system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 334system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 335system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 336system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 337system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 339system.cpu.dtb.inst_hits 0 # ITB inst hits 340system.cpu.dtb.inst_misses 0 # ITB inst misses 341system.cpu.dtb.read_hits 0 # DTB read hits 342system.cpu.dtb.read_misses 0 # DTB read misses 343system.cpu.dtb.write_hits 0 # DTB write hits 344system.cpu.dtb.write_misses 0 # DTB write misses 345system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 346system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 347system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 348system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 349system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 350system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 351system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 352system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 353system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 354system.cpu.dtb.read_accesses 0 # DTB read accesses 355system.cpu.dtb.write_accesses 0 # DTB write accesses 356system.cpu.dtb.inst_accesses 0 # ITB inst accesses 357system.cpu.dtb.hits 0 # DTB hits 358system.cpu.dtb.misses 0 # DTB misses 359system.cpu.dtb.accesses 0 # DTB accesses 360system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 361system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 362system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 363system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 364system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 365system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 366system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 381system.cpu.itb.inst_hits 0 # ITB inst hits 382system.cpu.itb.inst_misses 0 # ITB inst misses 383system.cpu.itb.read_hits 0 # DTB read hits 384system.cpu.itb.read_misses 0 # DTB read misses 385system.cpu.itb.write_hits 0 # DTB write hits 386system.cpu.itb.write_misses 0 # DTB write misses 387system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 388system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 389system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 390system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 391system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 392system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 393system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 394system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.itb.read_accesses 0 # DTB read accesses 397system.cpu.itb.write_accesses 0 # DTB write accesses 398system.cpu.itb.inst_accesses 0 # ITB inst accesses 399system.cpu.itb.hits 0 # DTB hits 400system.cpu.itb.misses 0 # DTB misses 401system.cpu.itb.accesses 0 # DTB accesses 402system.cpu.numCycles 33963 # number of cpu cycles simulated 403system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 404system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 405system.cpu.fetch.icacheStallCycles 6931 # Number of cycles fetch is stalled on an Icache miss 406system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 407system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 408system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 409system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 410system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 411system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked 412system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 413system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 414system.cpu.fetch.rateDist::samples 13238 # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::mean 1.137785 # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::stdev 2.552533 # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::0 10611 80.16% 80.16% # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::1 226 1.71% 81.86% # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::2 203 1.53% 83.40% # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::3 226 1.71% 85.10% # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::4 222 1.68% 86.78% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::5 269 2.03% 88.81% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::6 92 0.69% 89.51% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::total 13238 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.073050 # Number of branch fetches per cycle 432system.cpu.fetch.rate 0.351059 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 6943 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 2426 # Number of cycles decode is running 436system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 440system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 442system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 443system.cpu.rename.IdleCycles 7209 # Number of cycles rename is idle 444system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 446system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 449system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 450system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 451system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 452system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 453system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made 454system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 455system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 456system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 457system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 458system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 459system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 460system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 461system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 462system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 463system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 464system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 465system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 466system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 467system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 468system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 469system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 470system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph 471system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 472system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::3 544 4.11% 93.16% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::4 456 3.44% 96.60% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::5 260 1.96% 98.56% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::total 13238 # Number of insts issued each cycle 489system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 490system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 491system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 492system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 493system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 494system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 519system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 520system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 521system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 522system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 523system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 524system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 525system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 526system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 527system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 528system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 529system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 553system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 554system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 555system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 556system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 557system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 558system.cpu.iq.rate 0.262668 # Inst issue rate 559system.cpu.iq.fu_busy_cnt 224 # FU busy when requested 560system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 561system.cpu.iq.int_inst_queue_reads 31381 # Number of integer instruction queue reads 562system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 563system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 564system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 565system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 566system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 567system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 568system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 569system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 570system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 571system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 572system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 573system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 574system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 575system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 576system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 577system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 578system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 579system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 580system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 581system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 582system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 583system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 584system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 585system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 586system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 587system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 588system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 589system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 590system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 591system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 592system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 593system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 594system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions 595system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed 596system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 597system.cpu.iew.exec_swp 0 # number of swp insts executed 598system.cpu.iew.exec_nop 0 # number of nop insts executed 599system.cpu.iew.exec_refs 3299 # number of memory reference insts executed 600system.cpu.iew.exec_branches 1437 # Number of branches executed 601system.cpu.iew.exec_stores 1160 # Number of stores executed 602system.cpu.iew.exec_rate 0.250950 # Inst execution rate 603system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 604system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 605system.cpu.iew.wb_producers 3883 # num instructions producing a value 606system.cpu.iew.wb_consumers 7788 # num instructions consuming a value 607system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 608system.cpu.iew.wb_rate 0.237553 # insts written-back per cycle 609system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back 610system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 611system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 612system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 613system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 614system.cpu.commit.committed_per_cycle::samples 12287 # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::mean 0.466265 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::stdev 1.297883 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::0 10001 81.39% 81.39% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::1 1069 8.70% 90.10% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::2 402 3.27% 93.37% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::3 263 2.14% 95.51% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::4 175 1.42% 96.93% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::total 12287 # Number of insts commited each cycle 631system.cpu.commit.committedInsts 4591 # Number of instructions committed 632system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 633system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 634system.cpu.commit.refs 2138 # Number of memory references committed 635system.cpu.commit.loads 1200 # Number of loads committed 636system.cpu.commit.membars 12 # Number of memory barriers committed 637system.cpu.commit.branches 1007 # Number of branches committed 638system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 639system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 640system.cpu.commit.function_calls 82 # Number of function calls committed. 641system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 642system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 643system.cpu.rob.rob_reads 23234 # The number of ROB reads 644system.cpu.rob.rob_writes 23415 # The number of ROB writes 645system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 646system.cpu.idleCycles 20725 # Total number of cycles that the CPU has spent unscheduled due to idling 647system.cpu.committedInsts 4591 # Number of Instructions Simulated 648system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 649system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 650system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 651system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 652system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 653system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 654system.cpu.int_regfile_reads 39210 # number of integer regfile reads 655system.cpu.int_regfile_writes 7985 # number of integer regfile writes 656system.cpu.fp_regfile_reads 16 # number of floating regfile reads 657system.cpu.misc_regfile_reads 3239 # number of misc regfile reads 658system.cpu.misc_regfile_writes 24 # number of misc regfile writes 659system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 660system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 661system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 662system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 663system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 664system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 665system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 666system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 667system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 668system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 669system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 670system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 671system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 672system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 673system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 674system.cpu.toL2Bus.respLayer0.occupancy 479750 # Layer occupancy (ticks) 675system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 676system.cpu.toL2Bus.respLayer1.occupancy 229245 # Layer occupancy (ticks) 677system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 678system.cpu.icache.tags.replacements 4 # number of replacements 679system.cpu.icache.tags.tagsinuse 148.072869 # Cycle average of tags in use 680system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 681system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 682system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 683system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 684system.cpu.icache.tags.occ_blocks::cpu.inst 148.072869 # Average occupied blocks per requestor 685system.cpu.icache.tags.occ_percent::cpu.inst 0.072301 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_percent::total 0.072301 # Average percentage of cache occupancy 687system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 689system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 690system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 691system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 692system.cpu.icache.tags.data_accesses 4184 # Number of data accesses 693system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 694system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 695system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 696system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 697system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 698system.cpu.icache.overall_hits::total 1584 # number of overall hits 699system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 700system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 701system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 702system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 703system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 704system.cpu.icache.overall_misses::total 363 # number of overall misses 705system.cpu.icache.ReadReq_miss_latency::cpu.inst 23913500 # number of ReadReq miss cycles 706system.cpu.icache.ReadReq_miss_latency::total 23913500 # number of ReadReq miss cycles 707system.cpu.icache.demand_miss_latency::cpu.inst 23913500 # number of demand (read+write) miss cycles 708system.cpu.icache.demand_miss_latency::total 23913500 # number of demand (read+write) miss cycles 709system.cpu.icache.overall_miss_latency::cpu.inst 23913500 # number of overall miss cycles 710system.cpu.icache.overall_miss_latency::total 23913500 # number of overall miss cycles 711system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 713system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 714system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 715system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 716system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 717system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 718system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 719system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 720system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 721system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 722system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 723system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468 # average ReadReq miss latency 724system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468 # average ReadReq miss latency 725system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 726system.cpu.icache.demand_avg_miss_latency::total 65877.410468 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468 # average overall miss latency 728system.cpu.icache.overall_avg_miss_latency::total 65877.410468 # average overall miss latency 729system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 730system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 731system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 732system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 733system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 734system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 735system.cpu.icache.fast_writes 0 # number of fast writes performed 736system.cpu.icache.cache_copies 0 # number of cache copies performed 737system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 738system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 739system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 740system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 741system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 742system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 743system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 744system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 745system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 746system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 747system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 748system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 749system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19169750 # number of ReadReq MSHR miss cycles 750system.cpu.icache.ReadReq_mshr_miss_latency::total 19169750 # number of ReadReq MSHR miss cycles 751system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19169750 # number of demand (read+write) MSHR miss cycles 752system.cpu.icache.demand_mshr_miss_latency::total 19169750 # number of demand (read+write) MSHR miss cycles 753system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19169750 # number of overall MSHR miss cycles 754system.cpu.icache.overall_mshr_miss_latency::total 19169750 # number of overall MSHR miss cycles 755system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 756system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 757system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 758system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 759system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 760system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 761system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207 # average ReadReq mshr miss latency 762system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207 # average ReadReq mshr miss latency 763system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 764system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 765system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207 # average overall mshr miss latency 766system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207 # average overall mshr miss latency 767system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 768system.cpu.l2cache.tags.replacements 0 # number of replacements 769system.cpu.l2cache.tags.tagsinuse 186.546841 # Cycle average of tags in use 770system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 771system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 772system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 773system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 774system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.414103 # Average occupied blocks per requestor 775system.cpu.l2cache.tags.occ_blocks::cpu.data 47.132739 # Average occupied blocks per requestor 776system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004255 # Average percentage of cache occupancy 777system.cpu.l2cache.tags.occ_percent::cpu.data 0.001438 # Average percentage of cache occupancy 778system.cpu.l2cache.tags.occ_percent::total 0.005693 # Average percentage of cache occupancy 779system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 780system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 782system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 783system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 784system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 785system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 786system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 787system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 788system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 789system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 790system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 791system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 792system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 793system.cpu.l2cache.overall_hits::total 40 # number of overall hits 794system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 795system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 796system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 797system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 798system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 799system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 800system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 801system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 802system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 803system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 804system.cpu.l2cache.overall_misses::total 397 # number of overall misses 805system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18673250 # number of ReadReq miss cycles 806system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669500 # number of ReadReq miss cycles 807system.cpu.l2cache.ReadReq_miss_latency::total 25342750 # number of ReadReq miss cycles 808system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2970250 # number of ReadExReq miss cycles 809system.cpu.l2cache.ReadExReq_miss_latency::total 2970250 # number of ReadExReq miss cycles 810system.cpu.l2cache.demand_miss_latency::cpu.inst 18673250 # number of demand (read+write) miss cycles 811system.cpu.l2cache.demand_miss_latency::cpu.data 9639750 # number of demand (read+write) miss cycles 812system.cpu.l2cache.demand_miss_latency::total 28313000 # number of demand (read+write) miss cycles 813system.cpu.l2cache.overall_miss_latency::cpu.inst 18673250 # number of overall miss cycles 814system.cpu.l2cache.overall_miss_latency::cpu.data 9639750 # number of overall miss cycles 815system.cpu.l2cache.overall_miss_latency::total 28313000 # number of overall miss cycles 816system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 817system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 818system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 819system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 820system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 821system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 822system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 823system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 824system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 825system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 826system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 827system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 828system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 829system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 830system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 831system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 832system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 833system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 834system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 835system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 836system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 837system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 838system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185 # average ReadReq miss latency 839system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581 # average ReadReq miss latency 840system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000 # average ReadReq miss latency 841system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951 # average ReadExReq miss latency 842system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951 # average ReadExReq miss latency 843system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 844system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 845system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353 # average overall miss latency 846system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185 # average overall miss latency 847system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307 # average overall miss latency 848system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353 # average overall miss latency 849system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 850system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 851system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 852system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 853system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 854system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 855system.cpu.l2cache.fast_writes 0 # number of fast writes performed 856system.cpu.l2cache.cache_copies 0 # number of cache copies performed 857system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 858system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 859system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 860system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 861system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 862system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 863system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 864system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 865system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 867system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 868system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 869system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 870system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 871system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 872system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 873system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 874system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15282750 # number of ReadReq MSHR miss cycles 875system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5380500 # number of ReadReq MSHR miss cycles 876system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20663250 # number of ReadReq MSHR miss cycles 877system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2466250 # number of ReadExReq MSHR miss cycles 878system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2466250 # number of ReadExReq MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15282750 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7846750 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.demand_mshr_miss_latency::total 23129500 # number of demand (read+write) MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15282750 # number of overall MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7846750 # number of overall MSHR miss cycles 884system.cpu.l2cache.overall_mshr_miss_latency::total 23129500 # number of overall MSHR miss cycles 885system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 886system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 887system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 888system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 889system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 890system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 891system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 892system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 893system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 894system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 895system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 896system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778 # average ReadReq mshr miss latency 897system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926 # average ReadReq mshr miss latency 898system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120 # average ReadReq mshr miss latency 899system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024 # average ReadExReq mshr miss latency 900system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024 # average ReadExReq mshr miss latency 901system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 903system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 904system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951 # average overall mshr miss latency 906system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531 # average overall mshr miss latency 907system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 908system.cpu.dcache.tags.replacements 0 # number of replacements 909system.cpu.dcache.tags.tagsinuse 87.464066 # Cycle average of tags in use 910system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. 911system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 912system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. 913system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 914system.cpu.dcache.tags.occ_blocks::cpu.data 87.464066 # Average occupied blocks per requestor 915system.cpu.dcache.tags.occ_percent::cpu.data 0.021354 # Average percentage of cache occupancy 916system.cpu.dcache.tags.occ_percent::total 0.021354 # Average percentage of cache occupancy 917system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 918system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 919system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 920system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 921system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses 922system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses 923system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 924system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 925system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 926system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 927system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 928system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 929system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 930system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 931system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 932system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 933system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 934system.cpu.dcache.overall_hits::total 2373 # number of overall hits 935system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 936system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 937system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 938system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 939system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 940system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 941system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 942system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 943system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 944system.cpu.dcache.overall_misses::total 496 # number of overall misses 945system.cpu.dcache.ReadReq_miss_latency::cpu.data 11356993 # number of ReadReq miss cycles 946system.cpu.dcache.ReadReq_miss_latency::total 11356993 # number of ReadReq miss cycles 947system.cpu.dcache.WriteReq_miss_latency::cpu.data 19957500 # number of WriteReq miss cycles 948system.cpu.dcache.WriteReq_miss_latency::total 19957500 # number of WriteReq miss cycles 949system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 950system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 951system.cpu.dcache.demand_miss_latency::cpu.data 31314493 # number of demand (read+write) miss cycles 952system.cpu.dcache.demand_miss_latency::total 31314493 # number of demand (read+write) miss cycles 953system.cpu.dcache.overall_miss_latency::cpu.data 31314493 # number of overall miss cycles 954system.cpu.dcache.overall_miss_latency::total 31314493 # number of overall miss cycles 955system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 956system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 957system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 958system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 959system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 960system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 961system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 962system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 963system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 964system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 965system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 966system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 967system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 968system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 969system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 970system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 971system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 972system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 973system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 974system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 975system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 976system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 977system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053 # average ReadReq miss latency 978system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053 # average ReadReq miss latency 979system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322 # average WriteReq miss latency 980system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322 # average WriteReq miss latency 981system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 982system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 983system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 984system.cpu.dcache.demand_avg_miss_latency::total 63134.058468 # average overall miss latency 985system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468 # average overall miss latency 986system.cpu.dcache.overall_avg_miss_latency::total 63134.058468 # average overall miss latency 987system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 988system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 989system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 990system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 991system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 992system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 993system.cpu.dcache.fast_writes 0 # number of fast writes performed 994system.cpu.dcache.cache_copies 0 # number of cache copies performed 995system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 996system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 997system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 998system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 999system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1000system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1001system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 1002system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 1003system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 1004system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 1005system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 1006system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 1007system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 1008system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 1009system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 1010system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 1011system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 1012system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 1013system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979505 # number of ReadReq MSHR miss cycles 1014system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979505 # number of ReadReq MSHR miss cycles 1015system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3012250 # number of WriteReq MSHR miss cycles 1016system.cpu.dcache.WriteReq_mshr_miss_latency::total 3012250 # number of WriteReq MSHR miss cycles 1017system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9991755 # number of demand (read+write) MSHR miss cycles 1018system.cpu.dcache.demand_mshr_miss_latency::total 9991755 # number of demand (read+write) MSHR miss cycles 1019system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9991755 # number of overall MSHR miss cycles 1020system.cpu.dcache.overall_mshr_miss_latency::total 9991755 # number of overall MSHR miss cycles 1021system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 1022system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 1023system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 1024system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 1025system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 1026system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 1027system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 1028system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 1029system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792 # average ReadReq mshr miss latency 1030system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792 # average ReadReq mshr miss latency 1031system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195 # average WriteReq mshr miss latency 1032system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195 # average WriteReq mshr miss latency 1033system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 1034system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 1035system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449 # average overall mshr miss latency 1036system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449 # average overall mshr miss latency 1037system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038 1039---------- End Simulation Statistics ---------- 1040