stats.txt revision 9481
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 39322Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49459Ssaidi@eecs.umich.edusim_ticks 13354000 # Number of ticks simulated 59459Ssaidi@eecs.umich.edufinal_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 79481Snilay@cs.wisc.eduhost_inst_rate 22763 # Simulator instruction rate (inst/s) 89481Snilay@cs.wisc.eduhost_op_rate 28403 # Simulator op (including micro ops) rate (op/s) 99481Snilay@cs.wisc.eduhost_tick_rate 66199618 # Simulator tick rate (ticks/s) 109481Snilay@cs.wisc.eduhost_mem_usage 285296 # Number of bytes of host memory used 119481Snilay@cs.wisc.eduhost_seconds 0.20 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 5729 # Number of ops (including micro ops) simulated 149348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 159312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 25216 # Number of bytes read from this memory 179348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 189348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 199348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 209312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 219348SAli.Saidi@ARM.comsystem.physmem.num_reads::total 394 # Number of read requests responded to by this memory 229459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) 239459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) 249459Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) 259459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) 269459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) 279459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) 289459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) 299459Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) 309348SAli.Saidi@ARM.comsystem.physmem.readReqs 394 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329348SAli.Saidi@ARM.comsystem.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 339348SAli.Saidi@ARM.comsystem.physmem.bytesRead 25216 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis 409348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis 419348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis 429348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis 439322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis 449348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis 459312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis 469312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis 479312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis 489312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis 499312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis 529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis 539348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis 549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739459Ssaidi@eecs.umich.edusystem.physmem.totGap 13296500 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809348SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 394 # Categorize read packet sizes 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see 1029322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see 1039348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 1049348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 1059348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 1069348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 1079348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.totQLat 2460894 # Total cycles spent in queuing delays 1689348SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 1699348SAli.Saidi@ARM.comsystem.physmem.totBusLat 1576000 # Total cycles spent in databus access 1709348SAli.Saidi@ARM.comsystem.physmem.totBankLat 6524000 # Total cycles spent in bank access 1719348SAli.Saidi@ARM.comsystem.physmem.avgQLat 6245.92 # Average queueing delay per request 1729348SAli.Saidi@ARM.comsystem.physmem.avgBankLat 16558.38 # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749348SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 26804.30 # Average memory access latency 1759459Ssaidi@eecs.umich.edusystem.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779459Ssaidi@eecs.umich.edusystem.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809459Ssaidi@eecs.umich.edusystem.physmem.busUtil 11.80 # Data bus utilization in percentage 1819348SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 0.79 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839348SAli.Saidi@ARM.comsystem.physmem.readRowHits 319 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879459Ssaidi@eecs.umich.edusystem.physmem.avgGap 33747.46 # Average gap between requests 1889481Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2501 # Number of BP lookups 1899481Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted 1909481Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect 1919481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups 1929481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 702 # Number of BTB hits 1939481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1949481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage 1959481Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. 1969481Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 1978889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 1988889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 1998889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 2008889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 2018889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 2028889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 2038889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2048889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2058889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2068889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2078889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2088889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2098889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2108889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2118889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2128889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 2138889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 2148889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 2158889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 2168889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 2178889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 2188889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 2198889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 2208889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 2218889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 2228889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 2238889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 2248889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 2258889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2268889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2278889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2288889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2298889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2308889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2318889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2328889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2338889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 2348889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 2358889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 2368889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 2378889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 2388889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 2398889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 2409459Ssaidi@eecs.umich.edusystem.cpu.checker.numCycles 5742 # number of cpu cycles simulated 2418889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 2428889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 2438889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 2448889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 2458889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 2468889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 2478889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 2488889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 2498889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2508889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2518889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2528889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2538889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2548889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2558889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2568889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2578889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2588889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 2598889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 2608889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 2618889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 2628889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 2638889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 2648889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 2658889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 2668889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 2678889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 2688889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 2698889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 2708889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 2718889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2728889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2738889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2748889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2758889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2768889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2778889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2788889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2798889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 2808889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 2818889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 2828889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 2838889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 2848889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 2859459Ssaidi@eecs.umich.edusystem.cpu.numCycles 26709 # number of cpu cycles simulated 2868889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2878889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2889459Ssaidi@eecs.umich.edusystem.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss 2899459Ssaidi@eecs.umich.edusystem.cpu.fetch.Insts 12010 # Number of instructions fetch has processed 2909459Ssaidi@eecs.umich.edusystem.cpu.fetch.Branches 2501 # Number of branches that fetch encountered 2919459Ssaidi@eecs.umich.edusystem.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken 2929459Ssaidi@eecs.umich.edusystem.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked 2939459Ssaidi@eecs.umich.edusystem.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing 2949459Ssaidi@eecs.umich.edusystem.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked 2959459Ssaidi@eecs.umich.edusystem.cpu.fetch.CacheLines 1956 # Number of cache lines fetched 2969459Ssaidi@eecs.umich.edusystem.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 2979459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) 2989459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) 2999459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) 3008889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3019459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) 3029459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) 3039459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) 3049459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) 3059459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) 3069459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) 3079459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) 3089459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) 3099459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) 3108889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3118889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3128889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3139459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) 3149459Ssaidi@eecs.umich.edusystem.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle 3159459Ssaidi@eecs.umich.edusystem.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle 3169459Ssaidi@eecs.umich.edusystem.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle 3179459Ssaidi@eecs.umich.edusystem.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked 3189459Ssaidi@eecs.umich.edusystem.cpu.decode.RunCycles 2444 # Number of cycles decode is running 3199348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 3209348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing 3219459Ssaidi@eecs.umich.edusystem.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch 3229348SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 3239459Ssaidi@eecs.umich.edusystem.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode 3249348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 3259348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing 3269459Ssaidi@eecs.umich.edusystem.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle 3279348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 3289459Ssaidi@eecs.umich.edusystem.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst 3299459Ssaidi@eecs.umich.edusystem.cpu.rename.RunCycles 2245 # Number of cycles rename is running 3309459Ssaidi@eecs.umich.edusystem.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 3319459Ssaidi@eecs.umich.edusystem.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename 3329348SAli.Saidi@ARM.comsystem.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 3339348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 3349348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full 3359459Ssaidi@eecs.umich.edusystem.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed 3369459Ssaidi@eecs.umich.edusystem.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made 3379459Ssaidi@eecs.umich.edusystem.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups 3389348SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 3399459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 3409459Ssaidi@eecs.umich.edusystem.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing 3419459Ssaidi@eecs.umich.edusystem.cpu.rename.serializingInsts 41 # count of serializing insts renamed 3429459Ssaidi@eecs.umich.edusystem.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 3439459Ssaidi@eecs.umich.edusystem.cpu.rename.skidInsts 677 # count of insts added to the skid buffer 3449459Ssaidi@eecs.umich.edusystem.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. 3459459Ssaidi@eecs.umich.edusystem.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. 3469459Ssaidi@eecs.umich.edusystem.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 3479348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 3489459Ssaidi@eecs.umich.edusystem.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) 3499459Ssaidi@eecs.umich.edusystem.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 3509348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 3519348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 3529459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling 3539459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph 3549459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 3559459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle 3569459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle 3579459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle 3588889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3599459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle 3609459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle 3619459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle 3629459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle 3639459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle 3649459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle 3659459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle 3669348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 3679348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 3688889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3698889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3708889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3719459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle 3728889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3739348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 3749348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 3759348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 3769348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 3779348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 3789348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 3799348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 3809348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 3819348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 3829348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 3839348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 3849348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 3859348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 3869348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 3879348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 3889348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 3899348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 3909348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 3919348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 3929348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 3939348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 3949348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 3959348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 3969348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 3979348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 3989348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 3999348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 4009348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 4019348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 4029348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available 4039348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available 4048889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4058889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4068889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 4079459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued 4089459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued 4099459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued 4109459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued 4119459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued 4129459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued 4139459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued 4149459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued 4159459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued 4169459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued 4179459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued 4189459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued 4199459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued 4209459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued 4219459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued 4229459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued 4239459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued 4249459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued 4259459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued 4269459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued 4279459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued 4289459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued 4299459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued 4309459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued 4319459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued 4329459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued 4339459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued 4349459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued 4359459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued 4369459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued 4379459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued 4388889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4398889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4409348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8988 # Type of FU issued 4419459Ssaidi@eecs.umich.edusystem.cpu.iq.rate 0.336516 # Inst issue rate 4429348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 228 # FU busy when requested 4439348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) 4449459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads 4459459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes 4469459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses 4478889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 4489322Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 4498889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 4509348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 4518889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 4529348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 4538889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4549348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed 4559312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 4569459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations 4579459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed 4588889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4598889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4608889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 4619348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 4628889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4639348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 4649348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 4659348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 4669459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ 4679459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch 4689459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions 4699459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions 4709459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 4719348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 4729285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4739459Ssaidi@eecs.umich.edusystem.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations 4749459Ssaidi@eecs.umich.edusystem.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly 4759459Ssaidi@eecs.umich.edusystem.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly 4769459Ssaidi@eecs.umich.edusystem.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute 4779459Ssaidi@eecs.umich.edusystem.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions 4789348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 4799459Ssaidi@eecs.umich.edusystem.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute 4808889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 4819348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 4829459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_refs 3303 # number of memory reference insts executed 4839459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_branches 1443 # Number of branches executed 4849459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_stores 1167 # Number of stores executed 4859459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_rate 0.320604 # Inst execution rate 4869459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit 4879459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_count 8105 # cumulative count of insts written-back 4889459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_producers 3904 # num instructions producing a value 4899459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_consumers 7842 # num instructions consuming a value 4908889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4919459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_rate 0.303456 # insts written-back per cycle 4929459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back 4938889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4949459Ssaidi@eecs.umich.edusystem.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit 4959459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 4969459Ssaidi@eecs.umich.edusystem.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted 4979459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle 4989459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle 4999459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle 5008889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5019459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle 5029459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle 5039459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle 5049459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle 5059459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle 5069348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle 5079348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle 5089348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle 5099348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle 5108889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5118889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5128889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5139459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle 5149459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 4591 # Number of instructions committed 5159459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 5168889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5179459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 2138 # Number of memory references committed 5189459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 1200 # Number of loads committed 5198889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 5209459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 1007 # Number of branches committed 5218889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 5229459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 5238889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 5249348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 5258889Sgeoffrey.blake@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5269459Ssaidi@eecs.umich.edusystem.cpu.rob.rob_reads 22955 # The number of ROB reads 5279459Ssaidi@eecs.umich.edusystem.cpu.rob.rob_writes 23605 # The number of ROB writes 5289348SAli.Saidi@ARM.comsystem.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 5299449SAli.Saidi@ARM.comsystem.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling 5309459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 4591 # Number of Instructions Simulated 5319459Ssaidi@eecs.umich.edusystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 5329459Ssaidi@eecs.umich.edusystem.cpu.committedInsts_total 4591 # Number of Instructions Simulated 5339459Ssaidi@eecs.umich.edusystem.cpu.cpi 5.817687 # CPI: Cycles Per Instruction 5349459Ssaidi@eecs.umich.edusystem.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads 5359459Ssaidi@eecs.umich.edusystem.cpu.ipc 0.171890 # IPC: Instructions Per Cycle 5369459Ssaidi@eecs.umich.edusystem.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads 5379459Ssaidi@eecs.umich.edusystem.cpu.int_regfile_reads 39368 # number of integer regfile reads 5389459Ssaidi@eecs.umich.edusystem.cpu.int_regfile_writes 8018 # number of integer regfile writes 5398889Sgeoffrey.blake@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 5409459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_reads 2982 # number of misc regfile reads 5419459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 5429459Ssaidi@eecs.umich.edusystem.cpu.icache.replacements 3 # number of replacements 5439459Ssaidi@eecs.umich.edusystem.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use 5449459Ssaidi@eecs.umich.edusystem.cpu.icache.total_refs 1597 # Total number of references to valid blocks. 5459459Ssaidi@eecs.umich.edusystem.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. 5469459Ssaidi@eecs.umich.edusystem.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. 5478889Sgeoffrey.blake@arm.comsystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5489459Ssaidi@eecs.umich.edusystem.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor 5499459Ssaidi@eecs.umich.edusystem.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy 5509459Ssaidi@eecs.umich.edusystem.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy 5519459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits 5529459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits 5539459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits 5549459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits 5559459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits 5569459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_hits::total 1597 # number of overall hits 5579459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses 5589459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses 5599459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses 5609459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses 5619459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses 5629459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_misses::total 359 # number of overall misses 5639459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles 5649459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles 5659459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles 5669459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles 5679459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles 5689459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles 5699459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) 5709459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 5719459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses 5729459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses 5739459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses 5749459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses 5759459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses 5769459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses 5779459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses 5789459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses 5799459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses 5809459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses 5819459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency 5829459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency 5839459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency 5849459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency 5859459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency 5869459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency 5879322Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 5888889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5899322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 5908889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5919322Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 5928983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5938889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 5948889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 5959449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 5969449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 5979449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 5989449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 5999449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 6009449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 6019459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 6029459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 6039459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 6049459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 6059459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 6069459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses 6079459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles 6089459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles 6099459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles 6109459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles 6119459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles 6129459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles 6139459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses 6149459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses 6159459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses 6169459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses 6179459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses 6189459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses 6199459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency 6209459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency 6219459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency 6229459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency 6239459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency 6249459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency 6258889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6269449SAli.Saidi@ARM.comsystem.cpu.l2cache.replacements 0 # number of replacements 6279459Ssaidi@eecs.umich.edusystem.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use 6289459Ssaidi@eecs.umich.edusystem.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. 6299449SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 6309459Ssaidi@eecs.umich.edusystem.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. 6319449SAli.Saidi@ARM.comsystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6329459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor 6339459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor 6349459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy 6359459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy 6369459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy 6379459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 6389449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 6399459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 6409459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 6419449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 6429459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 6439459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 6449449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 6459459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_hits::total 39 # number of overall hits 6469449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 6479449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 6489449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 6499449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 6509449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 6519449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 6529449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 6539449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 6549449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 6559449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 6569449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 399 # number of overall misses 6579449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles 6589449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles 6599449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles 6609449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 6619449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 6629449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles 6639449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles 6649449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles 6659449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles 6669449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles 6679449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles 6689459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 6699449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 6709459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 6719449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 6729449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 6739459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 6749449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 6759459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 6769459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 6779449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 6789459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses 6799459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses 6809449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 6819459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses 6829449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6839449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6849459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses 6859449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 6869459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses 6879459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses 6889449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 6899459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses 6909449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency 6919449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency 6929449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency 6939449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 6949449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 6959449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 6969449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 6979449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency 6989449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 6999449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 7009449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency 7019449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7029449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7039449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7049449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7059449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7069449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7079449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7089449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7099449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 7109449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 7119449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 7129449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 7139449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 7149449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 7159449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 7169449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 7179449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 7189449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 7199449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 7209449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 7219449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 7229449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 7239449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 7249449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 7259449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 7269449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles 7279449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles 7289449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles 7299449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 7309449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 7319449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles 7329449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles 7339449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles 7349449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles 7359449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles 7369449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles 7379459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses 7389449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 7399459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses 7409449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7419449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7429459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses 7439449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 7449459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses 7459459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses 7469449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 7479459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses 7489449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency 7499449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency 7509449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency 7519449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 7529449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 7539449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 7549449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 7559449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 7569449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 7579449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 7589449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 7599449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7608889Sgeoffrey.blake@arm.comsystem.cpu.dcache.replacements 0 # number of replacements 7619459Ssaidi@eecs.umich.edusystem.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use 7629459Ssaidi@eecs.umich.edusystem.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. 7639348SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 7649459Ssaidi@eecs.umich.edusystem.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. 7658889Sgeoffrey.blake@arm.comsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7669459Ssaidi@eecs.umich.edusystem.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor 7679459Ssaidi@eecs.umich.edusystem.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy 7689459Ssaidi@eecs.umich.edusystem.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy 7699459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 7709459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 7719348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 7729348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 7739459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 7749459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 7759459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 7769459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 7779459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 7789459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 7799459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 7809459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_hits::total 2373 # number of overall hits 7819348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 7829348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 7839348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 7849348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 7858889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 7868889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 7879348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 7889348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 7899348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 7909348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 498 # number of overall misses 7919449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles 7929449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles 7939348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 7949348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 7959322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 7969322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 7979449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles 7989449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles 7999449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles 8009449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles 8019459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) 8029459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) 8038889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 8048889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 8059459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 8069459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 8079459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 8089459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 8099459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses 8109459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses 8119459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses 8129459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses 8139459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses 8149459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses 8159348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 8169348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 8179459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 8189459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 8199459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses 8209459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses 8219459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses 8229459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses 8239449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency 8249449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency 8259348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 8269348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 8279322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 8289322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 8299449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 8309449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency 8319449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 8329449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency 8339348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 8348889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8359348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 8368889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 8379348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked 8388983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8398889Sgeoffrey.blake@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8408889Sgeoffrey.blake@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8419348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits 8429348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 8439348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 8449348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 8458889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 8468889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 8479348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits 8489348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 8499348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits 8509348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits 8519322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 8529322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 8539348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 8549348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 8559348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 8569348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 8579348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 8589348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 8599449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles 8609449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles 8619348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 8629348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles 8639449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles 8649449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles 8659449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles 8669449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles 8679459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses 8689459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses 8699348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 8709348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 8719459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses 8729459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses 8739459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses 8749459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses 8759449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency 8769449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency 8779348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 8789348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency 8799449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 8809449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 8819449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 8829449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 8838889Sgeoffrey.blake@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8848889Sgeoffrey.blake@arm.com 8858889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 886