stats.txt revision 9449
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 39322Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49449SAli.Saidi@ARM.comsim_ticks 13372000 # Number of ticks simulated 59449SAli.Saidi@ARM.comfinal_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 79449SAli.Saidi@ARM.comhost_inst_rate 16216 # Simulator instruction rate (inst/s) 89449SAli.Saidi@ARM.comhost_op_rate 20228 # Simulator op (including micro ops) rate (op/s) 99449SAli.Saidi@ARM.comhost_tick_rate 47166036 # Simulator tick rate (ticks/s) 109449SAli.Saidi@ARM.comhost_mem_usage 230800 # Number of bytes of host memory used 119449SAli.Saidi@ARM.comhost_seconds 0.28 # Real time elapsed on the host 129265SAli.Saidi@ARM.comsim_insts 4596 # Number of instructions simulated 139265SAli.Saidi@ARM.comsim_ops 5734 # Number of ops (including micro ops) simulated 149348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 159312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 25216 # Number of bytes read from this memory 179348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 189348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 199348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 209312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 219348SAli.Saidi@ARM.comsystem.physmem.num_reads::total 394 # Number of read requests responded to by this memory 229449SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) 239449SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) 249449SAli.Saidi@ARM.comsystem.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) 259449SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) 269449SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) 279449SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) 289449SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) 299449SAli.Saidi@ARM.comsystem.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) 309348SAli.Saidi@ARM.comsystem.physmem.readReqs 394 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329348SAli.Saidi@ARM.comsystem.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 339348SAli.Saidi@ARM.comsystem.physmem.bytesRead 25216 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis 409348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis 419348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis 429348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis 439322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis 449348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis 459312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis 469312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis 479312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis 489312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis 499312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis 529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis 539348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis 549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739449SAli.Saidi@ARM.comsystem.physmem.totGap 13314500 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809348SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 394 # Categorize read packet sizes 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see 1029322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see 1039348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 1049348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 1059348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 1069348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 1079348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.totQLat 2460894 # Total cycles spent in queuing delays 1689348SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 1699348SAli.Saidi@ARM.comsystem.physmem.totBusLat 1576000 # Total cycles spent in databus access 1709348SAli.Saidi@ARM.comsystem.physmem.totBankLat 6524000 # Total cycles spent in bank access 1719348SAli.Saidi@ARM.comsystem.physmem.avgQLat 6245.92 # Average queueing delay per request 1729348SAli.Saidi@ARM.comsystem.physmem.avgBankLat 16558.38 # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749348SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 26804.30 # Average memory access latency 1759449SAli.Saidi@ARM.comsystem.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779449SAli.Saidi@ARM.comsystem.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809348SAli.Saidi@ARM.comsystem.physmem.busUtil 11.79 # Data bus utilization in percentage 1819348SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 0.79 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839348SAli.Saidi@ARM.comsystem.physmem.readRowHits 319 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879449SAli.Saidi@ARM.comsystem.physmem.avgGap 33793.15 # Average gap between requests 1888889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 1898889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 1908889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 1918889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 1928889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 1938889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 1948889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 1958889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1968889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1978889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1988889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 1998889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2008889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2018889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2028889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2038889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 2048889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 2058889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 2068889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 2078889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 2088889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 2098889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 2108889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 2118889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 2128889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 2138889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 2148889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 2158889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 2168889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2178889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2188889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2198889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2208889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2218889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2228889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2238889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2248889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 2258889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 2268889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 2278889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 2288889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 2298889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 2308889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 2319265SAli.Saidi@ARM.comsystem.cpu.checker.numCycles 5747 # number of cpu cycles simulated 2328889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 2338889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 2348889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 2358889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 2368889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 2378889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 2388889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 2398889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 2408889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2418889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2428889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2438889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2448889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2458889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2468889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2478889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2488889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2498889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 2508889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 2518889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 2528889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 2538889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 2548889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 2558889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 2568889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 2578889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 2588889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 2598889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 2608889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 2618889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 2628889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2638889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2648889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2658889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2668889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2678889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2688889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2698889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2708889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 2718889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 2728889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 2738889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 2748889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 2758889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 2769449SAli.Saidi@ARM.comsystem.cpu.numCycles 26745 # number of cpu cycles simulated 2778889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2788889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2799348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2505 # Number of BP lookups 2809348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted 2819348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect 2829322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups 2839348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 707 # Number of BTB hits 2848889Sgeoffrey.blake@arm.comsystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2859348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. 2869348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 2879449SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss 2889348SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 12026 # Number of instructions fetch has processed 2899348SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2505 # Number of branches that fetch encountered 2909348SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken 2919348SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked 2929348SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing 2939449SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked 2949449SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 2959449SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed 2969449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) 2979449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) 2989449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) 2998889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3009449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) 3019449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) 3029348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) 3039348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) 3049348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) 3059348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) 3069348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) 3079348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) 3089348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) 3098889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3108889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3118889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3129449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) 3139449SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle 3149449SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle 3159348SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle 3169449SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked 3179348SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2446 # Number of cycles decode is running 3189348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 3199348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing 3209348SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch 3219348SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 3229348SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode 3239348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 3249348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing 3259348SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle 3269348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 3279348SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst 3289348SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2247 # Number of cycles rename is running 3299449SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 3309449SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename 3319348SAli.Saidi@ARM.comsystem.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 3329348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 3339348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full 3349449SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed 3359449SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made 3369449SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups 3379348SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 3389265SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 3399449SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing 3409348SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 44 # count of serializing insts renamed 3419348SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed 3429348SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 683 # count of insts added to the skid buffer 3439348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. 3449348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. 3459348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. 3469348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 3479348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) 3489348SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ 3499348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 3509348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 3519348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling 3529348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph 3539348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed 3549449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle 3559449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle 3569449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle 3578889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3589449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle 3599348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle 3609449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle 3619348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle 3629348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle 3639348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle 3649348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle 3659348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 3669348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 3678889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3688889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3698889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3709449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle 3718889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3729348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 3739348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 3749348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 3759348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 3769348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 3779348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 3789348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 3799348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 3809348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 3819348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 3829348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 3839348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 3849348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 3859348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 3869348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 3879348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 3889348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 3899348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 3909348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 3919348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 3929348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 3939348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 3949348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 3959348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 3969348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 3979348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 3989348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 3999348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 4009348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 4019348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available 4029348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available 4038889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4048889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4058889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 4069348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued 4079348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued 4089348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued 4099348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued 4109348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued 4119348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued 4129348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued 4139348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued 4149348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued 4159348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued 4169348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued 4179348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued 4189348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued 4199348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued 4209348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued 4219348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued 4229348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued 4239348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued 4249348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued 4259348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued 4269348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued 4279348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued 4289348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued 4299348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued 4309348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued 4319348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued 4329348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued 4339348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued 4349348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued 4359348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued 4369348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued 4378889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4388889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4399348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8988 # Type of FU issued 4409449SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.336063 # Inst issue rate 4419348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 228 # FU busy when requested 4429348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) 4439449SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads 4449348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes 4459348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses 4468889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 4479322Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 4488889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 4499348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 4508889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 4519348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 4528889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4539348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed 4549312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 4559348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 4569348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed 4578889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4588889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4598889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 4609348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 4618889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4629348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 4639348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 4649348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 4659348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ 4669449SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch 4679348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions 4689348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions 4699348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions 4709348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 4719285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4729348SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 4739348SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 4749348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 4759348SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute 4769348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions 4779348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 4789348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute 4798889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 4809348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 4819348SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3300 # number of memory reference insts executed 4829348SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1446 # Number of branches executed 4839348SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1164 # Number of stores executed 4849449SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.320209 # Inst execution rate 4859348SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit 4869348SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 8109 # cumulative count of insts written-back 4879348SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 3899 # num instructions producing a value 4889348SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 7837 # num instructions consuming a value 4898889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4909449SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.303197 # insts written-back per cycle 4919348SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back 4928889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4939348SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit 4949265SAli.Saidi@ARM.comsystem.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 4959348SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 4969348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle 4979348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle 4989348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle 4998889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 5009348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle 5019348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle 5029348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle 5039348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle 5049348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle 5059348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle 5069348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle 5079348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle 5089348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle 5098889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5108889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5118889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 5129348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle 5139265SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 4596 # Number of instructions committed 5149265SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed 5158889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5169265SAli.Saidi@ARM.comsystem.cpu.commit.refs 2140 # Number of memory references committed 5179265SAli.Saidi@ARM.comsystem.cpu.commit.loads 1201 # Number of loads committed 5188889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 5199265SAli.Saidi@ARM.comsystem.cpu.commit.branches 1008 # Number of branches committed 5208889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 5219265SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 4980 # Number of committed integer instructions. 5228889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 5239348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 5248889Sgeoffrey.blake@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5259348SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 22988 # The number of ROB reads 5269348SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 23599 # The number of ROB writes 5279348SAli.Saidi@ARM.comsystem.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 5289449SAli.Saidi@ARM.comsystem.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling 5299265SAli.Saidi@ARM.comsystem.cpu.committedInsts 4596 # Number of Instructions Simulated 5309265SAli.Saidi@ARM.comsystem.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 5319265SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 4596 # Number of Instructions Simulated 5329449SAli.Saidi@ARM.comsystem.cpu.cpi 5.819191 # CPI: Cycles Per Instruction 5339449SAli.Saidi@ARM.comsystem.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads 5349449SAli.Saidi@ARM.comsystem.cpu.ipc 0.171845 # IPC: Instructions Per Cycle 5359449SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads 5369348SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 39369 # number of integer regfile reads 5379348SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 8027 # number of integer regfile writes 5388889Sgeoffrey.blake@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 5399378Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 2981 # number of misc regfile reads 5409265SAli.Saidi@ARM.comsystem.cpu.misc_regfile_writes 26 # number of misc regfile writes 5419312Sandreas.hansson@arm.comsystem.cpu.icache.replacements 4 # number of replacements 5429449SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use 5439348SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1601 # Total number of references to valid blocks. 5449348SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. 5459348SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. 5468889Sgeoffrey.blake@arm.comsystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5479449SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor 5489449SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy 5499449SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy 5509348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits 5519348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits 5529348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits 5539348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits 5549348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits 5559348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1601 # number of overall hits 5569449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses 5579449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses 5589449SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses 5599449SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses 5609449SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses 5619449SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 360 # number of overall misses 5629449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles 5639449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles 5649449SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles 5659449SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles 5669449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles 5679449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles 5689449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) 5699449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) 5709449SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses 5719449SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses 5729449SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses 5739449SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses 5749449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses 5759449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses 5769449SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses 5779449SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses 5789449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses 5799449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses 5809449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency 5819449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency 5829449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency 5839449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency 5849449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency 5859449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency 5869322Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 5878889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5889322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 5898889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5909322Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 5918983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5928889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 5938889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 5949449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 5959449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 5969449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 5979449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 5989449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 5999449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 6009348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses 6019348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses 6029348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses 6039348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses 6049348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses 6059348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses 6069449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles 6079449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles 6089449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles 6099449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles 6109449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles 6119449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles 6129449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses 6139449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses 6149449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses 6159449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses 6169449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses 6179449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses 6189449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency 6199449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency 6209449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency 6219449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency 6229449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency 6239449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency 6248889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6259449SAli.Saidi@ARM.comsystem.cpu.l2cache.replacements 0 # number of replacements 6269449SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use 6279449SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 6289449SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 6299449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. 6309449SAli.Saidi@ARM.comsystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6319449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor 6329449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor 6339449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy 6349449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy 6359449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy 6369449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 6379449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 6389449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 6399449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 6409449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 6419449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 6429449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 6439449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 6449449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 40 # number of overall hits 6459449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 6469449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 6479449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 6489449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 6499449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 6509449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 6519449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 6529449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 6539449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 6549449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 6559449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 399 # number of overall misses 6569449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles 6579449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles 6589449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles 6599449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 6609449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 6619449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles 6629449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles 6639449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles 6649449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles 6659449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles 6669449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles 6679449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) 6689449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 6699449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 6709449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 6719449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 6729449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses 6739449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 6749449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses 6759449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses 6769449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 6779449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses 6789449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses 6799449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 6809449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses 6819449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6829449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6839449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses 6849449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 6859449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses 6869449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses 6879449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 6889449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses 6899449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency 6909449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency 6919449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency 6929449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 6939449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 6949449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 6959449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 6969449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency 6979449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 6989449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 6999449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency 7009449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7019449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7029449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7039449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7049449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7059449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7069449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7079449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7089449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 7099449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 7109449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 7119449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 7129449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 7139449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 7149449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 7159449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 7169449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 7179449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 7189449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 7199449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 7209449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 7219449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 7229449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 7239449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 7249449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 7259449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles 7269449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles 7279449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles 7289449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 7299449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 7309449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles 7319449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles 7329449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles 7339449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles 7349449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles 7359449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles 7369449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses 7379449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 7389449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses 7399449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7409449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7419449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses 7429449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 7439449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses 7449449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses 7459449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 7469449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses 7479449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency 7489449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency 7499449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency 7509449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 7519449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 7529449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 7539449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 7549449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 7559449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 7569449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 7579449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 7589449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7598889Sgeoffrey.blake@arm.comsystem.cpu.dcache.replacements 0 # number of replacements 7609449SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use 7619348SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. 7629348SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 7639348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. 7648889Sgeoffrey.blake@arm.comsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7659449SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor 7669449SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy 7679449SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy 7689348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits 7699348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits 7709348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 7719348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 7729265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 7739265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 7749265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 7759265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 7769348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits 7779348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits 7789348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits 7799348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2371 # number of overall hits 7809348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 7819348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 7829348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 7839348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 7848889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 7858889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 7869348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 7879348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 7889348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 7899348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 498 # number of overall misses 7909449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles 7919449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles 7929348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 7939348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 7949322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 7959322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 7969449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles 7979449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles 7989449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles 7999449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles 8009348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 8019348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 8028889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 8038889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 8049265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 8059265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 8069265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 8079265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 8089348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 8099348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 8109348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 8119348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 8129348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses 8139348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses 8149348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 8159348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 8169265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 8179265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 8189348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses 8199348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses 8209348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses 8219348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses 8229449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency 8239449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency 8249348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 8259348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 8269322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 8279322Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 8289449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 8299449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency 8309449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 8319449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency 8329348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 8338889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8349348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 8358889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 8369348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked 8378983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8388889Sgeoffrey.blake@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8398889Sgeoffrey.blake@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8409348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits 8419348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 8429348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 8439348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 8448889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 8458889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 8469348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits 8479348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 8489348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits 8499348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits 8509322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 8519322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 8529348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 8539348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 8549348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 8559348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 8569348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 8579348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 8589449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles 8599449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles 8609348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 8619348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles 8629449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles 8639449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles 8649449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles 8659449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles 8669348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 8679348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 8689348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 8699348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 8709348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 8719348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 8729348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 8739348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 8749449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency 8759449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency 8769348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 8779348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency 8789449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 8799449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 8809449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 8819449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 8828889Sgeoffrey.blake@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8838889Sgeoffrey.blake@arm.com 8848889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 885