stats.txt revision 11731
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.000018 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 18422500 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711687Sandreas.hansson@arm.comhost_inst_rate 76941 # Simulator instruction rate (inst/s) 811687Sandreas.hansson@arm.comhost_op_rate 90095 # Simulator op (including micro ops) rate (op/s) 911687Sandreas.hansson@arm.comhost_tick_rate 308579581 # Simulator tick rate (ticks/s) 1011687Sandreas.hansson@arm.comhost_mem_usage 270584 # Number of bytes of host memory used 1111687Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 4592 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 5378 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 1711440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 25408 # Number of bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 2211440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 2310892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 397 # Number of read requests responded to by this memory 2511680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) 2611680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) 2711680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) 2811680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) 2911680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) 3011680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) 3111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) 3211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) 3311440SCurtis.Dunham@arm.comsystem.physmem.readReqs 397 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511440SCurtis.Dunham@arm.comsystem.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 89 # Per bank write bursts 4610812Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 5010352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5411440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 9 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 5711440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 10 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911680SCurtis.Dunham@arm.comsystem.physmem.totGap 18337000 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 397 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see 9511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see 9611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 9711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 9811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 9911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 10010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation 19111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation 19211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation 19311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation 19411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation 19511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation 19611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation 19711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation 20011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation 20111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation 20311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation 20411680SCurtis.Dunham@arm.comsystem.physmem.totQLat 5196750 # Total ticks spent queuing 20511680SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM 20611440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 20711680SCurtis.Dunham@arm.comsystem.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst 2089978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911680SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst 21011680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511680SCurtis.Dunham@arm.comsystem.physmem.busUtil 10.77 # Data bus utilization in percentage 21611680SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads 2179978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811680SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing 2199978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 330 # Number of row buffer hits during reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads 2239312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411680SCurtis.Dunham@arm.comsystem.physmem.avgGap 46188.92 # Average gap between requests 22511606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined 22611680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 22711680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) 22811680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) 23111680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) 23211680SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) 23311680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) 23411680SCurtis.Dunham@arm.comsystem.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) 23511680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23611680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) 23711680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 660.613923 # Core power per rank (mW) 23811680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank 23911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states 24010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 24111680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 24211680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states 24311680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states 24411680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states 24511680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) 24611680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) 24810628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) 25011680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) 25111680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) 25211680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) 25311680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) 25411680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25511680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) 25611680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 569.303026 # Core power per rank (mW) 25711680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank 25811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states 25910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 26011680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 26111680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states 26211680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states 26311680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states 26411680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 26511680SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 2844 # Number of BP lookups 26611680SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted 26711440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 26811680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups 26911680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 867 # Number of BTB hits 2709481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage 27211440SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 27310812Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 27411680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. 27511680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 27611680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 253 # Number of indirect misses. 27711440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 27810628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27911680SCurtis.Dunham@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 28010628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 28110628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 28210628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 28310628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 28410628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 28510628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 28610628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 28710628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 28810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 29510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 29710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 29810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 29910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 30410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 30510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 30610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 30710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 30810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 30911680SCurtis.Dunham@arm.comsystem.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 31010628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 31110628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31210628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31310628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31410628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31510628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31610628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31710628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 3218889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 3228889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 3238889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 3248889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3258889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3268889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3278889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3288889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3298889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3308889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3318889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3328889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3338889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 3348889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 3358889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 3368889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 3378889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 3388889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 33911680SCurtis.Dunham@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 34010628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34110628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34210628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34310628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34410628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34510628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34610628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34710628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 35010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 35110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 35210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 35310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 35410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 36010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 36110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 36210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 36410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 36710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 36810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 36911680SCurtis.Dunham@arm.comsystem.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 37010628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walks 0 # Table walker walks requested 37110628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37210628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37310628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37410628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37510628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37610628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37710628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3788889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3798889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3808889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3818889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3828889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3838889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3848889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3858889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3868889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3878889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3888889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3898889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3908889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3918889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3928889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3938889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3948889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3958889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3968889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3978889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3988889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3998889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 40011680SCurtis.Dunham@arm.comsystem.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states 40110812Snilay@cs.wisc.edusystem.cpu.checker.numCycles 5391 # number of cpu cycles simulated 4028889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 4038889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 40411680SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 40510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 41510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 41610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 41710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 41810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 41910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 42510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 42610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 42710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 42910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 43310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43411680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 43510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 43610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 43710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 44210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4438889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 4448889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 4458889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4468889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4478889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4488889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4498889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4508889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4518889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4528889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4538889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 4548889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4558889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 4568889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4578889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4588889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 4598889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 4608889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 4618889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 4628889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 4638889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 46411680SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 46510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 46610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 46710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 47410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 47510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 47710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 48210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 48310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 48410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 48510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 48610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 48710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 48810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 48910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 49010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 49110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 49210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 49310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 49411680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 49510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 49610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 5038889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 5048889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 5058889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 5068889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 5078889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 5088889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 5098889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 5108889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 5118889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 5128889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 5138889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 5148889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 5158889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 5168889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 5178889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 5188889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 5198889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 5208889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 5218889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 5228889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 5238889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 52411680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states 52511680SCurtis.Dunham@arm.comsystem.cpu.numCycles 36846 # number of cpu cycles simulated 5268889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5278889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52811680SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss 52911680SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 12314 # Number of instructions fetch has processed 53011680SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 2844 # Number of branches that fetch encountered 53111680SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken 53211680SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked 53311440SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 53410812Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 53511680SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps 53610812Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 53711680SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 1962 # Number of cache lines fetched 53811606Sandreas.sandberg@arm.comsystem.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed 53911680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) 54011680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) 54111680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) 5428889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 54311680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) 54411680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) 54511680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) 54611680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) 54711680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) 54811680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) 54911680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) 55011680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) 55111680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) 5528889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5538889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5548889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 55511680SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) 55611680SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle 55711680SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle 55811680SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle 55911680SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked 56011680SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 2146 # Number of cycles decode is running 56111680SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 56211440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 56311440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 56411440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 56511680SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode 56611440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 56711440SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 56811680SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle 56911680SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking 57011680SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst 57111680SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 2033 # Number of cycles rename is running 57211680SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking 57311680SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename 57411440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 57511680SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full 57611680SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full 57711680SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full 57811680SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed 57911680SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made 58011680SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups 58111440SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 58210352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 58311680SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing 58411440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 40 # count of serializing insts renamed 58511440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed 58611680SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 446 # count of insts added to the skid buffer 58711680SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. 58811680SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. 58911680SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. 59011440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. 59111680SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) 59211680SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ 59311680SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 8096 # Number of instructions issued 59411680SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued 59511680SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling 59611680SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph 59711680SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed 59811680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle 59911680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle 60011680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle 6018889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 60211680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle 60311680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle 60411680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle 60511680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle 60611680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle 60711680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle 60811680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle 60911680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle 61011680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle 6118889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 6128889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 6138889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 61411680SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle 6158889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 61611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available 61711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available 61811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available 61911687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available 62011687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available 62111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available 62211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available 62311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available 62411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available 62511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available 62611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available 62711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available 62811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available 62911687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available 63011687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available 63111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available 63211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available 63311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available 63411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available 63511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available 63611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available 63711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available 63811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available 63911687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available 64011687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available 64111687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available 64211687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available 64311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available 64411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available 64511687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available 64611687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available 64711687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available 64811687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available 64911687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available 65011687Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available 6518889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6528889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6538889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 65411680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued 65511680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued 65611680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued 65711680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued 65811680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued 65911680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued 66011680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued 66111687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued 66211680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued 66311687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued 66411680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued 66511680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued 66611680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued 66711680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued 66811680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued 66911680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued 67011680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued 67111680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued 67211680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued 67311680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued 67411680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued 67511680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued 67611680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued 67711680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued 67811680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued 67911680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued 68011680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued 68111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued 68211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued 68311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued 68411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued 68511680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued 68611687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued 68711687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued 68811687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued 6898889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 6908889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 69111680SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 8096 # Type of FU issued 69211680SCurtis.Dunham@arm.comsystem.cpu.iq.rate 0.219725 # Inst issue rate 69311687Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 150 # FU busy when requested 69411687Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst) 69511680SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads 69611680SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes 69711680SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses 69811687Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads 69911440SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 70010726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 70111680SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses 70211687Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses 70311103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 7048889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 70511680SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed 7069312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 70710726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 70811680SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed 7098889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 7108889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 71111680SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled 71210812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 7138889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 71411440SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing 71511680SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking 71611440SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 71711680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ 71811680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch 71911680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions 72011680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions 72111680SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions 72211440SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 72310892Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 72410726Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 72511440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly 72611680SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly 72711680SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute 72811680SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions 72911680SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed 73011680SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute 7318889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 73210812Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 9 # number of nop insts executed 73311680SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 2921 # number of memory reference insts executed 73411680SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 1491 # Number of branches executed 73511680SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 1153 # Number of stores executed 73611680SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 0.211855 # Inst execution rate 73711680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit 73811680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 7436 # cumulative count of insts written-back 73911680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 3503 # num instructions producing a value 74011680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 6835 # num instructions consuming a value 74111680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 0.201813 # insts written-back per cycle 74211680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back 74311680SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit 7449459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 74511440SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted 74611680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle 74711680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle 74811680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle 7498889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 75011680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle 75111680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle 75211680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle 75311680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle 75411680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle 75511680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle 75611680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle 75711680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle 75811680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle 7598889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7608889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7618889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 76211680SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle 76310812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 4592 # Number of instructions committed 76410812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 7658889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 76610352Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 76710352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 7688889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 76910812Snilay@cs.wisc.edusystem.cpu.commit.branches 1008 # Number of branches committed 7708889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 77110352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 7728889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 77310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 77410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 77510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 77610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 77710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 77810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 77910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 78010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 78111687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction 78210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 78311687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction 78410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 78510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 78610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 78710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 78810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 78910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 79010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 79110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 79210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 79310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 79410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 79510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 79610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 79710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 79810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 79910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 80010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 80110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 80210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 80310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 80410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 80510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 80611687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction 80711687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 80811687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 80910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 81010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 81110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5378 # Class of committed instruction 81211440SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached 81311680SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 22637 # The number of ROB reads 81411680SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 21308 # The number of ROB writes 81511440SCurtis.Dunham@arm.comsystem.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself 81611680SCurtis.Dunham@arm.comsystem.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling 81710812Snilay@cs.wisc.edusystem.cpu.committedInsts 4592 # Number of Instructions Simulated 81810812Snilay@cs.wisc.edusystem.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 81911680SCurtis.Dunham@arm.comsystem.cpu.cpi 8.023955 # CPI: Cycles Per Instruction 82011680SCurtis.Dunham@arm.comsystem.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads 82111680SCurtis.Dunham@arm.comsystem.cpu.ipc 0.124627 # IPC: Instructions Per Cycle 82211680SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads 82311680SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 7656 # number of integer regfile reads 82411680SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 4268 # number of integer regfile writes 82510726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 32 # number of floating regfile reads 82611606Sandreas.sandberg@arm.comsystem.cpu.cc_regfile_reads 27780 # number of cc regfile reads 82711606Sandreas.sandberg@arm.comsystem.cpu.cc_regfile_writes 3273 # number of cc regfile writes 82811680SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 2974 # number of misc regfile reads 8299459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 83011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 83110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 83211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use 83311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. 83411103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 83511680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. 83610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 83711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor 83811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy 83911680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy 84011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 84111440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 84211440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 84311103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 84411680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses 84511680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 5335 # Number of data accesses 84611680SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 84711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits 84811680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits 84911440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 85011440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 85111440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 85211440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 85310628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 85410628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 85511680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits 85611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits 85711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits 85811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 2072 # number of overall hits 85911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 86011440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses 86111440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 86211440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 86310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 86410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 86511440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 86611440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 86711440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 86811440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 499 # number of overall misses 86911680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles 87011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles 87111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles 87211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles 87311680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles 87411680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles 87511680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles 87611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles 87711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles 87811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles 87911680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) 88011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) 88110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 88210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 88311440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 88411440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 88510628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 88610628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 88711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses 88811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses 88911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses 89011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses 89111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses 89211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses 89311440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 89411440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 89511440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 89611440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 89711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses 89811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses 89911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses 90011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses 90111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency 90211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency 90311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency 90411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency 90511680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency 90611680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency 90711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency 90811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency 90911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency 91011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency 91111680SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked 91210628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91311103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 91410628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 91511680SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 91610628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91711440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 91811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 91911440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 92011440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 92110628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 92210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 92311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 92411440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 92511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 92611440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 92710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 92810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 92910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 93010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 93110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 93210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 93310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 93410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 93511680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles 93611680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles 93711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles 93811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles 93911680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles 94011680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles 94111680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles 94211680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles 94311680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses 94411680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses 94510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 94610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 94711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses 94811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses 94911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses 95011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses 95111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency 95211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency 95311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency 95411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency 95511680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency 95611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency 95711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency 95811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency 95911680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 96011440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 2 # number of replacements 96111680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use 96211680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 96311440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 96411680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 9659838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 96611680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor 96711680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy 96811680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy 96910812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 97011680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id 97111680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 97210812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 97311680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses 97411680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 4218 # Number of data accesses 97511680SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 97611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 97711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 97811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 97911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 98011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 98111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 1577 # number of overall hits 98211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 98311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses 98411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses 98511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses 98611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses 98711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 385 # number of overall misses 98811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles 98911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles 99011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles 99111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles 99211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles 99311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles 99411680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) 99511680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) 99611680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses 99711680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses 99811680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses 99911680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses 100011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses 100111680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses 100211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses 100311680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses 100411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses 100511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses 100611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency 100711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency 100811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency 100911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency 101011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency 101111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency 101211680SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked 10138889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 101410352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 10158889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 101611680SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked 10178983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 101811440SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 2 # number of writebacks 101911440SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 2 # number of writebacks 102011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits 102111680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 102211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits 102311680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 102411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits 102511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits 102611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 102711440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 102811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 102911440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 103011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 103111440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 103211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles 103311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles 103411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles 103511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles 103611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles 103711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles 103811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses 103911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses 104011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses 104111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses 104211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses 104311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses 104411680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency 104511680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency 104611680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency 104711680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency 104811680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency 104911680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency 105011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 10519838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 105211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use 105310352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 105411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 105511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. 10569838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 105711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor 105811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor 105911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy 106011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy 106111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy 106211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 106311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id 106411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 106511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 106611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 106711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses 106811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 106911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 107011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 107110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 107210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 107311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 107411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 107510892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 107611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 107711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits 107810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 107911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 108011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 38 # number of overall hits 108110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 108210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 108311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses 108411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses 108511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 108611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses 108711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 108811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 108911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 109011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 109111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 109211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 403 # number of overall misses 109311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles 109411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles 109511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles 109611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles 109711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles 109811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles 109911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles 110011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles 110111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles 110211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles 110311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles 110411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles 110511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 110611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 110710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 110810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 110911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 111011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) 111110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 111210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) 111311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 11149449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 111511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 111611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 11179449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 111811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 11199449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 11209449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 112111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses 112211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses 112311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 112411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses 112511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses 112611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 112711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 112811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses 112911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 113011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses 113111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency 113211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency 113311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency 113411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency 113511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency 113611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency 113711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency 113811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency 113911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency 114011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency 114111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency 114211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency 11439449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11449449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11459449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11469449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11479449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11489449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 114911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 115011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 115111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 115211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 115311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 115411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 115510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 115610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 115711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses 115811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses 115910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 116010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 116111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 116210892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 116311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 116411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 116510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 116611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 116711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles 116811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles 116911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles 117011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles 117111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles 117211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles 117311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles 117411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles 117511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles 117611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles 117711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles 117811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles 11799449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 11809449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 118111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 118211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses 118310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 118410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 118511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses 118610892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 118711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 118811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses 118910892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 119011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 119111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency 119211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency 119311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency 119411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency 119511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency 119611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency 119711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency 119811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency 119911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency 120011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency 120111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency 120211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency 120311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 120411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 120511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 120611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 120711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 120811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 120911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 121011440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 121111440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 121210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 121310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 121411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 121510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 121611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 121711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 121811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) 121911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 122011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 122111440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) 122210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 122311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 122411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 122511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram 122611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram 122710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 122911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram 123010827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 123110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 123211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 123310827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 123411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 123511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 123611680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 123711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) 123811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 123911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 124011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 124111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. 124211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 124311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 124411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 124511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 124611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 124711680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states 124811440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 355 # Transaction distribution 124910628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 42 # Transaction distribution 125010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 42 # Transaction distribution 125111440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 125211440SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 125311440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 125411440SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 125511440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 125610628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 125711570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 125811440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 397 # Request fanout histogram 125910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 126010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 126110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 126211440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 126310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 126410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 126510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 126610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 126711440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 397 # Request fanout histogram 126811680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) 126911680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 127011680SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) 127111680SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 11.4 # Layer utilization (%) 12728889Sgeoffrey.blake@arm.com 12738889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1274