stats.txt revision 11606
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 17458500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 52261 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 61197 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 198636102 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 269760 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 0.09 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 4592 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 5378 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 1711440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 1810892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 25408 # Number of bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 2211440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 2310892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 397 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) 2611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) 2711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) 2811606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) 3311440SCurtis.Dunham@arm.comsystem.physmem.readReqs 397 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511440SCurtis.Dunham@arm.comsystem.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 89 # Per bank write bursts 4610812Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 5010352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5411440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 9 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 5711440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 10 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911606Sandreas.sandberg@arm.comsystem.physmem.totGap 17373000 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 397 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see 9511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 9611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see 9711606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 9811440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 9910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation 19111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation 19211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation 19311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation 19411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation 19511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation 19611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation 19711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation 19911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation 20011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation 20111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation 20211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation 20411606Sandreas.sandberg@arm.comsystem.physmem.totQLat 3455750 # Total ticks spent queuing 20511606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM 20611440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 20711606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst 2089978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst 21011606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511606Sandreas.sandberg@arm.comsystem.physmem.busUtil 11.37 # Data bus utilization in percentage 21611606Sandreas.sandberg@arm.comsystem.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads 2179978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811606Sandreas.sandberg@arm.comsystem.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing 2199978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 330 # Number of row buffer hits during reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads 2239312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411606Sandreas.sandberg@arm.comsystem.physmem.avgGap 43760.71 # Average gap between requests 22511606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined 22611606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 22711606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 22811606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23010628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23111440SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 23210892Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 23311606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) 23411606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 906.309806 # Core power per rank (mW) 23511606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23811606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 23910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 24011606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) 24111606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) 24211606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24410628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24511606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) 24611606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) 24711606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) 24811606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 805.416167 # Core power per rank (mW) 24911606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25211606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states 25310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25411606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 25511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 2836 # Number of BP lookups 25611440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 25711440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 25811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups 25911606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHits 864 # Number of BTB hits 2609481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage 26211440SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 26310812Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 26411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 26511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 26611440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 26711440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 26810628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26911606Sandreas.sandberg@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 27010628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 27110628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 27210628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27310628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27410628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27510628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27610628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27710628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 28110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 28210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 29010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 29110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 29210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29911606Sandreas.sandberg@arm.comsystem.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 30010628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 30110628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30210628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30310628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30410628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30510628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30610628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30710628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3088889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 3098889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 3108889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 3118889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 3128889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 3138889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 3148889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3158889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3168889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3178889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3218889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3228889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3238889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 3248889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 3258889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 3268889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 3278889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 3288889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 32911606Sandreas.sandberg@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 33010628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 33110628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33210628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33310628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33410628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33510628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33610628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33710628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35911606Sandreas.sandberg@arm.comsystem.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 36010628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walks 0 # Table walker walks requested 36110628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36210628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36310628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36410628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36510628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36610628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36710628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3688889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3698889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3708889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3718889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3728889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3738889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3748889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3758889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3768889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3778889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3788889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3798889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3808889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3818889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3828889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3838889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3848889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3858889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3868889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3878889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3888889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3898889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 39011606Sandreas.sandberg@arm.comsystem.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states 39110812Snilay@cs.wisc.edusystem.cpu.checker.numCycles 5391 # number of cpu cycles simulated 3928889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3938889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 39411606Sandreas.sandberg@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 39510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 41010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 42010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 42110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 42210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42411606Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 42510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 42610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 42910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 43010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4338889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 4348889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 4358889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4368889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4378889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4388889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4398889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4408889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4418889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4428889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4438889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 4448889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4458889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 4468889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4478889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4488889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 4498889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 4508889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 4518889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 4528889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 4538889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 45411606Sandreas.sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 45510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 45610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 45910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 46010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 46310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 46410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 46610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 46910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 47010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 47210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 47410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 47510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 47610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 47710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 47810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 47910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 48010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 48110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 48210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 48310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 48411606Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 48510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 48610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4938889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 4948889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4958889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4968889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 4978889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 4988889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4998889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 5008889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 5018889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 5028889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 5038889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 5048889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 5058889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 5068889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 5078889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 5088889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 5098889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 5108889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 5118889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 5128889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 5138889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 51411606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states 51511606Sandreas.sandberg@arm.comsystem.cpu.numCycles 34918 # number of cpu cycles simulated 5168889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5178889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51811606Sandreas.sandberg@arm.comsystem.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss 51911606Sandreas.sandberg@arm.comsystem.cpu.fetch.Insts 12293 # Number of instructions fetch has processed 52011606Sandreas.sandberg@arm.comsystem.cpu.fetch.Branches 2836 # Number of branches that fetch encountered 52111606Sandreas.sandberg@arm.comsystem.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken 52211606Sandreas.sandberg@arm.comsystem.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked 52311440SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 52410812Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 52511606Sandreas.sandberg@arm.comsystem.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps 52610812Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 52711606Sandreas.sandberg@arm.comsystem.cpu.fetch.CacheLines 1960 # Number of cache lines fetched 52811606Sandreas.sandberg@arm.comsystem.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed 52911606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) 53011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) 53111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) 5328889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 53311606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) 53411606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) 53511606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) 53611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) 53711606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) 53811606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) 53911606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) 54011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) 54111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) 5428889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5438889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5448889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 54511606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) 54611606Sandreas.sandberg@arm.comsystem.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle 54711606Sandreas.sandberg@arm.comsystem.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle 54811606Sandreas.sandberg@arm.comsystem.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle 54911606Sandreas.sandberg@arm.comsystem.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked 55011606Sandreas.sandberg@arm.comsystem.cpu.decode.RunCycles 2143 # Number of cycles decode is running 55111606Sandreas.sandberg@arm.comsystem.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking 55211440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 55311440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 55411440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 55511606Sandreas.sandberg@arm.comsystem.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode 55611440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 55711440SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 55811606Sandreas.sandberg@arm.comsystem.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle 55911606Sandreas.sandberg@arm.comsystem.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking 56011606Sandreas.sandberg@arm.comsystem.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst 56111606Sandreas.sandberg@arm.comsystem.cpu.rename.RunCycles 2036 # Number of cycles rename is running 56211606Sandreas.sandberg@arm.comsystem.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking 56311606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename 56411440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 56511606Sandreas.sandberg@arm.comsystem.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full 56611606Sandreas.sandberg@arm.comsystem.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full 56711606Sandreas.sandberg@arm.comsystem.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full 56811606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed 56911606Sandreas.sandberg@arm.comsystem.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made 57011606Sandreas.sandberg@arm.comsystem.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups 57111440SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 57210352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 57311606Sandreas.sandberg@arm.comsystem.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing 57411440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 40 # count of serializing insts renamed 57511440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed 57611440SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 441 # count of insts added to the skid buffer 57711440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. 57811440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. 57911103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 58011440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. 58111606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) 58211440SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ 58311606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsIssued 8100 # Number of instructions issued 58411606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued 58511606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling 58611606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph 58711440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 58811606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle 58911606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle 59011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle 5918889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 59211606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle 59311606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle 59411606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle 59511606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle 59611606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle 59711606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle 59811606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle 59911440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle 60011440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle 6018889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 6028889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 6038889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 60411606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle 6058889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 60611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available 60711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available 60811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available 60911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available 61011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available 61111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available 61211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available 61311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available 61411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available 61511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available 61611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available 61711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available 61811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available 61911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available 62011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available 62111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available 62211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available 62311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available 62411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available 62511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available 62611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available 62711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available 62811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available 62911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available 63011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available 63111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available 63211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available 63311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available 63411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available 63511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available 63611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available 6378889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6388889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6398889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 64011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued 64111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued 64211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued 64311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued 64411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued 64511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued 64611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued 64711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued 64811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued 64911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued 65011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued 65111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued 65211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued 65311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued 65411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued 65511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued 65611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued 65711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued 65811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued 65911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued 66011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued 66111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued 66211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued 66311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued 66411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued 66511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued 66611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued 66711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued 66811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued 66911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued 67011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued 6718889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 6728889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 67311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::total 8100 # Type of FU issued 67411606Sandreas.sandberg@arm.comsystem.cpu.iq.rate 0.231972 # Inst issue rate 67511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_cnt 146 # FU busy when requested 67611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) 67711606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads 67811606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes 67911606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses 68011440SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads 68111440SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 68210726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 68311606Sandreas.sandberg@arm.comsystem.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses 68410352Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 68511103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 6868889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 68711440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed 6889312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 68910726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 69011440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed 6918889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6928889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 69311440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled 69410812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 6958889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 69611440SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing 69711606Sandreas.sandberg@arm.comsystem.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking 69811440SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 69911606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ 70011606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch 70111440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions 70211440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions 70311440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions 70411440SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 70510892Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 70610726Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 70711440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly 70811440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly 70911440SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute 71011606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions 71111606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed 71211606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute 7138889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 71410812Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 9 # number of nop insts executed 71511606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_refs 2920 # number of memory reference insts executed 71611440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 1492 # Number of branches executed 71711606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_stores 1147 # Number of stores executed 71811606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_rate 0.223581 # Inst execution rate 71911606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit 72011606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_count 7431 # cumulative count of insts written-back 72111606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_producers 3502 # num instructions producing a value 72211606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_consumers 6830 # num instructions consuming a value 72311606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_rate 0.212813 # insts written-back per cycle 72411606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back 72511606Sandreas.sandberg@arm.comsystem.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit 7269459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 72711440SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted 72811606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle 72911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle 73011606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle 7318889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 73211606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle 73311606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle 73411606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle 73511606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle 73611606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle 73711606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle 73811606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle 73911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle 74011440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle 7418889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7428889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7438889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 74411606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle 74510812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 4592 # Number of instructions committed 74610812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 7478889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 74810352Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 74910352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 7508889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 75110812Snilay@cs.wisc.edusystem.cpu.commit.branches 1008 # Number of branches committed 7528889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 75310352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 7548889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 75510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 75610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 75710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 75810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 75910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 76010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 76110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 76210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 76310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 76410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 76510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 76610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 76710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 76810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 76910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 77010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 77110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 77210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 77310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 77410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 77510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 77610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 77710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 77810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 77910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 78010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 78110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 78210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 78310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 78410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 78510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 78610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 78710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 78810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 78910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5378 # Class of committed instruction 79011440SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached 79111606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_reads 22352 # The number of ROB reads 79211606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_writes 21294 # The number of ROB writes 79311440SCurtis.Dunham@arm.comsystem.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself 79411606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling 79510812Snilay@cs.wisc.edusystem.cpu.committedInsts 4592 # Number of Instructions Simulated 79610812Snilay@cs.wisc.edusystem.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 79711606Sandreas.sandberg@arm.comsystem.cpu.cpi 7.604094 # CPI: Cycles Per Instruction 79811606Sandreas.sandberg@arm.comsystem.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads 79911606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.131508 # IPC: Instructions Per Cycle 80011606Sandreas.sandberg@arm.comsystem.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads 80111606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_reads 7649 # number of integer regfile reads 80211606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_writes 4266 # number of integer regfile writes 80310726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 32 # number of floating regfile reads 80411606Sandreas.sandberg@arm.comsystem.cpu.cc_regfile_reads 27780 # number of cc regfile reads 80511606Sandreas.sandberg@arm.comsystem.cpu.cc_regfile_writes 3273 # number of cc regfile writes 80611606Sandreas.sandberg@arm.comsystem.cpu.misc_regfile_reads 2976 # number of misc regfile reads 8079459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 80811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 80910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 81011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use 81111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. 81211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 81311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. 81410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 81511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor 81611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy 81711606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy 81811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 81911440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 82011440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 82111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 82211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses 82311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 5341 # Number of data accesses 82411606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 82511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits 82611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits 82711440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 82811440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 82911440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 83011440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 83110628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 83210628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 83311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits 83411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits 83511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits 83611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 2075 # number of overall hits 83711440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 83811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses 83911440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 84011440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 84110628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 84210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 84311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 84411440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 84511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 84611440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 499 # number of overall misses 84711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles 84811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles 84911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles 85011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles 85111606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles 85211606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles 85311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles 85411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles 85511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles 85611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles 85711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) 85811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) 85910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 86010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 86111440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 86211440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 86310628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 86410628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 86511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses 86611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses 86711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses 86811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses 86911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses 87011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses 87111440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 87211440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 87311440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 87411440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 87511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses 87611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses 87711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses 87811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses 87911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency 88011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency 88111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency 88211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency 88311606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency 88411606Sandreas.sandberg@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency 88511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency 88611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency 88711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency 88811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency 88911606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked 89010628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89111103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 89210628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 89311606Sandreas.sandberg@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked 89410628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 89611440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 89711440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 89811440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 89910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 90010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 90111440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 90211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 90311440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 90411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 90510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 90610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 90710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 90810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 90910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 91010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 91110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 91210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 91311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles 91411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles 91511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles 91611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles 91711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles 91811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles 91911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles 92011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles 92111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses 92211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses 92310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 92410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 92511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses 92611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses 92711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses 92811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses 92911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency 93011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency 93111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency 93211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency 93311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency 93411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency 93511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency 93611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency 93711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 93811440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 2 # number of replacements 93911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use 94011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. 94111440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 94211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. 9439838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor 94511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy 94611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy 94710812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 94811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id 94911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 95010812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 95111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses 95211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 4214 # Number of data accesses 95311606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 95411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits 95511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits 95611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits 95711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits 95811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits 95911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 1576 # number of overall hits 96011440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses 96111440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses 96211440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses 96311440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses 96411440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses 96511440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 384 # number of overall misses 96611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles 96711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles 96811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles 96911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles 97011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles 97111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles 97211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) 97311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) 97411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses 97511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses 97611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses 97711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses 97811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses 97911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses 98011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses 98111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses 98211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses 98311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses 98411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency 98511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency 98611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency 98711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency 98811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency 98911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency 99011606Sandreas.sandberg@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked 9918889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 99210352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 9938889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 99411606Sandreas.sandberg@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked 9958983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 99611440SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 2 # number of writebacks 99711440SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 2 # number of writebacks 99811440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 99911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 100011440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 100111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 100211440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 100311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits 100411440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 100511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 100611440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 100711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 100811440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 100911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 101011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles 101111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles 101211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles 101311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles 101411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles 101511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles 101611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses 101711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses 101811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses 101911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses 102011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses 102111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses 102211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency 102311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency 102411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency 102511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency 102611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency 102711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency 102811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 10299838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 103011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use 103110352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 103211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 103311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. 10349838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 103511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor 103611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor 103711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy 103811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy 103911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy 104011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 104111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id 104211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id 104311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 104411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 104511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses 104611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 104711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 104811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 104910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 105010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 105111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 105211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 105310892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 105411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 105511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits 105610892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 105711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 105811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 38 # number of overall hits 105910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 106010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 106111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses 106211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses 106311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 106411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses 106511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 106611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 106711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 106811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 106911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 107011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 403 # number of overall misses 107111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles 107211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles 107311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles 107411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles 107511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles 107611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles 107711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles 107811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles 107911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles 108011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles 108111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles 108211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles 108311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 108411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 108510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 108610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 108711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 108811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) 108910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 109010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) 109111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 10929449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 109311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 109411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 10959449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 109611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 10979449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 10989449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 109911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses 110011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses 110111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 110211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses 110311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses 110411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 110511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 110611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses 110711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 110811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses 110911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency 111011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency 111111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency 111211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency 111311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency 111411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency 111511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency 111611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency 111711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency 111811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency 111911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency 112011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency 11219449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11229449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11239449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11249449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11259449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11269449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 112811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 112911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 113011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 113111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 113211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 113310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 113410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 113511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses 113611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses 113710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 113810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 113911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 114010892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 114111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 114211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 114310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 114411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 114511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles 114611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles 114711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles 114811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles 114911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles 115011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles 115111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles 115211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles 115311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles 115411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles 115511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles 115611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles 11579449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 11589449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 115911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 116011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses 116110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 116210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 116311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses 116410892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 116511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 116611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses 116710892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 116811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 116911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency 117011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency 117111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency 117211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency 117311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency 117411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency 117511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency 117611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency 117711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency 117811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency 117911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency 118011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency 118111440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 118211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 118311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 118411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 118511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 118611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 118711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 118811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 118911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 119010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 119110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 119211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 119310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 119411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 119511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 119611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) 119711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 119811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 119911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) 120010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 120111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 120211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 120311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram 120411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram 120510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 120711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram 120810827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 120910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 121011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 121110827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 121211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 121311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 121410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 121511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) 121611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) 121711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 121810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 121911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. 122011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 122111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 122211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 122311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 122411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 122511606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states 122611440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 355 # Transaction distribution 122710628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 42 # Transaction distribution 122810628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 42 # Transaction distribution 122911440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 123011440SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 123111440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 123211440SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 123311440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 123410628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 123511570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 123611440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 397 # Request fanout histogram 123710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 123810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 123910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 124011440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 124110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 124210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 124310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 124410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 124511440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 397 # Request fanout histogram 124611440SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) 124710892Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 124811606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) 124911606Sandreas.sandberg@arm.comsystem.membus.respLayer1.utilization 12.0 # Layer utilization (%) 12508889Sgeoffrey.blake@arm.com 12518889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1252