stats.txt revision 11440
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 411440SCurtis.Dunham@arm.comsim_ticks 17232500 # Number of ticks simulated 511440SCurtis.Dunham@arm.comfinal_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711384Ssteve.reinhardt@amd.comhost_inst_rate 9367 # Simulator instruction rate (inst/s) 811384Ssteve.reinhardt@amd.comhost_op_rate 10970 # Simulator op (including micro ops) rate (op/s) 911384Ssteve.reinhardt@amd.comhost_tick_rate 35022410 # Simulator tick rate (ticks/s) 1011384Ssteve.reinhardt@amd.comhost_mem_usage 245324 # Number of bytes of host memory used 1111384Ssteve.reinhardt@amd.comhost_seconds 0.49 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 4592 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 5378 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 1811440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 25408 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 2210892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 2311440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 397 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) 2511440SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) 2611440SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) 2711440SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) 2811440SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) 2911440SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) 3011440SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) 3111440SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) 3211440SCurtis.Dunham@arm.comsystem.physmem.readReqs 397 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3411440SCurtis.Dunham@arm.comsystem.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3611440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3911440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4411440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 89 # Per bank write bursts 4510812Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 4710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5311440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 9 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 5611440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 10 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7811440SCurtis.Dunham@arm.comsystem.physmem.totGap 17147000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8511440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 397 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9311440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 9411440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 9511440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 9611440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 9711440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 9810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 9910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 19011440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation 19111440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation 19211440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation 19311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation 19411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation 19511440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation 19611440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation 19711440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation 19811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 19911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation 20011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation 20111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 20211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 20311440SCurtis.Dunham@arm.comsystem.physmem.totQLat 3287250 # Total ticks spent queuing 20411440SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM 20511440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 20611440SCurtis.Dunham@arm.comsystem.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811440SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst 20911440SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111440SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411440SCurtis.Dunham@arm.comsystem.physmem.busUtil 11.52 # Data bus utilization in percentage 21511440SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710892Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911440SCurtis.Dunham@arm.comsystem.physmem.readRowHits 331 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111440SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311440SCurtis.Dunham@arm.comsystem.physmem.avgGap 43191.44 # Average gap between requests 22411440SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 22511103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 22611103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 22711440SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23011440SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 23110892Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 23211440SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) 23311440SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 910.249171 # Core power per rank (mW) 23411440SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711440SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23910892Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 24010892Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 24111440SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24411103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) 24511103Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 24611440SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) 24711440SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 808.014211 # Core power per rank (mW) 24811440SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311440SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 2837 # Number of BP lookups 25411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted 25511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect 25611440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups 25711440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 865 # Number of BTB hits 2589481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25911440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage 26011440SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. 26110812Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 26211440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. 26311440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 14 # Number of indirect target hits. 26411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 251 # Number of indirect misses. 26511440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. 26610628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26710628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26810628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26910628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27010628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27110628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27210628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27310628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27410628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 28710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 28810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 28910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29610628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 29710628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29810628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29910628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30010628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30110628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30210628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30310628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3048889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 3058889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 3068889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 3078889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 3088889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 3098889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 3108889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3118889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3128889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3138889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3148889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3158889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3168889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3178889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 3218889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 3228889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 3238889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 3248889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 32510628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 32610628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32710628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32810628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32910628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33010628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33110628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33210628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35410628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walks 0 # Table walker walks requested 35510628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36010628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36110628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3628889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3638889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3648889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3658889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3668889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3678889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3688889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3698889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3708889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3718889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3728889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3738889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3748889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3758889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3768889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3778889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3788889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3798889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3808889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3818889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3828889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3838889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 38410812Snilay@cs.wisc.edusystem.cpu.checker.numCycles 5391 # number of cpu cycles simulated 3858889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3868889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 38710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 41710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 42010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 42110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 42310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4248889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 4258889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 4268889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4278889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4288889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4298889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4308889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4318889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4328889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4338889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4348889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 4358889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4368889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 4378889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4388889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4398889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 4408889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 4418889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 4428889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 4438889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 4448889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 44510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 45210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 45310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 45510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 45810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 45910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 46010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 46310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 46410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 46510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 46610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 46710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 46810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 46910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 47010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 47110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 47210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 47310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 47410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 47510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4828889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 4838889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4848889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4858889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 4868889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 4878889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4888889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4898889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4908889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4918889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4928889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4938889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4948889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4958889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4968889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4978889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4988889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4998889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 5008889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 5018889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 5028889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 50311440SCurtis.Dunham@arm.comsystem.cpu.numCycles 34466 # number of cpu cycles simulated 5048889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5058889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 50611440SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss 50711440SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 12295 # Number of instructions fetch has processed 50811440SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 2837 # Number of branches that fetch encountered 50911440SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken 51011440SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked 51111440SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing 51210812Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 51311440SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps 51410812Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 51511440SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 51611440SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 51711440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) 51811440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) 51911440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) 5208889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 52111440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) 52211440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) 52311440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) 52411440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) 52511440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) 52611440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) 52711440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) 52811440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) 52911440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) 5308889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5318889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5328889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 53311440SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) 53411440SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle 53511440SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle 53611440SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle 53711440SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked 53811440SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 2142 # Number of cycles decode is running 53911440SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 54011440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing 54111440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch 54211440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 54311440SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode 54411440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode 54511440SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing 54611440SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle 54711440SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking 54811440SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst 54911440SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 2037 # Number of cycles rename is running 55011440SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 55111440SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename 55211440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 55311440SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full 55410892Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full 55511440SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full 55611440SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed 55711440SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 52722 # Number of register rename lookups that rename has made 55811440SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups 55911440SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups 56010352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 56111440SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing 56211440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 40 # count of serializing insts renamed 56311440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed 56411440SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 441 # count of insts added to the skid buffer 56511440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. 56611440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. 56711103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 56811440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. 56911440SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) 57011440SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ 57111440SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 8103 # Number of instructions issued 57211440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued 57311440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling 57411440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 12413 # Number of squashed operands that are examined and possibly removed from graph 57511440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 57611440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle 57711440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle 57811440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle 5798889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 58011440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle 58111440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle 58211440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle 58311440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle 58411440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle 58511440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle 58611440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle 58711440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle 58811440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle 5898889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5908889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5918889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 59211440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle 5938889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 59411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available 59511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available 59611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available 59711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available 59811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available 59911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available 60011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available 60111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available 60211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available 60311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available 60411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available 60511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available 60611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available 60711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available 60811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available 60911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available 61011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available 61111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available 61211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available 61311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available 61411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available 61511440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available 61611440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available 61711440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available 61811440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available 61911440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available 62011440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available 62111440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available 62211440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available 62311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available 62411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available 6258889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6268889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6278889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 62811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued 62911440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued 63011440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued 63111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued 63211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued 63311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued 63411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued 63511440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued 63611440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued 63711440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued 63811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued 63911440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued 64011440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued 64111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued 64211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued 64311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued 64411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued 64511440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued 64611440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued 64711440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued 64811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued 64911440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued 65011440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued 65111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued 65211440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued 65311440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued 65411440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued 65511440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued 65611440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued 65711440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued 65811440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued 6598889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 6608889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 66111440SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 8103 # Type of FU issued 66211440SCurtis.Dunham@arm.comsystem.cpu.iq.rate 0.235101 # Inst issue rate 66311440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 145 # FU busy when requested 66411440SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) 66511440SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads 66611440SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes 66711440SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses 66811440SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads 66911440SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes 67010726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 67111440SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses 67210352Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 67311103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 6748889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 67511440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed 6769312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 67710726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 67811440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed 6798889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6808889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 68111440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled 68210812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 6838889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 68411440SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing 68511440SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking 68611440SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 68711440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ 68811440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch 68911440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions 69011440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions 69111440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions 69211440SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 69310892Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 69410726Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 69511440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly 69611440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly 69711440SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute 69811440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions 69911440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed 70011440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute 7018889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 70210812Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 9 # number of nop insts executed 70311440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 2923 # number of memory reference insts executed 70411440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 1492 # Number of branches executed 70511440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 1151 # Number of stores executed 70611440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 0.226716 # Inst execution rate 70711440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit 70811440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 7439 # cumulative count of insts written-back 70911440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 3504 # num instructions producing a value 71011440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 6831 # num instructions consuming a value 71111440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 0.215836 # insts written-back per cycle 71211440SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back 71311440SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit 7149459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 71511440SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted 71611440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle 71711440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle 71811440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle 7198889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 72011440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle 72111440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle 72211440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle 72311440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle 72411440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle 72511440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle 72611440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle 72711440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle 72811440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle 7298889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7308889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7318889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 73211440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle 73310812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 4592 # Number of instructions committed 73410812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 7358889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 73610352Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 73710352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 7388889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 73910812Snilay@cs.wisc.edusystem.cpu.commit.branches 1008 # Number of branches committed 7408889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 74110352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 7428889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 74310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 74410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 74510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 74610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 74710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 74810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 74910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 75010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 75110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 75210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 75310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 75410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 75510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 75610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 75710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 75810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 75910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 76010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 76110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 76210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 76310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 76410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 76510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 76610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 76710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 76810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 76910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 77010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 77110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 77210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 77310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 77410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 77510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 77610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 77710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5378 # Class of committed instruction 77811440SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached 77911440SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 22311 # The number of ROB reads 78011440SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 21303 # The number of ROB writes 78111440SCurtis.Dunham@arm.comsystem.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself 78211440SCurtis.Dunham@arm.comsystem.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling 78310812Snilay@cs.wisc.edusystem.cpu.committedInsts 4592 # Number of Instructions Simulated 78410812Snilay@cs.wisc.edusystem.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 78511440SCurtis.Dunham@arm.comsystem.cpu.cpi 7.505662 # CPI: Cycles Per Instruction 78611440SCurtis.Dunham@arm.comsystem.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads 78711440SCurtis.Dunham@arm.comsystem.cpu.ipc 0.133233 # IPC: Instructions Per Cycle 78811440SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads 78911440SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 7659 # number of integer regfile reads 79011440SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 4270 # number of integer regfile writes 79110726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 32 # number of floating regfile reads 79211440SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 27801 # number of cc regfile reads 79311440SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 3276 # number of cc regfile writes 79411440SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 3018 # number of misc regfile reads 7959459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 79610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 79711440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use 79811440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. 79911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 80011440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. 80110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 80211440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor 80311440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy 80411440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy 80511103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 80611440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 80711440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 80811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 80911440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses 81011440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 5339 # Number of data accesses 81111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits 81211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits 81311440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 81411440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 81511440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 81611440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 81710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 81810628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 81911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits 82011440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits 82111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits 82211440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 2074 # number of overall hits 82311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses 82411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses 82511440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 82611440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 82710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 82810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 82911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 83011440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 83111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 83211440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 499 # number of overall misses 83311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles 83411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles 83511440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles 83611440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles 83710892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles 83810892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles 83911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles 84011440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles 84111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles 84211440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles 84311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) 84411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) 84510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 84610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 84711440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 84811440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 84910628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 85010628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 85111440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses 85211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses 85311440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses 85411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses 85511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses 85611440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses 85711440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 85811440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 85911440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 86011440SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 86111440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses 86211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses 86311440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses 86411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses 86511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency 86611440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency 86711440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency 86811440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency 86910892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency 87010892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency 87111440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency 87211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency 87311440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency 87411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency 87511103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked 87610628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87711103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 87810628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 87911103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked 88010628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88110628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 88210628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 88311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 88411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 88511440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 88611440SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 88710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 88810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 88911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits 89011440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits 89111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits 89211440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits 89310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 89410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 89510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 89610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 89710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 89810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 89910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 90010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 90111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles 90211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles 90311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles 90411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles 90511440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles 90611440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles 90711440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles 90811440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles 90911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses 91011440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses 91110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 91210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 91311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses 91411440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses 91511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses 91611440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses 91711440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency 91811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency 91911138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency 92011138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency 92111440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 92211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 92311440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency 92411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency 92510628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 92611440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 2 # number of replacements 92711440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use 92811440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. 92911440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 93011440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. 9319838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93211440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor 93311440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy 93411440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy 93510812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 93611440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 93711440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id 93810812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 93911440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses 94011440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 4216 # Number of data accesses 94111440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 94211440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 94311440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 94411440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 94511440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 94611440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 1577 # number of overall hits 94711440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses 94811440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses 94911440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses 95011440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses 95111440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses 95211440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 384 # number of overall misses 95311440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles 95411440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles 95511440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles 95611440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles 95711440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles 95811440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles 95911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) 96011440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) 96111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses 96211440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses 96311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses 96411440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses 96511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses 96611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses 96711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses 96811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses 96911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses 97011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses 97111440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency 97211440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency 97311440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency 97411440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency 97511440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency 97611440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency 97711440SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked 9788889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97910352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 9808889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 98111440SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked 9828983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9838889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 9848889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 98511440SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 2 # number of writebacks 98611440SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 2 # number of writebacks 98711440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 98811440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 98911440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 99011440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 99111440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 99211440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits 99311440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 99411440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 99511440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 99611440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 99711440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 99811440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 99911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles 100011440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles 100111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles 100211440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles 100311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles 100411440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles 100511440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses 100611440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses 100711440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses 100811440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses 100911440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses 101011440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses 101111440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency 101211440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency 101311440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 101411440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 101511440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency 101611440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency 10178889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 10189838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 101911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use 102010352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 102111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 102211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 10239838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 102411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor 102511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor 102611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy 102711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy 102811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy 102911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 103011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 103111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 103211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 103311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses 103411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses 103511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 103611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 103710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 103810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 103911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits 104011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits 104110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 104211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 104311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits 104410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 104511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 104611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 38 # number of overall hits 104710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 104810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 104911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses 105011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses 105111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses 105211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses 105311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 105411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 105511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses 105611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 105711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 105811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 403 # number of overall misses 105911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles 106011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles 106111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles 106211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles 106311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles 106411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles 106511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles 106611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles 106711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles 106811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles 106911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles 107011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles 107111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 107211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 107310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 107410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 107511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) 107611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) 107710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 107810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) 107911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 10809449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 108111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 108211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 10839449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 108411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 10859449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 10869449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 108711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses 108811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses 108911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses 109011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses 109111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses 109211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 109311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses 109411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses 109511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 109611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses 109711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency 109811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency 109911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency 110011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency 110111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency 110211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency 110311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency 110411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency 110511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency 110611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency 110711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency 110811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency 11099449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11109449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11119449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11129449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11139449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11149449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11159449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 11169449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 111711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 111811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 111911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 112011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 112111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 112211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 112310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 112410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 112511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses 112611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses 112710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 112810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 112911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 113010892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 113111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 113211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 113310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 113411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 113511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles 113611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles 113711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles 113811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles 113911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles 114011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles 114111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles 114211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles 114311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles 114411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles 114511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles 114611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles 11479449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 11489449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 114911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses 115011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses 115110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 115210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 115311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses 115410892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 115511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 115611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses 115710892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 115811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 115911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency 116011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency 116111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency 116211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency 116311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency 116411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency 116511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 116611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 116711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 116811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency 116911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency 117011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency 11719449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 117211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. 117311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 117411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 117511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 117611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 117711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 117811440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution 117911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 118010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 118110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 118211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution 118310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 118411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 118511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 118611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) 118711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 118811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 118911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) 119010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 119111440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 119211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram 119311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram 119410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 119511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram 119611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram 119710827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 119810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 119911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 120010827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 120111440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 120211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 120310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 120411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) 120510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 120611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) 120710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 120811440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 355 # Transaction distribution 120910628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 42 # Transaction distribution 121010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 42 # Transaction distribution 121111440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 355 # Transaction distribution 121211440SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 121311440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 121411440SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 121511440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 121610628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 121711440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 397 # Request fanout histogram 121810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 121910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 122010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122111440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 122210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 122310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 122410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 122510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 122611440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 397 # Request fanout histogram 122711440SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) 122810892Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 122911440SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) 123010892Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 12.2 # Layer utilization (%) 12318889Sgeoffrey.blake@arm.com 12328889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1233