stats.txt revision 11103
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 411103Snilay@cs.wisc.edusim_ticks 17163000 # Number of ticks simulated 511103Snilay@cs.wisc.edufinal_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711103Snilay@cs.wisc.eduhost_inst_rate 25428 # Simulator instruction rate (inst/s) 811103Snilay@cs.wisc.eduhost_op_rate 29777 # Simulator op (including micro ops) rate (op/s) 911103Snilay@cs.wisc.eduhost_tick_rate 95019968 # Simulator tick rate (ticks/s) 1011103Snilay@cs.wisc.eduhost_mem_usage 305352 # Number of bytes of host memory used 1111103Snilay@cs.wisc.eduhost_seconds 0.18 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 4592 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 5378 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory 1810812Snilay@cs.wisc.edusystem.physmem.bytes_read::total 25344 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 2010892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 2210892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory 2310812Snilay@cs.wisc.edusystem.physmem.num_reads::total 396 # Number of read requests responded to by this memory 2411103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s) 2511103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s) 2611103Snilay@cs.wisc.edusystem.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s) 2711103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s) 2811103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s) 2911103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s) 3011103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s) 3111103Snilay@cs.wisc.edusystem.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s) 3210812Snilay@cs.wisc.edusystem.physmem.readReqs 396 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410812Snilay@cs.wisc.edusystem.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610812Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910812Snilay@cs.wisc.edusystem.physmem.bytesReadSys 25344 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 90 # Per bank write bursts 4510812Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 4710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5310242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::9 8 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7811103Snilay@cs.wisc.edusystem.physmem.totGap 17090000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510812Snilay@cs.wisc.edusystem.physmem.readPktSize::6 396 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see 9410892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 9511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see 9611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 9711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 9810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 9910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 19011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation 19111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation 19211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation 19311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation 19411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation 19511103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation 19611103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation 19711103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 19811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 19911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation 20011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation 20111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 20211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 20311103Snilay@cs.wisc.edusystem.physmem.totQLat 3055250 # Total ticks spent queuing 20411103Snilay@cs.wisc.edusystem.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM 20510812Snilay@cs.wisc.edusystem.physmem.totBusLat 1980000 # Total ticks spent in databus transfers 20611103Snilay@cs.wisc.edusystem.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811103Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst 20911103Snilay@cs.wisc.edusystem.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111103Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411103Snilay@cs.wisc.edusystem.physmem.busUtil 11.54 # Data bus utilization in percentage 21511103Snilay@cs.wisc.edusystem.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710892Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911103Snilay@cs.wisc.edusystem.physmem.readRowHits 330 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111103Snilay@cs.wisc.edusystem.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311103Snilay@cs.wisc.edusystem.physmem.avgGap 43156.57 # Average gap between requests 22411103Snilay@cs.wisc.edusystem.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined 22511103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 22611103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 22711103Snilay@cs.wisc.edusystem.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23011103Snilay@cs.wisc.edusystem.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) 23110892Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 23211103Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ) 23311103Snilay@cs.wisc.edusystem.physmem_0.averagePower 911.198611 # Core power per rank (mW) 23411103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23910892Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 24010892Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 24110892Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24411103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) 24511103Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 24611103Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) 24711103Snilay@cs.wisc.edusystem.physmem_1.averagePower 807.028896 # Core power per rank (mW) 24811103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311103Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2533 # Number of BP lookups 25411103Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted 25511103Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect 25611103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups 25711103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 812 # Number of BTB hits 2589481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25911103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage 26011103Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. 26110812Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 26210628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26310628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26410628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26510628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 26610628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 26710628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 26810628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 26910628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27010628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 27610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 27710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 27810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 27910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 28310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 28410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 28510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 28610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 28710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 28810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 28910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29210628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 29310628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29410628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29510628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 29610628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 29710628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 29810628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 29910628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3008889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 3018889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 3028889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 3038889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 3048889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 3058889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 3068889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3078889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3088889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3098889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3108889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3118889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3128889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3138889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3148889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3158889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 3168889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 3178889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 32110628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 32210628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32310628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32410628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32510628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 32610628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 32710628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 32810628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 33610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 34710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 34810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 34910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35010628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walks 0 # Table walker walks requested 35110628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35210628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35310628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35410628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35510628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3588889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3598889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3608889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3618889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3628889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3638889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3648889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3658889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3668889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3678889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3688889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3698889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3708889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3718889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3728889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3738889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3748889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3758889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3768889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3778889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3788889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3798889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 38010812Snilay@cs.wisc.edusystem.cpu.checker.numCycles 5391 # number of cpu cycles simulated 3818889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3828889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 38310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 41310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4208889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 4218889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 4228889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4238889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4248889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4258889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4268889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4278889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4288889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4298889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4308889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 4318889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4328889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 4338889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4348889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4358889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 4368889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 4378889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 4388889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 4398889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 4408889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 44110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 44810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 45110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 45410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 45510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 45610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 46010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 46110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 46210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 46310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 46410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 46510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 46610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 46710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 46810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 46910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 47010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 47110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4788889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 4798889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4808889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4818889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 4828889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 4838889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4848889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4858889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4868889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4878889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4888889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4898889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4908889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4918889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4928889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4938889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4948889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4958889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4968889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 4978889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 4988889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 49911103Snilay@cs.wisc.edusystem.cpu.numCycles 34327 # number of cpu cycles simulated 5008889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5018889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 50211103Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss 50311103Snilay@cs.wisc.edusystem.cpu.fetch.Insts 11725 # Number of instructions fetch has processed 50411103Snilay@cs.wisc.edusystem.cpu.fetch.Branches 2533 # Number of branches that fetch encountered 50511103Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken 50611103Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked 50711103Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing 50810812Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50910812Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps 51010812Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 51111103Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 1968 # Number of cache lines fetched 51211103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed 51311103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total) 51411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total) 51511103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total) 5168889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 51711103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total) 51811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total) 51911103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total) 52011103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total) 52111103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total) 52211103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total) 52311103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total) 52411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total) 52511103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total) 5268889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5278889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5288889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 52911103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total) 53011103Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle 53111103Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle 53211103Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle 53311103Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked 53411103Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 2063 # Number of cycles decode is running 53511103Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking 53611103Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing 53711103Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch 53810892Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 53911103Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode 54011103Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode 54111103Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing 54211103Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle 54311103Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking 54411103Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst 54511103Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 1964 # Number of cycles rename is running 54611103Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking 54711103Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename 54810892Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full 54910892Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full 55011103Snilay@cs.wisc.edusystem.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full 55111103Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed 55211103Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made 55311103Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups 55411103Snilay@cs.wisc.edusystem.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups 55510352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 55611103Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing 55711103Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 42 # count of serializing insts renamed 55810892Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 55911103Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 428 # count of insts added to the skid buffer 56011103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit. 56111103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit. 56211103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 56311103Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. 56411103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec) 56510352Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 56611103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 7972 # Number of instructions issued 56711103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued 56811103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling 56911103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph 57010352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 57111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle 57211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle 57311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle 5748889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 57511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle 57611103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle 57711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle 57811103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle 57911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle 58011103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle 58111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle 58211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle 58311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle 5848889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5858889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5868889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 58711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle 5888889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 58911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available 59011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available 59111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available 59211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available 59311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available 59411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available 59511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available 59611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available 59711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available 59811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available 59911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available 60011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available 60111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available 60211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available 60311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available 60411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available 60511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available 60611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available 60711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available 60811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available 60911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available 61011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available 61111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available 61211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available 61311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available 61411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available 61511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available 61611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available 61711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available 61811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available 61911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available 6208889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6218889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6228889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 62311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued 62411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued 62511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued 62611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued 62711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued 62811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued 62911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued 63011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued 63111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued 63211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued 63311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued 63411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued 63511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued 63611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued 63711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued 63811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued 63911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued 64011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued 64111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued 64211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued 64311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued 64411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued 64511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued 64611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued 64711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued 64811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued 64911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued 65011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued 65111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued 65211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued 65311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued 6548889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 6558889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 65611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 7972 # Type of FU issued 65711103Snilay@cs.wisc.edusystem.cpu.iq.rate 0.232237 # Inst issue rate 65811103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 152 # FU busy when requested 65911103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst) 66011103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads 66111103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes 66211103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses 66311103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads 66411103Snilay@cs.wisc.edusystem.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes 66510726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 66611103Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses 66710352Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 66811103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores 6698889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 67011103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed 6719312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 67210726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 67311103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed 6748889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6758889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 67611103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled 67710812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 6788889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 67911103Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing 68011103Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking 68110892Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking 68211103Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ 68311103Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch 68411103Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions 68511103Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions 68610352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 68710812Snilay@cs.wisc.edusystem.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 68810892Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 68910726Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 69011103Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly 69111103Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly 69211103Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute 69311103Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions 69411103Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed 69511103Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute 6968889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 69710812Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 9 # number of nop insts executed 69811103Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 2930 # number of memory reference insts executed 69911103Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 1433 # Number of branches executed 70011103Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 1194 # Number of stores executed 70111103Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.224226 # Inst execution rate 70211103Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit 70311103Snilay@cs.wisc.edusystem.cpu.iew.wb_count 7341 # cumulative count of insts written-back 70411103Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 3456 # num instructions producing a value 70511103Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 6757 # num instructions consuming a value 7068889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 70711103Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.213855 # insts written-back per cycle 70811103Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back 7098889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 71011103Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit 7119459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 71211103Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted 71311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle 71411103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle 71511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle 7168889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 71711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle 71811103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle 71911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle 72011103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle 72111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle 72211103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle 72311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle 72411103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle 72511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle 7268889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7278889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7288889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 72911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle 73010812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 4592 # Number of instructions committed 73110812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 7328889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 73310352Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 73410352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 7358889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 73610812Snilay@cs.wisc.edusystem.cpu.commit.branches 1008 # Number of branches committed 7378889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 73810352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 7398889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 74010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 74110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 74210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 74310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 74410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 74510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 74610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 74710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 74810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 74910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 75010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 75110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 75210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 75310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 75410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 75510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 75610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 75710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 75810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 75910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 76010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 76110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 76210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 76310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 76410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 76510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 76610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 76710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 76810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 76910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 77010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 77110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 77210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 77310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 77410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5378 # Class of committed instruction 77511103Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached 77611103Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 21783 # The number of ROB reads 77711103Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 20313 # The number of ROB writes 77811103Snilay@cs.wisc.edusystem.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself 77911103Snilay@cs.wisc.edusystem.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling 78010812Snilay@cs.wisc.edusystem.cpu.committedInsts 4592 # Number of Instructions Simulated 78110812Snilay@cs.wisc.edusystem.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 78211103Snilay@cs.wisc.edusystem.cpu.cpi 7.475392 # CPI: Cycles Per Instruction 78311103Snilay@cs.wisc.edusystem.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads 78411103Snilay@cs.wisc.edusystem.cpu.ipc 0.133772 # IPC: Instructions Per Cycle 78511103Snilay@cs.wisc.edusystem.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads 78611103Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 7631 # number of integer regfile reads 78711103Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 4176 # number of integer regfile writes 78810726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 32 # number of floating regfile reads 78911103Snilay@cs.wisc.edusystem.cpu.cc_regfile_reads 27375 # number of cc regfile reads 79011103Snilay@cs.wisc.edusystem.cpu.cc_regfile_writes 3204 # number of cc regfile writes 79111103Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 3054 # number of misc regfile reads 7929459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 79310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 79411103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use 79511103Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. 79611103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 79711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. 79810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor 80011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy 80111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy 80211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 80310892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 80411103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 80511103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 80611103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 5255 # Number of tag accesses 80711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 5255 # Number of data accesses 80811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1436 # number of ReadReq hits 80911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1436 # number of ReadReq hits 81011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits 81111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits 81210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 81310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 81410628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 81510628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 81611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 2032 # number of demand (read+write) hits 81711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 2032 # number of demand (read+write) hits 81811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 2032 # number of overall hits 81911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 2032 # number of overall hits 82011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 181 # number of ReadReq misses 82111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 181 # number of ReadReq misses 82211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses 82311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses 82410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 82510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 82611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 82711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 82811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 82911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 498 # number of overall misses 83011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles 83111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles 83211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles 83311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles 83410892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles 83510892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles 83611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles 83711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles 83811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles 83911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles 84011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) 84111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) 84210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 84310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 84410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 84510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 84610628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 84710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 84811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2530 # number of demand (read+write) accesses 84911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2530 # number of demand (read+write) accesses 85011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2530 # number of overall (read+write) accesses 85111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2530 # number of overall (read+write) accesses 85211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.111936 # miss rate for ReadReq accesses 85311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.111936 # miss rate for ReadReq accesses 85411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses 85511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses 85610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 85710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 85811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.196838 # miss rate for demand accesses 85911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses 86011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses 86111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses 86211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency 86311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency 86411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency 86511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency 86610892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency 86710892Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency 86811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency 86911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency 87011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency 87111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency 87211103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked 87310628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87411103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 87510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 87611103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked 87710628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87810628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 87910628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 88011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits 88111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 88211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits 88311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits 88410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 88510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 88611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits 88711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 88811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits 88911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits 89010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 89110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 89210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 89310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 89410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 89510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 89610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 89710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 89811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles 89911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles 90011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles 90111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles 90211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles 90311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles 90411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles 90511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles 90611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses 90711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses 90810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 90910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 91011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for demand accesses 91111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses 91211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses 91311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses 91411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency 91511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency 91611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency 91711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency 91811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency 91911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency 92011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency 92111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency 92210628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 92310242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.replacements 1 # number of replacements 92411103Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use 92511103Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks. 92610812Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. 92711103Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks. 9289838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 92911103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor 93011103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy 93111103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy 93210812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 93310892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 93410892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id 93510812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 93611103Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses 93711103Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 4229 # Number of data accesses 93811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits 93911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits 94011103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits 94111103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits 94211103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits 94311103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 1582 # number of overall hits 94411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses 94511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses 94611103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses 94711103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses 94811103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses 94911103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 386 # number of overall misses 95011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles 95111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles 95211103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles 95311103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles 95411103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles 95511103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles 95611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) 95711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) 95811103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses 95911103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses 96011103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses 96111103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses 96211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses 96311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses 96411103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses 96511103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses 96611103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses 96711103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses 96811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency 96911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency 97011103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency 97111103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency 97211103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency 97311103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency 97411103Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked 9758889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97610352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 9778889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 97811103Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 # average number of cycles each access was blocked 9798983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9808889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 9818889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 98211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits 98311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits 98411103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits 98511103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits 98611103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 93 # number of overall MSHR hits 98711103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 93 # number of overall MSHR hits 98810812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 98910812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses 99010812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 99110812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses 99210812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 99310812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses 99411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles 99511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles 99611103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles 99711103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles 99811103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles 99911103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles 100011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses 100111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses 100211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses 100311103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses 100411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses 100511103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses 100611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency 100711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency 100811103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency 100911103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency 101011103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency 101111103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency 10128889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 10139838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 101411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use 101510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 101610812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. 101710812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. 10189838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor 102011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor 102111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy 102211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy 102311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy 102410812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 102511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 102611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 102710812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id 102810812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses 102910812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses 103010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 103110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 103210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 21 # number of ReadSharedReq hits 103310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits 103410892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 103510892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits 103610352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 103710892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 103810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits 103910352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 39 # number of overall hits 104010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 104110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 104210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses 104310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses 104410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses 104510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses 104610892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 104710892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses 104810812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses 104910892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 105010892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses 105110812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 401 # number of overall misses 105211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles 105311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles 105411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles 105511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles 105611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles 105711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles 105811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles 105911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles 106011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles 106111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles 106211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles 106311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles 106410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 106510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 106610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) 106710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) 106810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) 106910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) 107010812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses 10719449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 107210812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 107310812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses 10749449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 107510812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 10769449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 10779449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 107810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses 107910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses 108010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.800000 # miss rate for ReadSharedReq accesses 108110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.800000 # miss rate for ReadSharedReq accesses 108210892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses 108310892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses 108410812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses 108510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses 108610892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses 108710812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses 108811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency 108911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency 109011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency 109111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency 109211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency 109311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency 109411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency 109511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency 109611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency 109711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency 109811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency 109911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency 11009449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11019449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11029449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 11039449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 11049449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11059449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11069449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 11079449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 110810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 110910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 11109449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 11119449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 11129449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 11139449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 111410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 111510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 111610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses 111710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses 111810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses 111910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses 112010892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 112110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses 112210812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses 112310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 112410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses 112510812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses 112611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles 112711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles 112811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles 112911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles 113011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles 113111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles 113211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles 113311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles 113411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles 113511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles 113611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles 113711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles 11389449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 11399449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 114010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses 114110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses 114210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses 114310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses 114410892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses 114510892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses 114610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses 114710892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses 114810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses 114910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses 115011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency 115111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency 115211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency 115311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency 115411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency 115511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency 115611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency 115711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency 115811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency 115911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency 116011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency 116111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency 11629449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 116311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 116410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 116510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 116610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution 116710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution 116810812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) 116911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 117011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) 117110812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 117211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 117311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 117410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 117510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 117610827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 117710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 117810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 117910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 118010892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram 118110827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 118210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 118310827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 118410827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 118510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 118610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 118710726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 118810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) 118910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 119011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks) 119110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 119210812Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 354 # Transaction distribution 119310628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 42 # Transaction distribution 119410628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 42 # Transaction distribution 119510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 354 # Transaction distribution 119610812Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) 119710812Snilay@cs.wisc.edusystem.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) 119810812Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) 119910812Snilay@cs.wisc.edusystem.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) 120010628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 120110812Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 396 # Request fanout histogram 120210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 120310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 120410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120510812Snilay@cs.wisc.edusystem.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram 120610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 120710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 120810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 120910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 121010812Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 396 # Request fanout histogram 121110892Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) 121210892Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 121311103Snilay@cs.wisc.edusystem.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks) 121410892Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 12.2 # Layer utilization (%) 12158889Sgeoffrey.blake@arm.com 12168889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1217