stats.txt revision 10827
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 410812Snilay@cs.wisc.edusim_ticks 17398000 # Number of ticks simulated 510812Snilay@cs.wisc.edufinal_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 710827Sandreas.hansson@arm.comhost_inst_rate 57922 # Simulator instruction rate (inst/s) 810827Sandreas.hansson@arm.comhost_op_rate 67825 # Simulator op (including micro ops) rate (op/s) 910827Sandreas.hansson@arm.comhost_tick_rate 219380871 # Simulator tick rate (ticks/s) 1010827Sandreas.hansson@arm.comhost_mem_usage 310080 # Number of bytes of host memory used 1110827Sandreas.hansson@arm.comhost_seconds 0.08 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 4592 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 5378 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 1710812Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory 1810812Snilay@cs.wisc.edusystem.physmem.bytes_read::total 25344 # Number of bytes read from this memory 1910726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 2010726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 2110726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 2210812Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory 2310812Snilay@cs.wisc.edusystem.physmem.num_reads::total 396 # Number of read requests responded to by this memory 2410812Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) 2510812Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) 2610812Snilay@cs.wisc.edusystem.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) 2710812Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) 2810812Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) 2910812Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) 3010812Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) 3110812Snilay@cs.wisc.edusystem.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) 3210812Snilay@cs.wisc.edusystem.physmem.readReqs 396 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410812Snilay@cs.wisc.edusystem.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610812Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910812Snilay@cs.wisc.edusystem.physmem.bytesReadSys 25344 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 90 # Per bank write bursts 4510812Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 45 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 4710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5310242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::9 8 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810812Snilay@cs.wisc.edusystem.physmem.totGap 17318000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510812Snilay@cs.wisc.edusystem.physmem.readPktSize::6 396 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310812Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see 9410812Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see 9510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 9610812Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 9710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 9810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 9910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation 19010812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation 19110812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation 19210812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation 19310812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation 19410812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation 19510812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation 19610812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation 19710812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation 19810812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation 19910812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation 20010812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation 20110812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation 20210812Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation 20310812Snilay@cs.wisc.edusystem.physmem.totQLat 3886750 # Total ticks spent queuing 20410812Snilay@cs.wisc.edusystem.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM 20510812Snilay@cs.wisc.edusystem.physmem.totBusLat 1980000 # Total ticks spent in databus transfers 20610812Snilay@cs.wisc.edusystem.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810812Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst 20910812Snilay@cs.wisc.edusystem.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110812Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410812Snilay@cs.wisc.edusystem.physmem.busUtil 11.38 # Data bus utilization in percentage 21510812Snilay@cs.wisc.edusystem.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710812Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910812Snilay@cs.wisc.edusystem.physmem.readRowHits 331 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110812Snilay@cs.wisc.edusystem.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310812Snilay@cs.wisc.edusystem.physmem.avgGap 43732.32 # Average gap between requests 22410812Snilay@cs.wisc.edusystem.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined 22510812Snilay@cs.wisc.edusystem.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) 22610812Snilay@cs.wisc.edusystem.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) 22710812Snilay@cs.wisc.edusystem.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23010812Snilay@cs.wisc.edusystem.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) 23110812Snilay@cs.wisc.edusystem.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) 23210812Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) 23310812Snilay@cs.wisc.edusystem.physmem_0.averagePower 905.226907 # Core power per rank (mW) 23410812Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23710812Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23910812Snilay@cs.wisc.edusystem.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) 24010812Snilay@cs.wisc.edusystem.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) 24110812Snilay@cs.wisc.edusystem.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24410812Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) 24510812Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) 24610812Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) 24710812Snilay@cs.wisc.edusystem.physmem_1.averagePower 804.955945 # Core power per rank (mW) 24810812Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25110812Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25310812Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2567 # Number of BP lookups 25410812Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted 25510812Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect 25610812Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups 25710812Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 778 # Number of BTB hits 2589481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25910812Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage 26010812Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. 26110812Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 26210628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26310628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26410628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26510628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 26610628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 26710628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 26810628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 26910628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27010628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 27610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 27710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 27810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 27910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 28310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 28410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 28510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 28610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 28710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 28810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 28910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29210628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 29310628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29410628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29510628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 29610628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 29710628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 29810628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 29910628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3008889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 3018889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 3028889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 3038889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 3048889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 3058889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 3068889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3078889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3088889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3098889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3108889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3118889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3128889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3138889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3148889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3158889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 3168889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 3178889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 32110628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 32210628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32310628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32410628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32510628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 32610628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 32710628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 32810628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 33610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 34710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 34810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 34910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35010628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walks 0 # Table walker walks requested 35110628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35210628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35310628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35410628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35510628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3588889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3598889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3608889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3618889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3628889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3638889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3648889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3658889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3668889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3678889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3688889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3698889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3708889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3718889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3728889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3738889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3748889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3758889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3768889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3778889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3788889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3798889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 38010812Snilay@cs.wisc.edusystem.cpu.checker.numCycles 5391 # number of cpu cycles simulated 3818889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3828889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 38310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 41310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4208889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 4218889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 4228889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4238889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4248889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4258889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4268889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4278889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4288889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4298889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4308889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 4318889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4328889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 4338889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4348889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4358889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 4368889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 4378889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 4388889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 4398889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 4408889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 44110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 44810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 45110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 45410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 45510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 45610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 46010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 46110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 46210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 46310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 46410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 46510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 46610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 46710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 46810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 46910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 47010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 47110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4788889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 4798889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4808889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4818889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 4828889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 4838889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4848889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4858889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4868889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4878889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4888889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4898889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4908889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4918889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4928889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4938889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4948889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4958889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4968889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 4978889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 4988889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 49910812Snilay@cs.wisc.edusystem.cpu.numCycles 34797 # number of cpu cycles simulated 5008889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5018889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 50210812Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss 50310812Snilay@cs.wisc.edusystem.cpu.fetch.Insts 12168 # Number of instructions fetch has processed 50410812Snilay@cs.wisc.edusystem.cpu.fetch.Branches 2567 # Number of branches that fetch encountered 50510812Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken 50610812Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked 50710812Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing 50810812Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 50910812Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps 51010812Snilay@cs.wisc.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR 51110812Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 2007 # Number of cache lines fetched 51210812Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 51310812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) 51410812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) 51510812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) 5168889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 51710812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) 51810812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) 51910812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) 52010812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) 52110812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) 52210812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) 52310812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) 52410812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) 52510812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) 5268889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5278889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5288889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 52910812Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) 53010812Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle 53110812Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle 53210812Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle 53310812Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked 53410812Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 2103 # Number of cycles decode is running 53510812Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking 53610812Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing 53710812Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 53810812Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 53910812Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode 54010812Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode 54110812Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing 54210812Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle 54310812Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking 54410812Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst 54510812Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 2012 # Number of cycles rename is running 54610812Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking 54710812Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename 54810812Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full 54910726Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full 55010812Snilay@cs.wisc.edusystem.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full 55110812Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed 55210812Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made 55310812Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups 55410352Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 55510352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 55610812Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing 55710812Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 42 # count of serializing insts renamed 55810812Snilay@cs.wisc.edusystem.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed 55910812Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 409 # count of insts added to the skid buffer 56010812Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. 56110812Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. 56210812Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. 56310812Snilay@cs.wisc.edusystem.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. 56410812Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) 56510352Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 56610812Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 8189 # Number of instructions issued 56710812Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 56810812Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling 56910812Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph 57010352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 57110812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle 57210812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle 57310812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle 5748889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 57510812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle 57610812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle 57710812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle 57810812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle 57910812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle 58010812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle 58110812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle 58210812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle 58310812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle 5848889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5858889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5868889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 58710812Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle 5888889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 58910812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available 59010812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available 59110812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available 59210812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available 59310812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available 59410812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available 59510812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available 59610812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available 59710812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 59810812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available 59910812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available 60010812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available 60110812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available 60210812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available 60310812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available 60410812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available 60510812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available 60610812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available 60710812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available 60810812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available 60910812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available 61010812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available 61110812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available 61210812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available 61310812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available 61410812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available 61510812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available 61610812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available 61710812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available 61810812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available 61910812Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available 6208889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6218889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6228889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 62310812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued 62410812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued 62510812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued 62610812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued 62710812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued 62810812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued 62910812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued 63010812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued 63110812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued 63210812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued 63310812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued 63410812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued 63510812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued 63610812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued 63710812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued 63810812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued 63910812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued 64010812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued 64110812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued 64210812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued 64310812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued 64410812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued 64510812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued 64610812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued 64710812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued 64810812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued 64910812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued 65010812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued 65110812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued 65210812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued 65310812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued 6548889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 6558889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 65610812Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 8189 # Type of FU issued 65710812Snilay@cs.wisc.edusystem.cpu.iq.rate 0.235336 # Inst issue rate 65810812Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 173 # FU busy when requested 65910812Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) 66010812Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads 66110812Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes 66210812Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses 66310352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads 66410352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes 66510726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses 66610812Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses 66710352Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 66810812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores 6698889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 67010812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed 6719312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 67210726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 67310812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed 6748889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6758889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 67610812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled 67710812Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked 6788889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 67910812Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing 68010812Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking 68110812Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 68210812Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ 68310812Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch 68410812Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions 68510812Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions 68610352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 68710812Snilay@cs.wisc.edusystem.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 68810726Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 68910726Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 69010812Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly 69110812Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly 69210812Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute 69310812Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions 69410812Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed 69510812Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute 6968889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 69710812Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 9 # number of nop insts executed 69810812Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 3070 # number of memory reference insts executed 69910812Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 1431 # Number of branches executed 70010812Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 1229 # Number of stores executed 70110812Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.225824 # Inst execution rate 70210812Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit 70310812Snilay@cs.wisc.edusystem.cpu.iew.wb_count 7454 # cumulative count of insts written-back 70410812Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 3520 # num instructions producing a value 70510812Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 6887 # num instructions consuming a value 7068889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 70710812Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.214214 # insts written-back per cycle 70810812Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back 7098889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 71010812Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit 7119459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 71210812Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted 71310812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle 71410812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle 71510812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle 7168889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 71710812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle 71810812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle 71910812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle 72010812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle 72110812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle 72210812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle 72310812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle 72410812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle 72510812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle 7268889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7278889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7288889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 72910812Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle 73010812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 4592 # Number of instructions committed 73110812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 7328889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 73310352Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 73410352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 7358889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 73610812Snilay@cs.wisc.edusystem.cpu.commit.branches 1008 # Number of branches committed 7378889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 73810352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 7398889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 74010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 74110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction 74210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction 74310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction 74410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction 74510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction 74610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction 74710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction 74810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction 74910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction 75010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction 75110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction 75210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction 75310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction 75410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction 75510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction 75610812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction 75710812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction 75810812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction 75910812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction 76010812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction 76110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction 76210812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction 76310812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction 76410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction 76510812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction 76610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 76710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 76810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 76910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 77010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 77110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 77210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 77310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 77410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 5378 # Class of committed instruction 77510812Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 77610812Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 22302 # The number of ROB reads 77710812Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 21197 # The number of ROB writes 77810812Snilay@cs.wisc.edusystem.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself 77910812Snilay@cs.wisc.edusystem.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling 78010812Snilay@cs.wisc.edusystem.cpu.committedInsts 4592 # Number of Instructions Simulated 78110812Snilay@cs.wisc.edusystem.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 78210812Snilay@cs.wisc.edusystem.cpu.cpi 7.577744 # CPI: Cycles Per Instruction 78310812Snilay@cs.wisc.edusystem.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads 78410812Snilay@cs.wisc.edusystem.cpu.ipc 0.131965 # IPC: Instructions Per Cycle 78510812Snilay@cs.wisc.edusystem.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads 78610812Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 7744 # number of integer regfile reads 78710812Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 4257 # number of integer regfile writes 78810726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 32 # number of floating regfile reads 78910812Snilay@cs.wisc.edusystem.cpu.cc_regfile_reads 28092 # number of cc regfile reads 79010812Snilay@cs.wisc.edusystem.cpu.cc_regfile_writes 3277 # number of cc regfile writes 79110812Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 3176 # number of misc regfile reads 7929459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 79310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 79410812Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use 79510812Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. 79610812Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 79710812Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. 79810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79910812Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor 80010812Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy 80110812Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy 80210812Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 80310812Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 80410726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 80510812Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 80610812Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses 80710812Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 5463 # Number of data accesses 80810812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits 80910812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits 81010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits 81110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits 81210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 81310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 81410628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 81510628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 81610812Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits 81710812Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits 81810812Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits 81910812Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 2137 # number of overall hits 82010812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses 82110812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses 82210726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses 82310726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses 82410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 82510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 82610812Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 82710812Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 82810812Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 82910812Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 497 # number of overall misses 83010812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles 83110812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles 83210812Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles 83310812Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles 83410726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles 83510726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles 83610812Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles 83710812Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles 83810812Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles 83910812Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles 84010812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) 84110812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) 84210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 84310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 84410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 84510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 84610628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 84710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 84810812Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses 84910812Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses 85010812Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses 85110812Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses 85210812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses 85310812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses 85410726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses 85510726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses 85610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 85710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 85810812Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses 85910812Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses 86010812Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses 86110812Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses 86210812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency 86310812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency 86410812Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency 86510812Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency 86610726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency 86710726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency 86810812Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency 86910812Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency 87010812Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency 87110812Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency 87210812Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked 87310628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87410812Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 87510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 87610812Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked 87710628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87810628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 87910628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 88010812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 88110812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 88210726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits 88310726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits 88410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 88510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 88610812Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 88710812Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 88810812Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 88910812Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 89010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 89110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 89210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 89310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 89410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 89510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 89610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 89710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 89810812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles 89910812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles 90010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles 90110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles 90210812Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles 90310812Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles 90410812Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles 90510812Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles 90610812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses 90710812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses 90810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 90910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 91010812Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses 91110812Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses 91210812Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses 91310812Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses 91410812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency 91510812Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency 91610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency 91710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency 91810812Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency 91910812Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency 92010812Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency 92110812Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency 92210628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 92310242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.replacements 1 # number of replacements 92410812Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use 92510812Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. 92610812Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. 92710812Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. 9289838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 92910812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor 93010812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy 93110812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy 93210812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id 93310812Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 93410726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 93510812Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id 93610812Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses 93710812Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 4307 # Number of data accesses 93810812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits 93910812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits 94010812Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits 94110812Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits 94210812Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits 94310812Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 1613 # number of overall hits 94410812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses 94510812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses 94610812Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses 94710812Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses 94810812Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses 94910812Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 394 # number of overall misses 95010812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles 95110812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles 95210812Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles 95310812Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles 95410812Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles 95510812Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles 95610812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) 95710812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) 95810812Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses 95910812Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses 96010812Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses 96110812Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses 96210812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses 96310812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses 96410812Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses 96510812Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses 96610812Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses 96710812Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses 96810812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency 96910812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency 97010812Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency 97110812Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency 97210812Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency 97310812Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency 97410812Snilay@cs.wisc.edusystem.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked 9758889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97610352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 9778889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 97810812Snilay@cs.wisc.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked 9798983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9808889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 9818889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 98210812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits 98310812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits 98410812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits 98510812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits 98610812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits 98710812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits 98810812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 98910812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses 99010812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 99110812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses 99210812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 99310812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses 99410812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22179000 # number of ReadReq MSHR miss cycles 99510812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles 99610812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 22179000 # number of demand (read+write) MSHR miss cycles 99710812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles 99810812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 22179000 # number of overall MSHR miss cycles 99910812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles 100010812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for ReadReq accesses 100110812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.145989 # mshr miss rate for ReadReq accesses 100210812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for demand accesses 100310812Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.145989 # mshr miss rate for demand accesses 100410812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for overall accesses 100510812Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.145989 # mshr miss rate for overall accesses 100610812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734 # average ReadReq mshr miss latency 100710812Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734 # average ReadReq mshr miss latency 100810812Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency 100910812Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency 101010812Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency 101110812Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency 10128889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 10139838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 101410812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 186.073007 # Cycle average of tags in use 101510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 101610812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. 101710812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. 10189838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101910812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 140.074126 # Average occupied blocks per requestor 102010812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 45.998881 # Average occupied blocks per requestor 102110812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004275 # Average percentage of cache occupancy 102210812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001404 # Average percentage of cache occupancy 102310812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.005678 # Average percentage of cache occupancy 102410812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 102510812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 102610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 102710812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id 102810812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses 102910812Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses 103010812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 103110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 103210352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 103310812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 103410812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 103510352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 103610812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 103710812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 103810352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 39 # number of overall hits 103910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 104010812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses 104110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::total 359 # number of ReadReq misses 104210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 104310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 104410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 104510812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 104610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses 104710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 104810812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 104910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 401 # number of overall misses 105010812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21706000 # number of ReadReq miss cycles 105110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6539250 # number of ReadReq miss cycles 105210812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::total 28245250 # number of ReadReq miss cycles 105310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles 105410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles 105510812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 21706000 # number of demand (read+write) miss cycles 105610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 9885750 # number of demand (read+write) miss cycles 105710812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 31591750 # number of demand (read+write) miss cycles 105810812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 21706000 # number of overall miss cycles 105910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 9885750 # number of overall miss cycles 106010812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 31591750 # number of overall miss cycles 106110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.inst 293 # number of ReadReq accesses(hits+misses) 106210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 106310812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 106410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 106510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 106610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses 10679449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 106810812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 106910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses 10709449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 107110812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 107210812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.941980 # miss rate for ReadReq accesses 107310812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.790476 # miss rate for ReadReq accesses 107410812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.902010 # miss rate for ReadReq accesses 10759449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 10769449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 107710812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.941980 # miss rate for demand accesses 107810812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.data 0.850340 # miss rate for demand accesses 107910812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses 108010812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses 108110812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses 108210812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses 108310812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency 108410812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency 108510812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency 108610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency 108710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency 108810812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency 108910812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency 109010812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency 109110812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency 109210812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency 109310812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency 10949449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10959449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10969449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 10979449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 10989449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10999449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 11009449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 11019449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 11029449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 11039449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 11049449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 11059449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 11069449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 11079449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 110810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 110910812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses 111010812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::total 354 # number of ReadReq MSHR misses 111110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 111210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 111310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 111410812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 120 # number of demand (read+write) MSHR misses 111510812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses 111610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 111710812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses 111810812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses 111910812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles 112010812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles 112110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles 112210812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles 112310812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles 112410812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles 112510812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles 112610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles 112710812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles 112810812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles 112910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles 113010812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses 113110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses 113210812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses 11339449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 11349449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 113510812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses 113610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses 113710812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses 113810812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses 113910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses 114010812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses 114110812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency 114210812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency 114310812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency 114410812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency 114510812Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency 114610812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency 114710812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency 114810812Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency 114910812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency 115010812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency 115110812Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency 11529449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 115310812Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution 115410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 115510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 115610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 115710812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) 115810812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 115910812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) 116010812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) 116110812Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 116210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 116310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 116410812Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram 116510827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 116610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 116710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 116910827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram 117010827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 117110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117210827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 117310827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 117410812Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram 117510812Snilay@cs.wisc.edusystem.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) 117610726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 117710812Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) 117810812Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 117910812Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) 118010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 118110812Snilay@cs.wisc.edusystem.membus.trans_dist::ReadReq 354 # Transaction distribution 118210812Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 354 # Transaction distribution 118310628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 42 # Transaction distribution 118410628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 42 # Transaction distribution 118510812Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) 118610812Snilay@cs.wisc.edusystem.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) 118710812Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) 118810812Snilay@cs.wisc.edusystem.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) 118910628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 119010812Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 396 # Request fanout histogram 119110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 119210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 119310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 119410812Snilay@cs.wisc.edusystem.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram 119510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 119610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 119710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 119810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 119910812Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 396 # Request fanout histogram 120010812Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) 120110726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 120210812Snilay@cs.wisc.edusystem.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) 120310812Snilay@cs.wisc.edusystem.membus.respLayer1.utilization 12.0 # Layer utilization (%) 12048889Sgeoffrey.blake@arm.com 12058889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1206