stats.txt revision 10628
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 39978Sandreas.hansson@arm.comsim_seconds 0.000016 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 16223000 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 54860 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 64243 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 193800024 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 308908 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 0.08 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 5377 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169978Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 179312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 189978Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25408 # Number of bytes read from this memory 199978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 209978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 219978Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 229312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 239978Sandreas.hansson@arm.comsystem.physmem.num_reads::total 397 # Number of read requests responded to by this memory 2410220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) 2510220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) 2610220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) 2710220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) 2810220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) 2910220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) 3010220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 397 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25408 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 90 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 46 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 43 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 32 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 8 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810220Sandreas.hansson@arm.comsystem.physmem.totGap 16156000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 397 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see 9410220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 9510220Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 969978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 979797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 989348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 19010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation 19110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation 19210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation 19310220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation 19410220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation 19510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 19610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation 19710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 19810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 19910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 20010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.totQLat 3126000 # Total ticks spent queuing 20310220Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM 20410220Sandreas.hansson@arm.comsystem.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 2059978Sandreas.hansson@arm.comsystem.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst 20610220Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst 20810220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s 20910220Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s 21110220Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.busUtil 12.24 # Data bus utilization in percentage 21410220Sandreas.hansson@arm.comsystem.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads 21510220Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 2169978Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing 21710220Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.readRowHits 331 # Number of row buffer hits during reads 21910148Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 2209312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads 22110148Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 2229312Sandreas.hansson@arm.comsystem.physmem.avgGap 40695.21 # Average gap between requests 22310220Sandreas.hansson@arm.comsystem.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 22410148Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) 22510220Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) 22610220Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) 22710220Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22810220Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 22910220Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) 23010220Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) 2319978Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) 2329978Sandreas.hansson@arm.comsystem.physmem_0.averagePower 920.354334 # Core power per rank (mW) 2339729Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states 2349729Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 2359978Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 2369978Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states 2379978Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 2389978Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 2399978Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 2409729Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) 24110148Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24210220Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24310220Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) 24410220Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) 24510036SAli.Saidi@ARM.comsystem.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) 2469978Sandreas.hansson@arm.comsystem.physmem_1.averagePower 810.522027 # Core power per rank (mW) 2479978Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states 2489620Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 2499978Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 2509797Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states 2519481Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 2529978Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2638 # Number of BP lookups 2539797Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 2549481Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect 25510038SAli.Saidi@ARM.comsystem.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups 25610038SAli.Saidi@ARM.comsystem.cpu.branchPred.BTBHits 783 # Number of BTB hits 25710038SAli.Saidi@ARM.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25810038SAli.Saidi@ARM.comsystem.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage 25910038SAli.Saidi@ARM.comsystem.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. 26010038SAli.Saidi@ARM.comsystem.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. 26110038SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 26510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 26610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 26710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 26810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 26910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 27510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 2768889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 2778889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2788889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2798889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2808889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 2818889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 2828889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 2838889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 2848889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2858889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 2868889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 2878889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 2888889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 2898889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 2908889Sgeoffrey.blake@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2918889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 2928889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 2938889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 2948889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 2958889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 2968889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 29710038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 29810038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 29910038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 30010038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 30110038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 30210038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 30310038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 30410038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 30510038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30610038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30710038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30810038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30910038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 31010038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 31110038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 31210038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 31310038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31410038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 31510038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 31610038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 31710038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.hits 0 # DTB hits 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 3218889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 3228889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 3238889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 3248889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 3258889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 3268889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 3278889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3288889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 3298889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 3308889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 3318889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 3328889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 3338889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 3348889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 3358889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3368889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3378889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3388889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 3398889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 3409459Ssaidi@eecs.umich.edusystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 3418889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 3428889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 34610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 34710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 34810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 34910038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walks 0 # Table walker walks requested 35010038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35110038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35210038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35310038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35410038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35510038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35610038SAli.Saidi@ARM.comsystem.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35710038SAli.Saidi@ARM.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 35810038SAli.Saidi@ARM.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 35910038SAli.Saidi@ARM.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 36010038SAli.Saidi@ARM.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 36110038SAli.Saidi@ARM.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 36210038SAli.Saidi@ARM.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 36310038SAli.Saidi@ARM.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3648889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3658889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3668889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3678889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3688889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3698889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3708889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3718889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3728889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3738889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3748889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3758889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3768889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3778889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3788889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 3798889Sgeoffrey.blake@arm.comsystem.cpu.checker.numCycles 5390 # number of cpu cycles simulated 3808889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3818889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 3828889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 3838889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 3848889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 4068889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 4078889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 4088889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 4098889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 4108889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 4118889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 4128889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 4138889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 4148889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 4158889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 4168889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 4178889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 4188889Sgeoffrey.blake@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4198889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 4208889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 4218889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4228889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4238889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4248889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4258889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4268889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42710220Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4288889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4298889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 43010220Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4319978Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 4329978Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4339797Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4349978Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 4359797Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 43610220Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 4379797Sandreas.hansson@arm.comsystem.cpu.dtb.hits 0 # DTB hits 4389978Sandreas.hansson@arm.comsystem.cpu.dtb.misses 0 # DTB misses 43910220Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 44010220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44110220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 4428889Sgeoffrey.blake@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44310220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44410220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44510220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44610220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 44710220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44810220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 44910220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 45010220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45110220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 4528889Sgeoffrey.blake@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 4538889Sgeoffrey.blake@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 4548889Sgeoffrey.blake@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 45510220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45610220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45710220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45810220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 45910220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 4609978Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 4619978Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 4629797Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4639797Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 4649729Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 4659978Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 4669348SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 4679797Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 46810220Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 4699978Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 47010220Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 4719978Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 4729978Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 4739978Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 4749729Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 4759978Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 4769978Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4779978Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 47810038SAli.Saidi@ARM.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4799978Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4809924Ssteve.reinhardt@amd.comsystem.cpu.itb.read_misses 0 # DTB read misses 4819459Ssaidi@eecs.umich.edusystem.cpu.itb.write_hits 0 # DTB write hits 4829978Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4839459Ssaidi@eecs.umich.edusystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4849459Ssaidi@eecs.umich.edusystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48510148Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4869978Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4879978Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4889459Ssaidi@eecs.umich.edusystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4899729Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4909978Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4919459Ssaidi@eecs.umich.edusystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4929978Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4939978Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4949978Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 49510038SAli.Saidi@ARM.comsystem.cpu.itb.hits 0 # DTB hits 4969459Ssaidi@eecs.umich.edusystem.cpu.itb.misses 0 # DTB misses 49710220Sandreas.hansson@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 49810220Sandreas.hansson@arm.comsystem.cpu.numCycles 32447 # number of cpu cycles simulated 49910220Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5008889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 50110220Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss 50210220Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 12484 # Number of instructions fetch has processed 50310220Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2638 # Number of branches that fetch encountered 50410220Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken 50510148Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked 50610220Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing 50710220Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 5089978Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps 5099729Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR 5108889Sgeoffrey.blake@arm.comsystem.cpu.fetch.CacheLines 2068 # Number of cache lines fetched 5118889Sgeoffrey.blake@arm.comsystem.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed 5128889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) 51310220Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) 5148889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) 5159978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 5169978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) 5179978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) 5189978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) 5199978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) 5209978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) 5219978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) 5229978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) 5239978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) 5249978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) 5259978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5269978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5279978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 5289978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) 5299978Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle 5309978Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle 5319978Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle 5329978Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked 5339978Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2145 # Number of cycles decode is running 5349978Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking 5359978Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing 5369978Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch 5379978Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 5389978Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode 5399978Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode 5409978Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing 5419978Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle 5429978Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking 5439978Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst 5449978Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2064 # Number of cycles rename is running 5459978Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking 5468889Sgeoffrey.blake@arm.comsystem.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename 5478889Sgeoffrey.blake@arm.comsystem.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full 5488889Sgeoffrey.blake@arm.comsystem.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full 5499978Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full 5509978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed 5519978Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made 5529978Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups 5539978Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups 5549978Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed 5559978Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing 5569978Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 43 # count of serializing insts renamed 5579978Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 5589978Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 443 # count of insts added to the skid buffer 5599978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. 5609978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. 5619978Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 5629978Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. 5639978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) 5649978Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 5659978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8358 # Number of instructions issued 5669978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued 5679978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling 5689978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph 5699978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 5709978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle 5719978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle 5729978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle 5739978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 5749978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle 5759978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle 5769978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle 5779978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle 5789978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle 5799978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle 5808889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle 5818889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle 5829978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle 58310220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5849978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5859978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 58610220Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle 5879978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 5889978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available 5898889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available 5909322Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available 5918889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available 5929978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available 5938889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available 5949729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available 5958889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available 5969978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available 5979312Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available 5989729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available 5999978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available 6008889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available 6018889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available 6028889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available 6039348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available 6048889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available 6059797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available 6069797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available 6079978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available 6089978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available 6099978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available 6109978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available 6119978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available 6129459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available 6139978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available 6149285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available 6159729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available 6169620Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available 6179797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available 6189797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available 61910220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 62010220Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 62110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 6228889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued 6239348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued 62410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued 6259797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued 6269729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued 62710220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued 6289978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued 6299978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued 6309978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued 63110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued 6328889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued 63310220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued 63410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued 6358889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued 6369978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued 6379459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued 6389620Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued 63910220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued 64010220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued 64110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued 6428889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued 64310220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued 64410220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued 64510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued 64610148Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued 64710220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued 6489978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued 6499978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued 65010220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued 65110220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued 6528889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued 6538889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 6548889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 65510220Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8358 # Type of FU issued 6569459Ssaidi@eecs.umich.edusystem.cpu.iq.rate 0.257589 # Inst issue rate 6579459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_busy_cnt 169 # FU busy when requested 6588889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) 6599459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads 6609459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes 6618889Sgeoffrey.blake@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses 6629459Ssaidi@eecs.umich.edusystem.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads 6638889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes 6649459Ssaidi@eecs.umich.edusystem.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses 6658889Sgeoffrey.blake@arm.comsystem.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses 66610220Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 66710220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores 66810220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 66910220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed 67010220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 67110220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 67210220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed 67310220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 67410220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 67510220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled 67610220Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 67710220Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 67810220Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing 67910220Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking 68010220Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking 68110220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ 68210220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch 68310220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions 68410220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions 68510220Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 68610220Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 68710220Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 68810220Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 68910220Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly 69010220Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly 69110220Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute 69210220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions 69310220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed 69410220Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute 69510220Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 69610220Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 11 # number of nop insts executed 69710220Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3148 # number of memory reference insts executed 69810220Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1457 # Number of branches executed 69910220Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1240 # Number of stores executed 70010220Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.248498 # Inst execution rate 7019978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit 7028889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_count 7601 # cumulative count of insts written-back 70310220Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 3572 # num instructions producing a value 7049978Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6998 # num instructions consuming a value 70510220Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 70610220Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.234259 # insts written-back per cycle 7079459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back 7089459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 7099459Ssaidi@eecs.umich.edusystem.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit 71010220Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 71110220Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted 71210220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle 71310220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle 71410220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle 7159978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 7168889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle 71710038SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle 7189459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle 71910220Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle 7209978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle 7219978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle 7229729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle 7239729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle 7249978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle 7259838Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7269978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7279978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 7289838Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle 7299978Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 4591 # Number of instructions committed 7309978Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 7319729Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 7329978Sandreas.hansson@arm.comsystem.cpu.commit.refs 1965 # Number of memory references committed 7339729Sandreas.hansson@arm.comsystem.cpu.commit.loads 1027 # Number of loads committed 73410220Sandreas.hansson@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 7359978Sandreas.hansson@arm.comsystem.cpu.commit.branches 1007 # Number of branches committed 73610220Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 73710220Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4624 # Number of committed integer instructions. 7389838Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 73910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 7409978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction 7419978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction 7429978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction 7439838Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction 74410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction 74510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction 74610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction 74710036SAli.Saidi@ARM.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction 74810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction 74910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction 75010036SAli.Saidi@ARM.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction 75110036SAli.Saidi@ARM.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction 75210036SAli.Saidi@ARM.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction 7539978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction 7549978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction 7559978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction 7569978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction 7579978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction 7589978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction 7599978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction 7609978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction 7619978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction 7629978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction 7639978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction 7649978Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction 76510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction 76610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 76710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 76810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 76910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 77010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 7719797Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 7729797Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 7739797Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5377 # Class of committed instruction 7749797Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 7759797Sandreas.hansson@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 7769797Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 22692 # The number of ROB reads 7779978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 21720 # The number of ROB writes 7789978Sandreas.hansson@arm.comsystem.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself 7799978Sandreas.hansson@arm.comsystem.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling 7809978Sandreas.hansson@arm.comsystem.cpu.committedInsts 4591 # Number of Instructions Simulated 7819978Sandreas.hansson@arm.comsystem.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 7829978Sandreas.hansson@arm.comsystem.cpu.cpi 7.067523 # CPI: Cycles Per Instruction 78310220Sandreas.hansson@arm.comsystem.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads 78410220Sandreas.hansson@arm.comsystem.cpu.ipc 0.141492 # IPC: Instructions Per Cycle 78510220Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 78610220Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 7945 # number of integer regfile reads 78710220Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 4420 # number of integer regfile writes 78810220Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 31 # number of floating regfile reads 7899978Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 28734 # number of cc regfile reads 7908889Sgeoffrey.blake@arm.comsystem.cpu.cc_regfile_writes 3302 # number of cc regfile writes 7919978Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 3189 # number of misc regfile reads 7928889Sgeoffrey.blake@arm.comsystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 7939978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 7948983Snate@binkert.orgsystem.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use 7958889Sgeoffrey.blake@arm.comsystem.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 7968889Sgeoffrey.blake@arm.comsystem.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 7979729Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. 7989729Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7999729Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor 8009729Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy 8019729Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy 8029729Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 8039978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 8049978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 8059978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 8069978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 8079978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 8089978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 80910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits 81010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits 81110220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits 81210220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 81310220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 81410220Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 8159978Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 8169978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits 8179978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits 8189978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits 8199978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2146 # number of overall hits 8209978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses 82110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses 82210220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 82310220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses 82410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 82510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 82610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 8278889Sgeoffrey.blake@arm.comsystem.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 8289838Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 82910220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 521 # number of overall misses 8309838Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles 8319978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles 8329978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 8339838Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 83410220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 83510220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles 83610220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles 83710220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles 83810220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles 83910036SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles 84010220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 84110220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) 84210036SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 84310036SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 84410036SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 8459729Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 8469449SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 8479729Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 8489729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses 8499449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses 8509729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses 8519729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses 8529449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses 8539729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses 8549978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 8559449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 8569978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 8579449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 8589449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 8599978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 8609449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 8619978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses 8629978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency 8639449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency 8649978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 86510220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 86610220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 86710220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency 86810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 86910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency 87010220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency 87110220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency 87210220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 87310220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87410220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 87510220Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 8769978Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 8779449SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8789978Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8799449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8809449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits 8819978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits 8829449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits 8839978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits 8849978Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 8859449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 8869978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 8879978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 8889449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 8899978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 8909449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 8919449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 8929978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 8939449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 8949978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 8959978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 8969449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 8979978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 89810220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles 89910220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles 90010220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 90110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles 90210148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles 90310220Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles 90410220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles 90510220Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles 90610220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 90710220Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 90810220Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 9099449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 9109449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 9119449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 9129449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 9139449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses 9149449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency 9159449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency 9169449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 9179449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency 9189449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 9199449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 9209449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency 9219449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency 9229449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9239978Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1 # number of replacements 9249449SAli.Saidi@ARM.comsystem.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use 9259978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 9269449SAli.Saidi@ARM.comsystem.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 9279449SAli.Saidi@ARM.comsystem.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. 9289978Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 9299449SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor 9309978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy 9319978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy 9329449SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id 9339978Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 93410220Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 93510220Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id 93610220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses 93710148Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 4430 # Number of data accesses 93810148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits 93910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits 94010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits 94110220Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits 94210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits 94310220Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1666 # number of overall hits 94410220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses 9459978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses 9469449SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses 9479978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses 9489449SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses 9499449SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 402 # number of overall misses 9509978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles 9519449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles 9529978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles 9539978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles 9549449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles 9559978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles 95610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 95710220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 95810220Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 95910148Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 96010148Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 96110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 96210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses 96310220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses 96410220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses 96510220Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses 96610220Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses 9679449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses 9689838Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency 96910220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency 97010220Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency 9719838Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency 97210220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency 9739838Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency 97410220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked 97510220Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97610220Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 97710036SAli.Saidi@ARM.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 97810036SAli.Saidi@ARM.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked 97910036SAli.Saidi@ARM.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98010036SAli.Saidi@ARM.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 98110220Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 98210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits 9839978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits 9849978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits 9859348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits 9869348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 98710220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 98810220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 9899459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 9909459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 9919978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 9929978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 9939978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 9949978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles 9959978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles 9969978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles 9979348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles 9989348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles 9998889Sgeoffrey.blake@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles 10008889Sgeoffrey.blake@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses 10019978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses 10029978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses 10039978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses 10049978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses 100510220Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses 100610220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency 100710148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency 100810148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency 10099797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency 10109797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency 101110220Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency 101210220Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 101310220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 101410220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use 10159978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 10169978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 10178889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. 10188889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101910220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor 102010220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor 10219459Ssaidi@eecs.umich.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy 10229459Ssaidi@eecs.umich.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy 10239978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy 10249978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 10259978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 10269978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 10279978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 10289978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses 10299348SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses 10309348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 103110220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 103210220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 10339978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 10349978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 10359978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 10369978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 103710220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 103810220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 39 # number of overall hits 103910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses 104010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 10419797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses 10429797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 104310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 104410220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 104510220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 104610220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses 10479797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 10488889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 10499348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 402 # number of overall misses 10508889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles 10519797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles 10528983Snate@binkert.orgsystem.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles 10538889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles 10548889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles 10559978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles 10569978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles 10579348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles 10589348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles 10598889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles 10608889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles 10619978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) 10629978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 10639978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 10649978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 10659322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 10669322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 10679348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 10689348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 10699348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 10709348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 10719348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 10729348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses 107310220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 107410220Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses 107510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 107610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 107710220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses 107810220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 107910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses 108010220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses 10819978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 10829978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses 10839348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency 10849348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency 10859978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency 10869978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency 10879978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency 10889978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency 108910220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency 109010220Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency 109110148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency 109210148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency 109310220Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency 109410220Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 109510220Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 109610220Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 10978889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 10988889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10998889Sgeoffrey.blake@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1100system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1101system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1102system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 1103system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 1104system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1105system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 1106system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1107system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 1108system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 1109system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses 1110system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses 1111system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 1112system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 1115system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 1116system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 1119system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles 1120system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles 1121system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles 1122system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles 1123system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles 1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles 1130system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses 1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1134system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 1141system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency 1142system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency 1148system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency 1151system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 1152system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1153system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 1157system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1164system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram 1183system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 1184system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 1185system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 1187system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 1188system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 1189system.membus.trans_dist::ReadReq 355 # Transaction distribution 1190system.membus.trans_dist::ReadResp 355 # Transaction distribution 1191system.membus.trans_dist::ReadExReq 42 # Transaction distribution 1192system.membus.trans_dist::ReadExResp 42 # Transaction distribution 1193system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 1194system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 1195system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 1196system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 1197system.membus.snoops 0 # Total snoops (count) 1198system.membus.snoop_fanout::samples 397 # Request fanout histogram 1199system.membus.snoop_fanout::mean 0 # Request fanout histogram 1200system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1201system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1202system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram 1203system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1204system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1205system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1206system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1207system.membus.snoop_fanout::total 397 # Request fanout histogram 1208system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 1209system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 1210system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 1211system.membus.respLayer1.utilization 22.8 # Layer utilization (%) 1212 1213---------- End Simulation Statistics ---------- 1214