stats.txt revision 10242
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 39978Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 410242Ssteve.reinhardt@amd.comsim_ticks 16786000 # Number of ticks simulated 510242Ssteve.reinhardt@amd.comfinal_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 710242Ssteve.reinhardt@amd.comhost_inst_rate 36444 # Simulator instruction rate (inst/s) 810242Ssteve.reinhardt@amd.comhost_op_rate 45472 # Simulator op (including micro ops) rate (op/s) 910242Ssteve.reinhardt@amd.comhost_tick_rate 133219523 # Simulator tick rate (ticks/s) 1010242Ssteve.reinhardt@amd.comhost_mem_usage 259336 # Number of bytes of host memory used 1110242Ssteve.reinhardt@amd.comhost_seconds 0.13 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 5729 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169978Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 179312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 189978Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25088 # Number of bytes read from this memory 199978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 209978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 219978Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 229312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 239978Sandreas.hansson@arm.comsystem.physmem.num_reads::total 392 # Number of read requests responded to by this memory 2410242Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s) 2510242Ssteve.reinhardt@amd.comsystem.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s) 2610242Ssteve.reinhardt@amd.comsystem.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s) 2710242Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s) 2810242Ssteve.reinhardt@amd.comsystem.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s) 2910242Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s) 3010242Ssteve.reinhardt@amd.comsystem.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s) 3110242Ssteve.reinhardt@amd.comsystem.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 392 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 86 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 46 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 42 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 17 # Per bank write bursts 4910242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::5 33 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5310242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::9 8 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810242Ssteve.reinhardt@amd.comsystem.physmem.totGap 16721500 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 392 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see 9410242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see 9510242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see 9610242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 9710242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 989348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 999348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 19010242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation 19110242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation 19210242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation 19310242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation 19410242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation 19510242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation 19610242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation 19710242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation 19810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation 19910242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation 20010242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation 20310242Ssteve.reinhardt@amd.comsystem.physmem.totQLat 3300000 # Total ticks spent queuing 20410242Ssteve.reinhardt@amd.comsystem.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM 2059978Sandreas.hansson@arm.comsystem.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 20610242Ssteve.reinhardt@amd.comsystem.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810242Ssteve.reinhardt@amd.comsystem.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst 20910242Ssteve.reinhardt@amd.comsystem.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110242Ssteve.reinhardt@amd.comsystem.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410242Ssteve.reinhardt@amd.comsystem.physmem.busUtil 11.68 # Data bus utilization in percentage 21510242Ssteve.reinhardt@amd.comsystem.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710242Ssteve.reinhardt@amd.comsystem.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910148Sandreas.hansson@arm.comsystem.physmem.readRowHits 326 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310242Ssteve.reinhardt@amd.comsystem.physmem.avgGap 42656.89 # Average gap between requests 22410148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined 22510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 11000 # Time in different power states 22610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22810242Ssteve.reinhardt@amd.comsystem.physmem.memoryStateTime::ACT 15315250 # Time in different power states 22910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23010242Ssteve.reinhardt@amd.comsystem.membus.throughput 1494578816 # Throughput (bytes/s) 23110242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadReq 350 # Transaction distribution 2329978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 350 # Transaction distribution 23310242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExReq 42 # Transaction distribution 23410242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExResp 42 # Transaction distribution 23510242Ssteve.reinhardt@amd.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes) 23610242Ssteve.reinhardt@amd.comsystem.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes) 23710242Ssteve.reinhardt@amd.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes) 23810242Ssteve.reinhardt@amd.comsystem.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) 23910242Ssteve.reinhardt@amd.comsystem.membus.data_through_bus 25088 # Total data (bytes) 2409729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 24110242Ssteve.reinhardt@amd.comsystem.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks) 24210220Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 24310242Ssteve.reinhardt@amd.comsystem.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks) 24410242Ssteve.reinhardt@amd.comsystem.membus.respLayer1.utilization 21.8 # Layer utilization (%) 24510036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 24610242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.lookups 2517 # Number of BP lookups 24710242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted 2489620Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 24910242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups 25010242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.BTBHits 714 # Number of BTB hits 2519481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25210242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage 25310242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target. 2549481Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 25510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 25610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 25710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 25810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 25910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 26010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 26110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 26210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 26310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 26410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 26510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 26610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 26710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 26810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 26910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 27010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 27110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 27210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 27310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 27410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 27510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2768889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 2778889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 2788889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 2798889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 2808889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 2818889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 2828889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2838889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2848889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2858889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2868889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2878889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2888889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2898889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2908889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2918889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 2928889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 2938889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 2948889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 2958889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 2968889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 29710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 30210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 30810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 31610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 31710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3218889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3228889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3238889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3248889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3258889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3268889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3278889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3288889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3298889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3308889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3318889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3328889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3338889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3348889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3358889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3368889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3378889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3388889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3398889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 3409459Ssaidi@eecs.umich.edusystem.cpu.checker.numCycles 5742 # number of cpu cycles simulated 3418889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3428889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 34310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 36210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 36310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3648889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 3658889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 3668889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 3678889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 3688889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 3698889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 3708889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3718889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3728889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3738889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3748889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3758889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3768889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3778889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3788889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3798889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 3808889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 3818889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3828889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 3838889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 3848889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 38510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 38610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 39610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 40410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 40510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 4068889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 4078889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4088889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4098889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 4108889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 4118889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4128889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4138889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4148889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4158889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4168889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4178889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4188889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4198889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4208889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4218889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4228889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4238889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4248889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 4258889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 4268889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42710242Ssteve.reinhardt@amd.comsystem.cpu.numCycles 33573 # number of cpu cycles simulated 4288889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4298889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43010242Ssteve.reinhardt@amd.comsystem.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss 43110242Ssteve.reinhardt@amd.comsystem.cpu.fetch.Insts 12073 # Number of instructions fetch has processed 43210242Ssteve.reinhardt@amd.comsystem.cpu.fetch.Branches 2517 # Number of branches that fetch encountered 43310242Ssteve.reinhardt@amd.comsystem.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken 43410242Ssteve.reinhardt@amd.comsystem.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked 43510242Ssteve.reinhardt@amd.comsystem.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing 43610242Ssteve.reinhardt@amd.comsystem.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked 43710242Ssteve.reinhardt@amd.comsystem.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps 43810242Ssteve.reinhardt@amd.comsystem.cpu.fetch.CacheLines 1968 # Number of cache lines fetched 43910242Ssteve.reinhardt@amd.comsystem.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed 44010242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total) 44110242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total) 44210242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total) 4438889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 44410242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total) 44510242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total) 44610242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total) 44710242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total) 44810242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total) 44910242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total) 45010242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total) 45110242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total) 45210242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total) 4538889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4548889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4558889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 45610242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total) 45710242Ssteve.reinhardt@amd.comsystem.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle 45810242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle 45910242Ssteve.reinhardt@amd.comsystem.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle 46010242Ssteve.reinhardt@amd.comsystem.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked 46110242Ssteve.reinhardt@amd.comsystem.cpu.decode.RunCycles 2492 # Number of cycles decode is running 46210242Ssteve.reinhardt@amd.comsystem.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking 46310242Ssteve.reinhardt@amd.comsystem.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing 46410242Ssteve.reinhardt@amd.comsystem.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch 46510242Ssteve.reinhardt@amd.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 46610242Ssteve.reinhardt@amd.comsystem.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode 46710242Ssteve.reinhardt@amd.comsystem.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode 46810242Ssteve.reinhardt@amd.comsystem.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing 46910242Ssteve.reinhardt@amd.comsystem.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle 47010242Ssteve.reinhardt@amd.comsystem.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking 47110242Ssteve.reinhardt@amd.comsystem.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst 47210242Ssteve.reinhardt@amd.comsystem.cpu.rename.RunCycles 2296 # Number of cycles rename is running 47310242Ssteve.reinhardt@amd.comsystem.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking 47410242Ssteve.reinhardt@amd.comsystem.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename 47510242Ssteve.reinhardt@amd.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 47610242Ssteve.reinhardt@amd.comsystem.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full 47710242Ssteve.reinhardt@amd.comsystem.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full 47810242Ssteve.reinhardt@amd.comsystem.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full 47910242Ssteve.reinhardt@amd.comsystem.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed 48010242Ssteve.reinhardt@amd.comsystem.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made 48110242Ssteve.reinhardt@amd.comsystem.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups 48210242Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups 4839459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 48410242Ssteve.reinhardt@amd.comsystem.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing 4859459Ssaidi@eecs.umich.edusystem.cpu.rename.serializingInsts 41 # count of serializing insts renamed 4869459Ssaidi@eecs.umich.edusystem.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 48710242Ssteve.reinhardt@amd.comsystem.cpu.rename.skidInsts 329 # count of insts added to the skid buffer 48810242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit. 48910242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit. 49010242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. 49110242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 49210242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec) 4939459Ssaidi@eecs.umich.edusystem.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 49410242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqInstsIssued 8961 # Number of instructions issued 49510242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued 49610242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling 49710242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph 4989459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 49910242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle 50010242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle 50110242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle 5028889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 50310242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle 50410242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle 50510242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle 50610242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle 50710242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle 50810242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle 50910242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle 51010242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle 51110242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle 5128889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5138889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5148889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 51510242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle 5168889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 51710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available 51810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available 51910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available 52010242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available 52110242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available 52210242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available 52310242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available 52410242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available 52510242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available 52610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available 52710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available 52810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available 52910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available 53010242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available 53110242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available 53210242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available 53310242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available 53410242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available 53510242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available 53610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available 53710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available 53810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available 53910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available 54010242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available 54110242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available 54210242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available 54310242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available 54410242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available 54510242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available 54610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available 54710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available 5488889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5498889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5508889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 55110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued 55210242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued 55310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued 55410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued 55510242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued 55610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued 55710242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued 55810242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued 55910242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued 56010242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued 56110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued 56210242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued 56310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued 56410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued 56510242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued 56610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued 56710242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued 56810242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued 56910242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued 57010242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued 57110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued 57210242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued 57310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued 57410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued 57510242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued 57610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued 57710242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued 57810242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued 57910242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued 58010242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued 58110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued 5828889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5838889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 58410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::total 8961 # Type of FU issued 58510242Ssteve.reinhardt@amd.comsystem.cpu.iq.rate 0.266911 # Inst issue rate 58610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_busy_cnt 221 # FU busy when requested 58710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) 58810242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads 58910242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes 59010242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses 5918889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 5929322Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 5938889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 59410242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses 5958889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 5969729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 5978889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 59810242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed 5999312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 6009729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 60110242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed 6028889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6038889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 6048889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 6059348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 6068889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 60710242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing 60810242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking 60910242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking 61010242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ 61110242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch 61210242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions 61310242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions 6149459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 6159978Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 61610242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 6179729Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 61810242Ssteve.reinhardt@amd.comsystem.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 61910242Ssteve.reinhardt@amd.comsystem.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly 62010242Ssteve.reinhardt@amd.comsystem.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute 62110242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions 62210242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed 62310242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute 6248889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 62510242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_nop 1 # number of nop insts executed 62610242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_refs 3332 # number of memory reference insts executed 62710242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_branches 1443 # Number of branches executed 62810242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_stores 1172 # Number of stores executed 62910242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_rate 0.255205 # Inst execution rate 63010242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit 63110242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_count 8093 # cumulative count of insts written-back 63210242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_producers 3919 # num instructions producing a value 63310242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_consumers 8062 # num instructions consuming a value 6348889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 63510242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_rate 0.241057 # insts written-back per cycle 63610242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back 6378889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 63810242Ssteve.reinhardt@amd.comsystem.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit 6399459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 64010242Ssteve.reinhardt@amd.comsystem.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted 64110242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle 64210242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle 64310242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle 6448889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 64510242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle 64610242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle 64710242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle 64810242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle 64910242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle 65010242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle 65110242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle 65210242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle 65310242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle 6548889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6558889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6568889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 65710242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle 6589459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 4591 # Number of instructions committed 6599459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 6608889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 6619459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 2138 # Number of memory references committed 6629459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 1200 # Number of loads committed 6638889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 6649459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 1007 # Number of branches committed 6658889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 6669459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 6678889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 66810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 66910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction 67010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction 67110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction 67210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction 67310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction 67410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction 67510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction 67610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction 67710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction 67810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction 67910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction 68010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction 68110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction 68210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction 68310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction 68410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction 68510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction 68610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction 68710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction 68810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction 68910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction 69010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction 69110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction 69210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction 69310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction 69410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction 69510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction 69610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction 69710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction 69810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction 69910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction 70010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 70110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 70210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5729 # Class of committed instruction 70310242Ssteve.reinhardt@amd.comsystem.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached 7048889Sgeoffrey.blake@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 70510242Ssteve.reinhardt@amd.comsystem.cpu.rob.rob_reads 23212 # The number of ROB reads 70610242Ssteve.reinhardt@amd.comsystem.cpu.rob.rob_writes 23723 # The number of ROB writes 70710242Ssteve.reinhardt@amd.comsystem.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself 70810242Ssteve.reinhardt@amd.comsystem.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling 7099459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 4591 # Number of Instructions Simulated 7109459Ssaidi@eecs.umich.edusystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 71110242Ssteve.reinhardt@amd.comsystem.cpu.cpi 7.312786 # CPI: Cycles Per Instruction 71210242Ssteve.reinhardt@amd.comsystem.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads 71310242Ssteve.reinhardt@amd.comsystem.cpu.ipc 0.136747 # IPC: Instructions Per Cycle 71410242Ssteve.reinhardt@amd.comsystem.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads 71510242Ssteve.reinhardt@amd.comsystem.cpu.int_regfile_reads 39407 # number of integer regfile reads 71610242Ssteve.reinhardt@amd.comsystem.cpu.int_regfile_writes 7992 # number of integer regfile writes 7178889Sgeoffrey.blake@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 71810242Ssteve.reinhardt@amd.comsystem.cpu.misc_regfile_reads 3253 # number of misc regfile reads 7199459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 72010242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s) 72110242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution 72210242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution 72310242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 72410242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 72510242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes) 7269838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 72710242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes) 72810242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) 7299838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 73010242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes) 73110242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes) 73210242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) 7339978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 7349729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 73510242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks) 73610242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 73710220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) 73810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 73910242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.replacements 1 # number of replacements 74010242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use 74110242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks. 7429978Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 74310242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks. 7449838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 74510242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor 74610242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy 74710242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy 74810242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id 74910242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 75010242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 75110242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id 75210242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses 75310242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.data_accesses 4226 # Number of data accesses 75410242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits 75510242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits 75610242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits 75710242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits 75810242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits 75910242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::total 1601 # number of overall hits 76010242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses 76110242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses 76210242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses 76310242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses 76410242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses 76510242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_misses::total 367 # number of overall misses 76610242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles 76710242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles 76810242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_latency::cpu.inst 23960000 # number of demand (read+write) miss cycles 76910242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_latency::total 23960000 # number of demand (read+write) miss cycles 77010242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_latency::cpu.inst 23960000 # number of overall miss cycles 77110242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_latency::total 23960000 # number of overall miss cycles 77210242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) 77310242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) 77410242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses 77510242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses 77610242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses 77710242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses 77810242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186484 # miss rate for ReadReq accesses 77910242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::total 0.186484 # miss rate for ReadReq accesses 78010242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.186484 # miss rate for demand accesses 78110242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::total 0.186484 # miss rate for demand accesses 78210242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.186484 # miss rate for overall accesses 78310242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::total 0.186484 # miss rate for overall accesses 78410242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65286.103542 # average ReadReq miss latency 78510242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542 # average ReadReq miss latency 78610242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency 78710242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_miss_latency::total 65286.103542 # average overall miss latency 78810242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency 78910242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_miss_latency::total 65286.103542 # average overall miss latency 79010242Ssteve.reinhardt@amd.comsystem.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked 7918889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7929978Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 7938889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 79410242Ssteve.reinhardt@amd.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 53.500000 # average number of cycles each access was blocked 7958983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7968889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 7978889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 79810242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits 79910242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 80010242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits 80110242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits 80210242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits 80310242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits 8049978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 8059978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 8069978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 8079978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 8089978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 8099978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 81010242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19152500 # number of ReadReq MSHR miss cycles 81110242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 19152500 # number of ReadReq MSHR miss cycles 81210242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 19152500 # number of demand (read+write) MSHR miss cycles 81310242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_latency::total 19152500 # number of demand (read+write) MSHR miss cycles 81410242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 19152500 # number of overall MSHR miss cycles 81510242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_latency::total 19152500 # number of overall MSHR miss cycles 81610242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for ReadReq accesses 81710242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.147358 # mshr miss rate for ReadReq accesses 81810242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for demand accesses 81910242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.147358 # mshr miss rate for demand accesses 82010242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147358 # mshr miss rate for overall accesses 82110242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.147358 # mshr miss rate for overall accesses 82210242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66043.103448 # average ReadReq mshr miss latency 82310242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66043.103448 # average ReadReq mshr miss latency 82410242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency 82510242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency 82610242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66043.103448 # average overall mshr miss latency 82710242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 66043.103448 # average overall mshr miss latency 8288889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 8299838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 83010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.tagsinuse 185.364644 # Cycle average of tags in use 83110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks. 8329978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 83310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.avg_refs 0.105714 # Average number of references to valid blocks. 8349838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 83510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 138.907401 # Average occupied blocks per requestor 83610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 46.457243 # Average occupied blocks per requestor 83710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004239 # Average percentage of cache occupancy 83810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001418 # Average percentage of cache occupancy 83910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::total 0.005657 # Average percentage of cache occupancy 84010036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 84110220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 84210220Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 84310036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 84410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.tag_accesses 3864 # Number of tag accesses 84510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.data_accesses 3864 # Number of data accesses 84610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 8479449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 84810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits 84910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 8509449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 85110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits 85210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 8539449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 85410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_hits::total 37 # number of overall hits 8559978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 85610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 85710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_misses::total 355 # number of ReadReq misses 85810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 85910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 8609978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 8619449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 8629978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 8639978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 8649449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 8659978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 397 # number of overall misses 86610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18683000 # number of ReadReq miss cycles 86710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6637250 # number of ReadReq miss cycles 86810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_latency::total 25320250 # number of ReadReq miss cycles 86910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3108750 # number of ReadExReq miss cycles 87010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3108750 # number of ReadExReq miss cycles 87110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 18683000 # number of demand (read+write) miss cycles 87210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9746000 # number of demand (read+write) miss cycles 87310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_latency::total 28429000 # number of demand (read+write) miss cycles 87410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 18683000 # number of overall miss cycles 87510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9746000 # number of overall miss cycles 87610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_latency::total 28429000 # number of overall miss cycles 87710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 287 # number of ReadReq accesses(hits+misses) 87810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 87910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::total 392 # number of ReadReq accesses(hits+misses) 88010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 88110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 88210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::cpu.inst 287 # number of demand (read+write) accesses 8839449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 88410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses 88510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::cpu.inst 287 # number of overall (read+write) accesses 8869449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 88710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses 88810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.940767 # miss rate for ReadReq accesses 88910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 89010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.905612 # miss rate for ReadReq accesses 8919449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8929449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 89310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.940767 # miss rate for demand accesses 8949449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 89510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_rate::total 0.914747 # miss rate for demand accesses 89610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.940767 # miss rate for overall accesses 8979449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 89810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_rate::total 0.914747 # miss rate for overall accesses 89910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69196.296296 # average ReadReq miss latency 90010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78085.294118 # average ReadReq miss latency 90110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 71324.647887 # average ReadReq miss latency 90210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74017.857143 # average ReadExReq miss latency 90310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74017.857143 # average ReadExReq miss latency 90410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency 90510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency 90610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71609.571788 # average overall miss latency 90710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency 90810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency 90910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71609.571788 # average overall miss latency 9109449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 9119449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9129449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 9139449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 9149449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 9159449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9169449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 9179449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 9189449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 9199449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 9209449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 9219449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 9229449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 9239449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 9249978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 92510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses 92610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 92710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 92810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 9299978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 9309449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 9319978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 9329978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 9339449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 9349978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 93510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15291000 # number of ReadReq MSHR miss cycles 93610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5345250 # number of ReadReq MSHR miss cycles 93710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 20636250 # number of ReadReq MSHR miss cycles 93810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2596250 # number of ReadExReq MSHR miss cycles 93910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2596250 # number of ReadExReq MSHR miss cycles 94010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15291000 # number of demand (read+write) MSHR miss cycles 94110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7941500 # number of demand (read+write) MSHR miss cycles 94210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23232500 # number of demand (read+write) MSHR miss cycles 94310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15291000 # number of overall MSHR miss cycles 94410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7941500 # number of overall MSHR miss cycles 94510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23232500 # number of overall MSHR miss cycles 94610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for ReadReq accesses 94710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses 94810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892857 # mshr miss rate for ReadReq accesses 9499449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9509449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 95110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for demand accesses 9529449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 95310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # mshr miss rate for demand accesses 95410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for overall accesses 9559449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 95610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.903226 # mshr miss rate for overall accesses 95710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56633.333333 # average ReadReq mshr miss latency 95810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66815.625000 # average ReadReq mshr miss latency 95910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58960.714286 # average ReadReq mshr miss latency 96010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61815.476190 # average ReadExReq mshr miss latency 96110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61815.476190 # average ReadExReq mshr miss latency 96210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency 96310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency 96410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency 96510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency 96610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency 96710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency 9689449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 9699838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 97010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use 97110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. 9729838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 97310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks. 9749838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 97510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor 97610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy 97710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy 97810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 97910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 98010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id 98110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 98210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses 98310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.data_accesses 5964 # Number of data accesses 98410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits 98510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits 98610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits 98710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits 98810220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 98910220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 9909459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 9919459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 99210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::cpu.data 2378 # number of demand (read+write) hits 99310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::total 2378 # number of demand (read+write) hits 99410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::cpu.data 2378 # number of overall hits 99510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::total 2378 # number of overall hits 99610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses 99710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses 99810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses 99910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses 10008889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 10018889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 100210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses 100310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses 100410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses 100510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_misses::total 507 # number of overall misses 100610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles 100710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles 100810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles 100910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles 10109797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 10119797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 101210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles 101310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles 101410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles 101510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles 101610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses) 101710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) 10188889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 10198889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 102010220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 102110220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 10229459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 10239459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 102410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses 102510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses 102610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses 102710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses 102810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses 102910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses 103010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses 103110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses 103210220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 103310220Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 103410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses 103510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses 103610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses 103710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses 103810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency 103910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency 104010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency 104110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency 10429797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 10439797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 104410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency 104510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency 104610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency 104710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency 104810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked 10498889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10509348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 10518889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 105210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked 10538983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10548889Sgeoffrey.blake@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 10558889Sgeoffrey.blake@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 105610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits 105710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 105810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits 105910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits 10608889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 10618889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 106210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits 106310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits 106410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits 106510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits 106610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 106710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 106810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 106910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 10709348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 10719348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 10729348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 10739348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 107410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles 107510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles 107610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles 107710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles 107810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles 107910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles 108010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles 108110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles 108210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses 108310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses 108410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 108510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 108610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses 108710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses 108810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses 108910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses 109010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency 109110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency 109210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency 109310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency 109410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency 109510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency 109610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency 109710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency 10988889Sgeoffrey.blake@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10998889Sgeoffrey.blake@arm.com 11008889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1101