stats.txt revision 10220
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 310352Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 410352Sandreas.hansson@arm.comsim_ticks 16955000 # Number of ticks simulated 510352Sandreas.hansson@arm.comfinal_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 43189 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 53887 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 159459409 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 309444 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 0.11 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 5729 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610352Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 179312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25088 # Number of bytes read from this memory 1910352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 2010352Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 229312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 2310352Sandreas.hansson@arm.comsystem.physmem.num_reads::total 392 # Number of read requests responded to by this memory 2410352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) 2510352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) 2610352Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) 2710352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) 2810352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) 2910352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) 3010352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) 3110352Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) 3210352Sandreas.hansson@arm.comsystem.physmem.readReqs 392 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410352Sandreas.hansson@arm.comsystem.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610352Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910352Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4410352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 86 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 46 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 4710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 42 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 17 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 34 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 5310242Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::9 7 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810352Sandreas.hansson@arm.comsystem.physmem.totGap 16897500 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510352Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 392 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see 9410409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 9510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 9610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 9710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 9810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 9910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 19010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation 19110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation 19210352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation 19310352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation 19410352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation 19510352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation 19610352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation 19710352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation 19810352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation 19910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation 20010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation 20110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation 20210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation 20310409Sandreas.hansson@arm.comsystem.physmem.totQLat 3795000 # Total ticks spent queuing 20410352Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM 20510409Sandreas.hansson@arm.comsystem.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 2069978Sandreas.hansson@arm.comsystem.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst 20710409Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810352Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst 2099978Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s 21010352Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21310352Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410352Sandreas.hansson@arm.comsystem.physmem.busUtil 11.56 # Data bus utilization in percentage 2159978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads 21610352Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 2179978Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing 21810352Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 2199312Sandreas.hansson@arm.comsystem.physmem.readRowHits 326 # Number of row buffer hits during reads 22010352Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 2219312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads 22210352Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310352Sandreas.hansson@arm.comsystem.physmem.avgGap 43105.87 # Average gap between requests 22410628Sandreas.hansson@arm.comsystem.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined 22510628Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 11000 # Time in different power states 22610628Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22710628Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22810628Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 15324750 # Time in different power states 22910628Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23010628Sandreas.hansson@arm.comsystem.membus.throughput 1475906812 # Throughput (bytes/s) 23110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 351 # Transaction distribution 23210628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 350 # Transaction distribution 23310628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 41 # Transaction distribution 23410628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 41 # Transaction distribution 23510628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 23610628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 23710628Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 23810628Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 23910628Sandreas.hansson@arm.comsystem.membus.data_through_bus 25024 # Total data (bytes) 24010628Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 24110628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 24210628Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 24310628Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) 24410628Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 21.5 # Layer utilization (%) 24510628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 24610628Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2481 # Number of BP lookups 24710628Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 24810628Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 24910628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 25010628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 697 # Number of BTB hits 25110628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25210352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 25310352Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 25410352Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 25510352Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 25610352Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2579481Snilay@cs.wisc.edusystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 25810352Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 25910352Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 26010352Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 26110628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 26210628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 26310628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 26410628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 26510628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 26610628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 26710628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 26810628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 26910628Sandreas.hansson@arm.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 27010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 27110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 27210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 27310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 27410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 27510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 27610038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 27710038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 27810038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 27910038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 28010038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 28110038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 28210038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 28310038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28410038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28510038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28610038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 28710038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 28810038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 28910038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 29010038SAli.Saidi@ARM.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29110628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 29210628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 29310628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 29410628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 29510628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 29610628Sandreas.hansson@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 29710628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29810628Sandreas.hansson@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 2998889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 3008889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 3018889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 3028889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 3038889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 3048889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3058889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3068889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3078889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 3088889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 3098889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 3108889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 3118889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3128889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 3138889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 3148889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 3158889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 3168889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 3178889Sgeoffrey.blake@arm.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 32010628Sandreas.hansson@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 32110628Sandreas.hansson@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 32210628Sandreas.hansson@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 32310628Sandreas.hansson@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 32410628Sandreas.hansson@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 32510628Sandreas.hansson@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32610628Sandreas.hansson@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32710628Sandreas.hansson@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32810038SAli.Saidi@ARM.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 32910038SAli.Saidi@ARM.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 33010038SAli.Saidi@ARM.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 33110038SAli.Saidi@ARM.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 33210038SAli.Saidi@ARM.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33310038SAli.Saidi@ARM.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 33410038SAli.Saidi@ARM.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 33510038SAli.Saidi@ARM.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 33610038SAli.Saidi@ARM.comsystem.cpu.checker.itb.hits 0 # DTB hits 33710038SAli.Saidi@ARM.comsystem.cpu.checker.itb.misses 0 # DTB misses 33810038SAli.Saidi@ARM.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 33910038SAli.Saidi@ARM.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 34010038SAli.Saidi@ARM.comsystem.cpu.checker.numCycles 5742 # number of cpu cycles simulated 34110038SAli.Saidi@ARM.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 34210038SAli.Saidi@ARM.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 34310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 3578889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3588889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 3598889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 3608889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 3618889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 3628889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 3638889Sgeoffrey.blake@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3648889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 3658889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 3668889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 3678889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 3688889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 3698889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 3708889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3718889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3728889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3738889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3748889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3758889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3768889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3778889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3788889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37910352Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 3808889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 3818889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 38210628Sandreas.hansson@arm.comsystem.cpu.dtb.hits 0 # DTB hits 38310628Sandreas.hansson@arm.comsystem.cpu.dtb.misses 0 # DTB misses 38410628Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 38510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 38610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 39610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 40410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 40510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 40610038SAli.Saidi@ARM.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 40710038SAli.Saidi@ARM.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40810038SAli.Saidi@ARM.comsystem.cpu.itb.read_hits 0 # DTB read hits 40910038SAli.Saidi@ARM.comsystem.cpu.itb.read_misses 0 # DTB read misses 41010038SAli.Saidi@ARM.comsystem.cpu.itb.write_hits 0 # DTB write hits 41110628Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41210628Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41310628Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41410628Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41510628Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41610628Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 41710628Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41810628Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4198889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4208889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4218889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4228889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4238889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4248889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 4258889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 4268889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 4278889Sgeoffrey.blake@arm.comsystem.cpu.numCycles 33911 # number of cpu cycles simulated 4288889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4298889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 4308889Sgeoffrey.blake@arm.comsystem.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss 4318889Sgeoffrey.blake@arm.comsystem.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 4328889Sgeoffrey.blake@arm.comsystem.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 4338889Sgeoffrey.blake@arm.comsystem.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 4348889Sgeoffrey.blake@arm.comsystem.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 4358889Sgeoffrey.blake@arm.comsystem.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 4368889Sgeoffrey.blake@arm.comsystem.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked 4378889Sgeoffrey.blake@arm.comsystem.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 4388889Sgeoffrey.blake@arm.comsystem.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 4398889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) 44010628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) 44110628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) 44210628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 44310628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) 44410628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) 44510628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) 44610628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) 44710628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) 44810038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) 44910038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) 45010038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) 45110038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) 45210038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 45310038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 45410038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 45510038SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) 45610038SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle 45710038SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle 45810038SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle 45910038SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked 46010038SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2426 # Number of cycles decode is running 46110038SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 46210038SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 46310038SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 46410038SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 46510038SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 46610038SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 46710038SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 46810038SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle 46910628Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 47010628Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst 47110628Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2227 # Number of cycles rename is running 47210628Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 47310628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 47410628Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 47510628Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 47610628Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 4778889Sgeoffrey.blake@arm.comsystem.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 4788889Sgeoffrey.blake@arm.comsystem.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made 4798889Sgeoffrey.blake@arm.comsystem.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 4808889Sgeoffrey.blake@arm.comsystem.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 4818889Sgeoffrey.blake@arm.comsystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 4828889Sgeoffrey.blake@arm.comsystem.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 4838889Sgeoffrey.blake@arm.comsystem.cpu.rename.serializingInsts 41 # count of serializing insts renamed 4848889Sgeoffrey.blake@arm.comsystem.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 4858889Sgeoffrey.blake@arm.comsystem.cpu.rename.skidInsts 666 # count of insts added to the skid buffer 4868889Sgeoffrey.blake@arm.comsystem.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 4878889Sgeoffrey.blake@arm.comsystem.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 4888889Sgeoffrey.blake@arm.comsystem.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 4898889Sgeoffrey.blake@arm.comsystem.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 4908889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 4918889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 4928889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 4938889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 4948889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 4958889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph 4968889Sgeoffrey.blake@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 4978889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle 49810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle 4998889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle 5008889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 50110352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle 50210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle 50310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle 50410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle 50510352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle 50610488Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle 50710352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle 50810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 50910352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 51010352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 51110352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 51210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 51310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle 51410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 5158889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 51610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 51710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 51810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 51910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 52010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 52110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 52210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 52310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 52410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 5258889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 5268889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 5278889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 52810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 52910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 53010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 53110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 53210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 53310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 53410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 53510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 53610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 53710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 53810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 53910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 54010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 54110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 54210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 54310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 54410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 54510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 54610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 54710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 54810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 54910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 55010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 55110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 55210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 55310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 55410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 55510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 55610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 55710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 55810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 55910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 56010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 56110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 56210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 56310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 56410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 56510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 56610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 56710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 56810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 56910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 57010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 57110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 57210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 5738889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 57410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 57510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 57610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 57710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 57810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 57910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 58010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 58110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 58210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8921 # Type of FU issued 5838889Sgeoffrey.blake@arm.comsystem.cpu.iq.rate 0.263071 # Inst issue rate 5848889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_busy_cnt 224 # FU busy when requested 5858889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 58610352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads 5878889Sgeoffrey.blake@arm.comsystem.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 58810352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 58910352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 59010352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 59110352Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 59210352Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 59310352Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 59410352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 59510352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 59610352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 59710352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 59810352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 59910352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 60010352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 60110352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 60210352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 60310352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 60410352Sandreas.hansson@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 60510352Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 60610352Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 60710352Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 60810352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 60910352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 61010352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 61110352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 61210352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 61310352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 61410352Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 61510352Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 61610352Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 61710352Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 61810352Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 6198889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions 6208889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed 6218889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute 62210352Sandreas.hansson@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 62310352Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 62410352Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3300 # number of memory reference insts executed 62510352Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1437 # Number of branches executed 62610352Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1160 # Number of stores executed 62710352Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.251364 # Inst execution rate 62810352Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 62910352Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 8068 # cumulative count of insts written-back 63010352Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 3883 # num instructions producing a value 63110352Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7789 # num instructions consuming a value 63210352Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 63310352Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.237917 # insts written-back per cycle 63410352Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back 63510352Sandreas.hansson@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 63610352Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 63710352Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 63810352Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 63910352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle 64010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle 64110352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle 64210352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 64310352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle 64410352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle 64510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle 64610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle 64710352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle 64810352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 64910352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 65010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle 65110352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle 65210352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6538889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6548889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 65510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle 65610352Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 4591 # Number of instructions committed 65710352Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 65810352Sandreas.hansson@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 65910352Sandreas.hansson@arm.comsystem.cpu.commit.refs 2138 # Number of memory references committed 66010352Sandreas.hansson@arm.comsystem.cpu.commit.loads 1200 # Number of loads committed 66110352Sandreas.hansson@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 66210352Sandreas.hansson@arm.comsystem.cpu.commit.branches 1007 # Number of branches committed 66310352Sandreas.hansson@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 66410352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 66510352Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 66610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 66710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction 6688889Sgeoffrey.blake@arm.comsystem.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction 66910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction 6709312Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction 67110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction 67210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction 6738889Sgeoffrey.blake@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction 6748889Sgeoffrey.blake@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction 67510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction 67610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction 6778889Sgeoffrey.blake@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction 67810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction 67910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction 68010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction 68110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction 68210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction 68310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction 68410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction 68510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction 68610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction 68710242Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction 68810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction 68910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction 69010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction 69110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction 69210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction 69310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction 69410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction 6958889Sgeoffrey.blake@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction 69610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction 69710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction 69810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 69910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 70010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 5729 # Class of committed instruction 70110352Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 70210352Sandreas.hansson@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 70310352Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 23248 # The number of ROB reads 70410352Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 23415 # The number of ROB writes 7058889Sgeoffrey.blake@arm.comsystem.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself 70610352Sandreas.hansson@arm.comsystem.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling 70710352Sandreas.hansson@arm.comsystem.cpu.committedInsts 4591 # Number of Instructions Simulated 7088889Sgeoffrey.blake@arm.comsystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 70910352Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 4591 # Number of Instructions Simulated 7109459Ssaidi@eecs.umich.edusystem.cpu.cpi 7.386408 # CPI: Cycles Per Instruction 71110352Sandreas.hansson@arm.comsystem.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads 71210352Sandreas.hansson@arm.comsystem.cpu.ipc 0.135384 # IPC: Instructions Per Cycle 71310352Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads 71410352Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 39214 # number of integer regfile reads 7158889Sgeoffrey.blake@arm.comsystem.cpu.int_regfile_writes 7985 # number of integer regfile writes 71610352Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 71710352Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 3239 # number of misc regfile reads 71810352Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 71910352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) 72010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 72110352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 72210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 72310352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 72410352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 7258889Sgeoffrey.blake@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 7268889Sgeoffrey.blake@arm.comsystem.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 7278889Sgeoffrey.blake@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 72810352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 7299459Ssaidi@eecs.umich.edusystem.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 73010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 7318889Sgeoffrey.blake@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 73210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 73310352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 7348889Sgeoffrey.blake@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) 7359459Ssaidi@eecs.umich.edusystem.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 7368889Sgeoffrey.blake@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) 73710352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 7388889Sgeoffrey.blake@arm.comsystem.cpu.icache.tags.replacements 4 # number of replacements 73910220Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use 74010352Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 74110352Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 74210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 74310352Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 74410352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor 74510352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy 74610352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy 74710352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 74810352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 74910352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 75010352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 75110352Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 75210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 4184 # Number of data accesses 75310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 75410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 75510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 75610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 75710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 75810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1584 # number of overall hits 75910352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 76010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 76110352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 76210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 76310352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 76410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 363 # number of overall misses 76510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles 76610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles 76710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles 76810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles 76910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles 77010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles 77110220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 77210220Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 77310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 77410352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 7758889Sgeoffrey.blake@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 77610352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 77710488Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 77810352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 77910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 7809459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 78110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 78210352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 78310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency 78410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency 78510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 78610488Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency 78710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency 78810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency 78910352Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 79010352Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 79110352Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 7929459Ssaidi@eecs.umich.edusystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 79310628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 79410628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 79510628Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 79610628Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 79710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 79810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 79910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 80010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 80110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 80210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 80310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 80410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 80510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 80610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 80710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 80810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 80910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles 81010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles 81110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles 81210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles 81310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles 81410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles 81510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 81610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 81710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 81810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 81910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 82010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 82110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency 82210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency 82310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 82410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 82510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency 82610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency 82710628Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 82810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 82910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use 83010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 83110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 83210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 83310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 83410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor 83510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor 83610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy 83710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy 83810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy 83910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 84010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 84110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 84210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 84310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 84410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 84510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 84610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 84710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 84810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 84910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 85010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 85110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 85210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 85310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 40 # number of overall hits 85410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 85510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 85610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 85710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 85810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 85910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 86010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 86110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 86210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 86310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 86410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 397 # number of overall misses 86510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles 86610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles 86710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles 86810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles 86910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles 87010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles 87110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles 87210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles 87310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles 87410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles 87510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles 87610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 87710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 87810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 87910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 88010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 88110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 88210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 88310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 88410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 88510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 88610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 88710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 88810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 88910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 89010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 89110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 89210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 89310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 89410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 89510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 89610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 89710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 89810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency 89910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency 90010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency 90110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency 90210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency 90310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 90410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 90510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency 90610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency 90710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency 90810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency 90910628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91010628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91110628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 91210628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 91310628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91410628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91510628Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 91610628Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 91710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 91810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 91910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 92010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 92110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 92210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 92310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 92410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 92510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 92610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 92710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 9289838Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 92910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 93010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 93110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 93210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 93310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 93410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles 93510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles 93610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles 93710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles 93810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles 93910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles 94010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles 94110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles 94210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles 94310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles 94410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles 94510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 94610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 94710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 94810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 94910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 95010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 95110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 95210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 95310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 95410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 95510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 95610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency 95710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency 95810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency 95910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency 96010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency 96110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 96210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 96310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 96410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency 96510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency 96610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency 96710352Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 96810409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 96910409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use 97010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 97110409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 97210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. 97310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 97410352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor 9758889Sgeoffrey.blake@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy 97610352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy 9778889Sgeoffrey.blake@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 97810352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 9798983Snate@binkert.orgsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 9808889Sgeoffrey.blake@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 9818889Sgeoffrey.blake@arm.comsystem.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses 98210352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 5932 # Number of data accesses 98310352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 98410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 98510352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 98610352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 98710352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 98810352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 98910352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 99010352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 99110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 99210352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 99310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 99410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2373 # number of overall hits 99510409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 99610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 99710409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 99810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 99910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 100010352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 100110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 100210352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 100310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 100410352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 496 # number of overall misses 100510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles 100610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles 100710409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles 100810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles 100910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 101010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 101110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles 10128889Sgeoffrey.blake@arm.comsystem.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles 10139838Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles 101410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles 101510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 101610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 101710352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 10189838Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 101910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 102010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 102110409Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 102210352Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 102310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 102410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 102510352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 102610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 102710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 102810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 102910352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 103010352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 10319449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 103210352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 103310352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 10349449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 103510352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 103610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 10379449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency 103810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency 103910352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency 104010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency 104110352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 104210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 104310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 104410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency 10459449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency 104610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency 104710352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 10489449SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 104910352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 105010409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 105110409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 105210352Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 105310352Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 105410352Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 105510409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 105610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 105710352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 105810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 105910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 106010352Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 106110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 106210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 106310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 106410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 106510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 106610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 10679449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 106810352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 106910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 10709449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 107110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 107210352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 107310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles 107410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles 10759449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles 10769449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles 107710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles 10789449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles 107910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles 108010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles 10819449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 108210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 108310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 108410409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 108510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 108610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 108710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 108810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 108910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency 109010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency 109110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency 109210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency 109310352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 10949449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 10959449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency 10969449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency 10979449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10989449SAli.Saidi@ARM.com 10999449SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 11009449SAli.Saidi@ARM.com