stats.txt revision 10148
18889Sgeoffrey.blake@arm.com 28889Sgeoffrey.blake@arm.com---------- Begin Simulation Statistics ---------- 39978Sandreas.hansson@arm.comsim_seconds 0.000017 # Number of seconds simulated 410148Sandreas.hansson@arm.comsim_ticks 17056000 # Number of ticks simulated 510148Sandreas.hansson@arm.comfinal_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68889Sgeoffrey.blake@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 710148Sandreas.hansson@arm.comhost_inst_rate 29277 # Simulator instruction rate (inst/s) 810148Sandreas.hansson@arm.comhost_op_rate 36530 # Simulator op (including micro ops) rate (op/s) 910148Sandreas.hansson@arm.comhost_tick_rate 108745688 # Simulator tick rate (ticks/s) 1010148Sandreas.hansson@arm.comhost_mem_usage 308972 # Number of bytes of host memory used 1110148Sandreas.hansson@arm.comhost_seconds 0.16 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 4591 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 5729 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169978Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 179312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 189978Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25088 # Number of bytes read from this memory 199978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory 209978Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory 219978Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory 229312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 239978Sandreas.hansson@arm.comsystem.physmem.num_reads::total 392 # Number of read requests responded to by this memory 2410148Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s) 2510148Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s) 2610148Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s) 2710148Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s) 2810148Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s) 2910148Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s) 3010148Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s) 3110148Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 392 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 25088 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 86 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 46 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 20 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 42 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 17 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 34 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 35 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 10 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 4 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 7 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 28 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 42 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 9 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 6 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 6 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810148Sandreas.hansson@arm.comsystem.physmem.totGap 16998500 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 392 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see 9410148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see 9510148Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 969978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 979797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 989348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 999348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation 19010148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation 19110148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation 19210148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation 19310148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation 19410148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation 19510148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation 19610148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation 19710148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation 19810148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation 19910148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation 20010148Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation 20110148Sandreas.hansson@arm.comsystem.physmem.totQLat 4223500 # Total ticks spent queuing 20210148Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM 2039978Sandreas.hansson@arm.comsystem.physmem.totBusLat 1960000 # Total ticks spent in databus transfers 20410148Sandreas.hansson@arm.comsystem.physmem.totBankLat 5431250 # Total ticks spent accessing banks 20510148Sandreas.hansson@arm.comsystem.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst 20610148Sandreas.hansson@arm.comsystem.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810148Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst 20910148Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110148Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410148Sandreas.hansson@arm.comsystem.physmem.busUtil 11.49 # Data bus utilization in percentage 21510148Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710148Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910148Sandreas.hansson@arm.comsystem.physmem.readRowHits 326 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310148Sandreas.hansson@arm.comsystem.physmem.avgGap 43363.52 # Average gap between requests 22410148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined 2259978Sandreas.hansson@arm.comsystem.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state 22610148Sandreas.hansson@arm.comsystem.membus.throughput 1467166979 # Throughput (bytes/s) 2279978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 351 # Transaction distribution 2289978Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 350 # Transaction distribution 2299729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 41 # Transaction distribution 2309729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 41 # Transaction distribution 2319978Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes) 2329978Sandreas.hansson@arm.comsystem.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes) 2339978Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes) 2349978Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) 2359978Sandreas.hansson@arm.comsystem.membus.data_through_bus 25024 # Total data (bytes) 2369729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 23710148Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 2389978Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 23910148Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks) 24010148Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 21.4 # Layer utilization (%) 24110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2429978Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2481 # Number of BP lookups 2439978Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 2449620Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 2459978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 2469797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 697 # Number of BTB hits 2479481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2489978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 2499797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 2509481Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 25110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 25210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 25310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 25410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 25510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 25610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 25710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 25810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 25910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 26010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 26110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 26210038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 26310038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 26410038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 26510038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 26610038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 26710038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 26810038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 26910038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 27010038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 27110038SAli.Saidi@ARM.comsystem.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2728889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_hits 0 # ITB inst hits 2738889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_misses 0 # ITB inst misses 2748889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_hits 0 # DTB read hits 2758889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_misses 0 # DTB read misses 2768889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_hits 0 # DTB write hits 2778889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_misses 0 # DTB write misses 2788889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2798889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2808889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2818889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2828889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2838889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2848889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2858889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2868889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2878889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.read_accesses 0 # DTB read accesses 2888889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.write_accesses 0 # DTB write accesses 2898889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 2908889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.hits 0 # DTB hits 2918889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.misses 0 # DTB misses 2928889Sgeoffrey.blake@arm.comsystem.cpu.checker.dtb.accesses 0 # DTB accesses 29310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 30410038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30510038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30610038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30710038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30810038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 30910038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31010038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31110038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 31210038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 31310038SAli.Saidi@ARM.comsystem.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3148889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_hits 0 # ITB inst hits 3158889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_misses 0 # ITB inst misses 3168889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_hits 0 # DTB read hits 3178889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_misses 0 # DTB read misses 3188889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_hits 0 # DTB write hits 3198889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_misses 0 # DTB write misses 3208889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 3218889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3228889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3238889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3248889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3258889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3268889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3278889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3288889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3298889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.read_accesses 0 # DTB read accesses 3308889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.write_accesses 0 # DTB write accesses 3318889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 3328889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.hits 0 # DTB hits 3338889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.misses 0 # DTB misses 3348889Sgeoffrey.blake@arm.comsystem.cpu.checker.itb.accesses 0 # DTB accesses 3358889Sgeoffrey.blake@arm.comsystem.cpu.workload.num_syscalls 13 # Number of system calls 3369459Ssaidi@eecs.umich.edusystem.cpu.checker.numCycles 5742 # number of cpu cycles simulated 3378889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 3388889Sgeoffrey.blake@arm.comsystem.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 33910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 35810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 35910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3608889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 3618889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 3628889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 3638889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 3648889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 3658889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 3668889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3678889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3688889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3698889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3708889Sgeoffrey.blake@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3718889Sgeoffrey.blake@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3728889Sgeoffrey.blake@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3738889Sgeoffrey.blake@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3748889Sgeoffrey.blake@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3758889Sgeoffrey.blake@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 3768889Sgeoffrey.blake@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 3778889Sgeoffrey.blake@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3788889Sgeoffrey.blake@arm.comsystem.cpu.dtb.hits 0 # DTB hits 3798889Sgeoffrey.blake@arm.comsystem.cpu.dtb.misses 0 # DTB misses 3808889Sgeoffrey.blake@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 38110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 38210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 39210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 40010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 40110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 4028889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 4038889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 4048889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 4058889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 4068889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 4078889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 4088889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4098889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4108889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4118889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4128889Sgeoffrey.blake@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4138889Sgeoffrey.blake@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4148889Sgeoffrey.blake@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4158889Sgeoffrey.blake@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4168889Sgeoffrey.blake@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4178889Sgeoffrey.blake@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 4188889Sgeoffrey.blake@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 4198889Sgeoffrey.blake@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4208889Sgeoffrey.blake@arm.comsystem.cpu.itb.hits 0 # DTB hits 4218889Sgeoffrey.blake@arm.comsystem.cpu.itb.misses 0 # DTB misses 4228889Sgeoffrey.blake@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42310148Sandreas.hansson@arm.comsystem.cpu.numCycles 34113 # number of cpu cycles simulated 4248889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4258889Sgeoffrey.blake@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42610148Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss 4279978Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 11923 # Number of instructions fetch has processed 4289978Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2481 # Number of branches that fetch encountered 4299797Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken 4309978Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked 4319797Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing 4329978Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked 4339797Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1947 # Number of cache lines fetched 4349978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 43510148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total) 43610148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total) 43710148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total) 4388889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 43910148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total) 44010148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total) 44110148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total) 44210148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total) 44310148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total) 44410148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total) 44510148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total) 4469978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) 4479978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) 4488889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4498889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 4508889Sgeoffrey.blake@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 45110148Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total) 45210148Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle 45310148Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle 45410148Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle 4559978Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked 4569978Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2426 # Number of cycles decode is running 4579978Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 4589797Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing 4599797Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch 4609729Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 4619978Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode 4629348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 4639797Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing 46410148Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle 4659978Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking 4669978Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 4679978Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2227 # Number of cycles rename is running 4689978Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 4699978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 4709729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 4719978Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 4729978Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 4739978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed 47410038SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made 4759978Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 4769924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 4779459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 4789978Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 4799459Ssaidi@eecs.umich.edusystem.cpu.rename.serializingInsts 41 # count of serializing insts renamed 4809459Ssaidi@eecs.umich.edusystem.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 48110148Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 666 # count of insts added to the skid buffer 4829978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 4839978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 4849459Ssaidi@eecs.umich.edusystem.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 4859729Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 4869978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 4879459Ssaidi@eecs.umich.edusystem.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 4889978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 4899978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 4909978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling 49110038SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph 4929459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 49310148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle 49410148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle 49510148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle 4968889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 49710148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle 49810148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle 49910148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle 50010148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle 50110148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle 50210148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle 5039978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle 5049978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle 5059729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle 5068889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5078889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5088889Sgeoffrey.blake@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 50910148Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle 5108889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 5119978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available 5129978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available 5139978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available 5149978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available 5159978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available 5169978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available 5179978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available 5189978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available 5199978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 5209978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available 5219978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available 5229978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available 5239978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available 5249978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available 5259978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available 5269978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available 5279978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available 5289978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available 5299978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available 5309978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available 5319978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available 5329978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available 5339978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available 5349978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available 5359978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available 5369978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available 5379978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available 5389978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available 5399978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available 5409978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available 5419978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available 5428889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5438889Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5448889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 5459978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued 5469978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued 5479978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued 5489978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued 5499978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued 5509978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued 5519978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued 5529978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued 5539978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued 5549978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued 5559978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued 5569978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued 5579978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued 5589978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued 5599978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued 5609978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued 5619978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued 5629978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued 5639978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued 5649978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued 5659978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued 5669978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued 5679978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued 5689978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued 5699978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued 5709978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued 5719978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued 5729978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued 5739978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued 5749978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued 5759978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued 5768889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5778889Sgeoffrey.blake@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 5789978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8921 # Type of FU issued 57910148Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.261513 # Inst issue rate 5809978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 224 # FU busy when requested 5819978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) 58210148Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads 5839978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes 5849978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses 5858889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 5869322Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 5878889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 5889978Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses 5898889Sgeoffrey.blake@arm.comsystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 5909729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 5918889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 5929978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed 5939312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 5949729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 5959978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed 5968889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5978889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 5988889Sgeoffrey.blake@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 5999348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 6008889Sgeoffrey.blake@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 6019797Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing 6029797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking 6039978Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 6049978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ 6059978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch 6069978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 6079978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions 6089459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 6099978Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 6109285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 6119729Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 6129620Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly 6139797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly 6149797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute 6159978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions 6169978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed 6179978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 6188889Sgeoffrey.blake@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 6199348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 6209978Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3299 # number of memory reference insts executed 6219797Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1437 # Number of branches executed 6229729Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1160 # Number of stores executed 62310148Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.249846 # Inst execution rate 6249978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit 6259978Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 8068 # cumulative count of insts written-back 6269978Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 3883 # num instructions producing a value 6279978Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7788 # num instructions consuming a value 6288889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 62910148Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.236508 # insts written-back per cycle 6309978Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back 6318889Sgeoffrey.blake@arm.comsystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 6329978Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit 6339459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 6349620Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted 63510148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle 63610148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle 63710148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle 6388889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 63910148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle 64010148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle 64110148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle 64210148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle 64310148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle 6449978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle 6459978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 64610148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle 64710148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle 6488889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6498889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6508889Sgeoffrey.blake@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 65110148Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle 6529459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 4591 # Number of instructions committed 6539459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 6548889Sgeoffrey.blake@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 6559459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 2138 # Number of memory references committed 6569459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 1200 # Number of loads committed 6578889Sgeoffrey.blake@arm.comsystem.cpu.commit.membars 12 # Number of memory barriers committed 6589459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 1007 # Number of branches committed 6598889Sgeoffrey.blake@arm.comsystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 6609459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 4976 # Number of committed integer instructions. 6618889Sgeoffrey.blake@arm.comsystem.cpu.commit.function_calls 82 # Number of function calls committed. 6629978Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached 6638889Sgeoffrey.blake@arm.comsystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 66410148Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 23225 # The number of ROB reads 6659978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 23415 # The number of ROB writes 66610148Sandreas.hansson@arm.comsystem.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself 66710148Sandreas.hansson@arm.comsystem.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling 6689459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 4591 # Number of Instructions Simulated 6699459Ssaidi@eecs.umich.edusystem.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 6709459Ssaidi@eecs.umich.edusystem.cpu.committedInsts_total 4591 # Number of Instructions Simulated 67110148Sandreas.hansson@arm.comsystem.cpu.cpi 7.430407 # CPI: Cycles Per Instruction 67210148Sandreas.hansson@arm.comsystem.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads 67310148Sandreas.hansson@arm.comsystem.cpu.ipc 0.134582 # IPC: Instructions Per Cycle 67410148Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads 6759978Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 39210 # number of integer regfile reads 6769978Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7985 # number of integer regfile writes 6778889Sgeoffrey.blake@arm.comsystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 67810038SAli.Saidi@ARM.comsystem.cpu.misc_regfile_reads 3239 # number of misc regfile reads 6799459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 24 # number of misc regfile writes 68010148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s) 6819978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 6829978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 6839729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 6849729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 6859978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 6869838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 6879978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes) 6889978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes) 6899838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 6909978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes) 6919978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes) 6929729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 6939978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) 6949729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 69510148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) 6969978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 69710148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks) 69810148Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 6999838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 4 # number of replacements 70010148Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use 7019978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. 7029978Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. 7039978Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. 7049838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70510148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor 70610148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy 70710148Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy 70810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id 70910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 71010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id 71110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id 71210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses 71310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 4184 # Number of data accesses 7149978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits 7159978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits 7169978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits 7179978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits 7189978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits 7199978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1584 # number of overall hits 7209978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses 7219978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses 7229978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 7239978Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses 7249978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses 7259978Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 363 # number of overall misses 72610148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles 72710148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles 72810148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles 72910148Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles 73010148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles 73110148Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles 7329797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) 7339797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) 7349797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses 7359797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses 7369797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses 7379797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses 7389978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses 7399978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses 7409978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses 7419978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses 7429978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses 7439978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses 74410148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency 74510148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency 74610148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency 74710148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency 74810148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency 74910148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency 7509978Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked 7518889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7529978Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 7538889Sgeoffrey.blake@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 7549978Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked 7558983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7568889Sgeoffrey.blake@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 7578889Sgeoffrey.blake@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 7589729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 7599729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 7609729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 7619729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 7629729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 7639729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits 7649978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses 7659978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses 7669978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses 7679978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses 7689978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 7699978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses 77010148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles 77110148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles 77210148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles 77310148Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles 77410148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles 77510148Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles 7769978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses 7779978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses 7789978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses 7799978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses 7809978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses 7819978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses 78210148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency 78310148Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency 78410148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency 78510148Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency 78610148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency 78710148Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency 7888889Sgeoffrey.blake@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7899838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 79010148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use 7919838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 7929978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. 7939978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. 7949838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79510148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor 79610148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor 79710148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy 79810148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy 79910148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy 80010036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id 80110148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 80210148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 80310036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id 80410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses 80510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses 8069729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 8079449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 8089729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 8099729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 8109449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 8119729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 8129729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 8139449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 8149729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 40 # number of overall hits 8159978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses 8169449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 8179978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 8189449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 8199449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 8209978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses 8219449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 8229978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses 8239978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses 8249449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 8259978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 397 # number of overall misses 82610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles 82710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles 82810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles 82910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles 83010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles 83110148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles 83210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles 83310148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles 83410148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles 83510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles 83610148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles 8379978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) 8389449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 8399978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) 8409449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 8419449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 8429978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses 8439449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 8449978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses 8459978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses 8469449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 8479978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses 8489978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses 8499449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 8509978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses 8519449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8529449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 8539978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses 8549449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 8559978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses 8569978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses 8579449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 8589978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses 85910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency 86010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency 86110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency 86210148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency 86310148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency 86410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency 86510148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency 86610148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency 86710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency 86810148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency 86910148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency 8709449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8719449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8729449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8739449SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8749449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8759449SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8769449SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8779449SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 8789449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 8799449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 8809449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 8819449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 8829449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 8839449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 8849978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses 8859449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 8869978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 8879449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 8889449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 8899978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses 8909449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 8919978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses 8929978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses 8939449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 8949978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses 89510148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles 89610148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles 89710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles 89810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles 89910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles 90010148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles 90110148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles 90210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles 90310148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles 90410148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles 90510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles 9069978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses 9079449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 9089978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses 9099449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9109449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 9119978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses 9129449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 9139978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses 9149978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses 9159449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 9169978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses 91710148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency 91810148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency 91910148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency 92010148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency 92110148Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency 92210148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency 92310148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency 92410148Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency 92510148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency 92610148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency 92710148Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency 9289449SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 9299838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 93010148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use 9319978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. 9329838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 9339978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. 9349838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93510148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor 93610148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy 93710148Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy 93810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 93910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 94010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 94110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 94210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses 94310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 5930 # Number of data accesses 9449978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 9459978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 9469348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 9479348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 9489797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 9499797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 9509459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 9519459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 9529978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 9539978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 9549978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 9559978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2373 # number of overall hits 9569978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses 9579978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses 9589348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 9599348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 9608889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 9618889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 9629978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses 9639978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses 9649978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses 9659978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 496 # number of overall misses 96610148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles 96710148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles 96810148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles 96910148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles 9709797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 9719797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 97210148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles 97310148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles 97410148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles 97510148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles 9769978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 9779978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 9788889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 9798889Sgeoffrey.blake@arm.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 9809797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 9819797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 9829459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 9839459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 9849978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 9859978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 9869978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 9879978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 9889978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses 9899978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses 9909348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 9919348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 9929797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 9939797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 9949978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses 9959978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses 9969978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses 9979978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses 99810148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency 99910148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency 100010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency 100110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency 10029797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency 10039797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency 100410148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency 100510148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency 100610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency 100710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency 10089797Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked 10098889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10109348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 10118889Sgeoffrey.blake@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 10129797Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked 10138983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10148889Sgeoffrey.blake@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 10158889Sgeoffrey.blake@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 10169978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits 10179978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 10189348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 10199348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 10208889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 10218889Sgeoffrey.blake@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 10229978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits 10239978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits 10249978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits 10259978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits 10269322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 10279322Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 10289348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 10299348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 10309348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 10319348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 10329348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 10339348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 103410148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles 103510148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles 103610148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles 103710148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles 103810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles 103910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles 104010148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles 104110148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles 10429978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 10439978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 10449348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 10459348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 10469978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 10479978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 10489978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 10499978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 105010148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency 105110148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency 105210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency 105310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency 105410148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency 105510148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency 105610148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency 105710148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency 10588889Sgeoffrey.blake@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 10598889Sgeoffrey.blake@arm.com 10608889Sgeoffrey.blake@arm.com---------- End Simulation Statistics ---------- 1061