config.ini revision 9510:921d858c5bc7
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=timing 18mem_ranges= 19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39SQEntries=32 40SSITSize=1024 41activity=0 42backComSize=5 43branchPred=system.cpu.branchPred 44cachePorts=200 45checker=system.cpu.checker 46clock=500 47commitToDecodeDelay=1 48commitToFetchDelay=1 49commitToIEWDelay=1 50commitToRenameDelay=1 51commitWidth=8 52cpu_id=0 53decodeToFetchDelay=1 54decodeToRenameDelay=1 55decodeWidth=8 56dispatchWidth=8 57do_checkpoint_insts=true 58do_quiesce=true 59do_statistics_insts=true 60dtb=system.cpu.dtb 61fetchToDecodeDelay=1 62fetchTrapLatency=1 63fetchWidth=8 64forwardComSize=5 65fuPool=system.cpu.fuPool 66function_trace=false 67function_trace_start=0 68iewToCommitDelay=1 69iewToDecodeDelay=1 70iewToFetchDelay=1 71iewToRenameDelay=1 72interrupts=system.cpu.interrupts 73isa=system.cpu.isa 74issueToExecuteDelay=1 75issueWidth=8 76itb=system.cpu.itb 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81needsTSO=false 82numIQEntries=64 83numPhysFloatRegs=256 84numPhysIntRegs=256 85numROBEntries=192 86numRobs=1 87numThreads=1 88profile=0 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105store_set_clear_period=250000 106switched_out=false 107system=system 108tracer=system.cpu.tracer 109trapLatency=13 110wbDepth=1 111wbWidth=8 112workload=system.cpu.workload 113dcache_port=system.cpu.dcache.cpu_side 114icache_port=system.cpu.icache.cpu_side 115 116[system.cpu.branchPred] 117type=BranchPredictor 118BTBEntries=4096 119BTBTagSize=16 120RASSize=16 121choiceCtrBits=2 122choicePredictorSize=8192 123globalCtrBits=2 124globalHistoryBits=13 125globalPredictorSize=8192 126instShiftAmt=2 127localCtrBits=2 128localHistoryBits=11 129localHistoryTableSize=2048 130localPredictorSize=2048 131numThreads=1 132predType=tournament 133 134[system.cpu.checker] 135type=O3Checker 136children=dtb isa itb tracer 137branchPred=Null 138checker=Null 139clock=500 140cpu_id=0 141do_checkpoint_insts=true 142do_quiesce=true 143do_statistics_insts=true 144dtb=system.cpu.checker.dtb 145exitOnError=false 146function_trace=false 147function_trace_start=0 148interrupts=Null 149isa=system.cpu.checker.isa 150itb=system.cpu.checker.itb 151max_insts_all_threads=0 152max_insts_any_thread=0 153max_loads_all_threads=0 154max_loads_any_thread=0 155numThreads=1 156profile=0 157progress_interval=0 158switched_out=false 159system=system 160tracer=system.cpu.checker.tracer 161updateOnError=true 162warnOnlyOnLoadError=true 163workload=system.cpu.workload 164 165[system.cpu.checker.dtb] 166type=ArmTLB 167children=walker 168size=64 169walker=system.cpu.checker.dtb.walker 170 171[system.cpu.checker.dtb.walker] 172type=ArmTableWalker 173clock=500 174num_squash_per_cycle=2 175sys=system 176port=system.cpu.toL2Bus.slave[5] 177 178[system.cpu.checker.isa] 179type=ArmISA 180fpsid=1090793632 181id_isar0=34607377 182id_isar1=34677009 183id_isar2=555950401 184id_isar3=17899825 185id_isar4=268501314 186id_isar5=0 187id_mmfr0=3 188id_mmfr1=0 189id_mmfr2=19070976 190id_mmfr3=4027589137 191id_pfr0=49 192id_pfr1=1 193midr=890224640 194 195[system.cpu.checker.itb] 196type=ArmTLB 197children=walker 198size=64 199walker=system.cpu.checker.itb.walker 200 201[system.cpu.checker.itb.walker] 202type=ArmTableWalker 203clock=500 204num_squash_per_cycle=2 205sys=system 206port=system.cpu.toL2Bus.slave[4] 207 208[system.cpu.checker.tracer] 209type=ExeTracer 210 211[system.cpu.dcache] 212type=BaseCache 213addr_ranges=0:18446744073709551615 214assoc=2 215block_size=64 216clock=500 217forward_snoops=true 218hit_latency=2 219is_top_level=true 220max_miss_count=0 221mshrs=4 222prefetch_on_access=false 223prefetcher=Null 224response_latency=2 225size=262144 226system=system 227tgts_per_mshr=20 228two_queue=false 229write_buffers=8 230cpu_side=system.cpu.dcache_port 231mem_side=system.cpu.toL2Bus.slave[1] 232 233[system.cpu.dtb] 234type=ArmTLB 235children=walker 236size=64 237walker=system.cpu.dtb.walker 238 239[system.cpu.dtb.walker] 240type=ArmTableWalker 241clock=500 242num_squash_per_cycle=2 243sys=system 244port=system.cpu.toL2Bus.slave[3] 245 246[system.cpu.fuPool] 247type=FUPool 248children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 249FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 250 251[system.cpu.fuPool.FUList0] 252type=FUDesc 253children=opList 254count=6 255opList=system.cpu.fuPool.FUList0.opList 256 257[system.cpu.fuPool.FUList0.opList] 258type=OpDesc 259issueLat=1 260opClass=IntAlu 261opLat=1 262 263[system.cpu.fuPool.FUList1] 264type=FUDesc 265children=opList0 opList1 266count=2 267opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 268 269[system.cpu.fuPool.FUList1.opList0] 270type=OpDesc 271issueLat=1 272opClass=IntMult 273opLat=3 274 275[system.cpu.fuPool.FUList1.opList1] 276type=OpDesc 277issueLat=19 278opClass=IntDiv 279opLat=20 280 281[system.cpu.fuPool.FUList2] 282type=FUDesc 283children=opList0 opList1 opList2 284count=4 285opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 286 287[system.cpu.fuPool.FUList2.opList0] 288type=OpDesc 289issueLat=1 290opClass=FloatAdd 291opLat=2 292 293[system.cpu.fuPool.FUList2.opList1] 294type=OpDesc 295issueLat=1 296opClass=FloatCmp 297opLat=2 298 299[system.cpu.fuPool.FUList2.opList2] 300type=OpDesc 301issueLat=1 302opClass=FloatCvt 303opLat=2 304 305[system.cpu.fuPool.FUList3] 306type=FUDesc 307children=opList0 opList1 opList2 308count=2 309opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 310 311[system.cpu.fuPool.FUList3.opList0] 312type=OpDesc 313issueLat=1 314opClass=FloatMult 315opLat=4 316 317[system.cpu.fuPool.FUList3.opList1] 318type=OpDesc 319issueLat=12 320opClass=FloatDiv 321opLat=12 322 323[system.cpu.fuPool.FUList3.opList2] 324type=OpDesc 325issueLat=24 326opClass=FloatSqrt 327opLat=24 328 329[system.cpu.fuPool.FUList4] 330type=FUDesc 331children=opList 332count=0 333opList=system.cpu.fuPool.FUList4.opList 334 335[system.cpu.fuPool.FUList4.opList] 336type=OpDesc 337issueLat=1 338opClass=MemRead 339opLat=1 340 341[system.cpu.fuPool.FUList5] 342type=FUDesc 343children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 344count=4 345opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 346 347[system.cpu.fuPool.FUList5.opList00] 348type=OpDesc 349issueLat=1 350opClass=SimdAdd 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList01] 354type=OpDesc 355issueLat=1 356opClass=SimdAddAcc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList02] 360type=OpDesc 361issueLat=1 362opClass=SimdAlu 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList03] 366type=OpDesc 367issueLat=1 368opClass=SimdCmp 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList04] 372type=OpDesc 373issueLat=1 374opClass=SimdCvt 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList05] 378type=OpDesc 379issueLat=1 380opClass=SimdMisc 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList06] 384type=OpDesc 385issueLat=1 386opClass=SimdMult 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList07] 390type=OpDesc 391issueLat=1 392opClass=SimdMultAcc 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList08] 396type=OpDesc 397issueLat=1 398opClass=SimdShift 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList09] 402type=OpDesc 403issueLat=1 404opClass=SimdShiftAcc 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList10] 408type=OpDesc 409issueLat=1 410opClass=SimdSqrt 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList11] 414type=OpDesc 415issueLat=1 416opClass=SimdFloatAdd 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList12] 420type=OpDesc 421issueLat=1 422opClass=SimdFloatAlu 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList13] 426type=OpDesc 427issueLat=1 428opClass=SimdFloatCmp 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList14] 432type=OpDesc 433issueLat=1 434opClass=SimdFloatCvt 435opLat=1 436 437[system.cpu.fuPool.FUList5.opList15] 438type=OpDesc 439issueLat=1 440opClass=SimdFloatDiv 441opLat=1 442 443[system.cpu.fuPool.FUList5.opList16] 444type=OpDesc 445issueLat=1 446opClass=SimdFloatMisc 447opLat=1 448 449[system.cpu.fuPool.FUList5.opList17] 450type=OpDesc 451issueLat=1 452opClass=SimdFloatMult 453opLat=1 454 455[system.cpu.fuPool.FUList5.opList18] 456type=OpDesc 457issueLat=1 458opClass=SimdFloatMultAcc 459opLat=1 460 461[system.cpu.fuPool.FUList5.opList19] 462type=OpDesc 463issueLat=1 464opClass=SimdFloatSqrt 465opLat=1 466 467[system.cpu.fuPool.FUList6] 468type=FUDesc 469children=opList 470count=0 471opList=system.cpu.fuPool.FUList6.opList 472 473[system.cpu.fuPool.FUList6.opList] 474type=OpDesc 475issueLat=1 476opClass=MemWrite 477opLat=1 478 479[system.cpu.fuPool.FUList7] 480type=FUDesc 481children=opList0 opList1 482count=4 483opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 484 485[system.cpu.fuPool.FUList7.opList0] 486type=OpDesc 487issueLat=1 488opClass=MemRead 489opLat=1 490 491[system.cpu.fuPool.FUList7.opList1] 492type=OpDesc 493issueLat=1 494opClass=MemWrite 495opLat=1 496 497[system.cpu.fuPool.FUList8] 498type=FUDesc 499children=opList 500count=1 501opList=system.cpu.fuPool.FUList8.opList 502 503[system.cpu.fuPool.FUList8.opList] 504type=OpDesc 505issueLat=3 506opClass=IprAccess 507opLat=3 508 509[system.cpu.icache] 510type=BaseCache 511addr_ranges=0:18446744073709551615 512assoc=2 513block_size=64 514clock=500 515forward_snoops=true 516hit_latency=2 517is_top_level=true 518max_miss_count=0 519mshrs=4 520prefetch_on_access=false 521prefetcher=Null 522response_latency=2 523size=131072 524system=system 525tgts_per_mshr=20 526two_queue=false 527write_buffers=8 528cpu_side=system.cpu.icache_port 529mem_side=system.cpu.toL2Bus.slave[0] 530 531[system.cpu.interrupts] 532type=ArmInterrupts 533 534[system.cpu.isa] 535type=ArmISA 536fpsid=1090793632 537id_isar0=34607377 538id_isar1=34677009 539id_isar2=555950401 540id_isar3=17899825 541id_isar4=268501314 542id_isar5=0 543id_mmfr0=3 544id_mmfr1=0 545id_mmfr2=19070976 546id_mmfr3=4027589137 547id_pfr0=49 548id_pfr1=1 549midr=890224640 550 551[system.cpu.itb] 552type=ArmTLB 553children=walker 554size=64 555walker=system.cpu.itb.walker 556 557[system.cpu.itb.walker] 558type=ArmTableWalker 559clock=500 560num_squash_per_cycle=2 561sys=system 562port=system.cpu.toL2Bus.slave[2] 563 564[system.cpu.l2cache] 565type=BaseCache 566addr_ranges=0:18446744073709551615 567assoc=8 568block_size=64 569clock=500 570forward_snoops=true 571hit_latency=20 572is_top_level=false 573max_miss_count=0 574mshrs=20 575prefetch_on_access=false 576prefetcher=Null 577response_latency=20 578size=2097152 579system=system 580tgts_per_mshr=12 581two_queue=false 582write_buffers=8 583cpu_side=system.cpu.toL2Bus.master[0] 584mem_side=system.membus.slave[1] 585 586[system.cpu.toL2Bus] 587type=CoherentBus 588block_size=64 589clock=500 590header_cycles=1 591use_default_range=false 592width=32 593master=system.cpu.l2cache.cpu_side 594slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 595 596[system.cpu.tracer] 597type=ExeTracer 598 599[system.cpu.workload] 600type=LiveProcess 601cmd=hello 602cwd= 603egid=100 604env= 605errout=cerr 606euid=100 607executable=tests/test-progs/hello/bin/arm/linux/hello 608gid=100 609input=cin 610max_stack_size=67108864 611output=cout 612pid=100 613ppid=99 614simpoint=0 615system=system 616uid=100 617 618[system.membus] 619type=CoherentBus 620block_size=64 621clock=1000 622header_cycles=1 623use_default_range=false 624width=8 625master=system.physmem.port 626slave=system.system_port system.cpu.l2cache.mem_side 627 628[system.physmem] 629type=SimpleDRAM 630activation_limit=4 631addr_mapping=openmap 632banks_per_rank=8 633clock=1000 634conf_table_reported=false 635in_addr_map=true 636lines_per_rowbuffer=32 637mem_sched_policy=frfcfs 638null=false 639page_policy=open 640range=0:134217727 641ranks_per_channel=2 642read_buffer_size=32 643tBURST=5000 644tCL=13750 645tRCD=13750 646tREFI=7800000 647tRFC=300000 648tRP=13750 649tWTR=7500 650tXAW=40000 651write_buffer_size=32 652write_thresh_perc=70 653zero=false 654port=system.membus.master[0] 655 656