stats.txt revision 9729
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 32544000 # Number of ticks simulated 5final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 19861 # Simulator instruction rate (inst/s) 8host_op_rate 19860 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 101141711 # Simulator tick rate (ticks/s) 10host_mem_usage 224276 # Number of bytes of host memory used 11host_seconds 0.32 # Real time elapsed on the host 12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 877089479 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 373 # Transaction distribution 32system.membus.trans_dist::ReadResp 373 # Transaction distribution 33system.membus.trans_dist::ReadExReq 73 # Transaction distribution 34system.membus.trans_dist::ReadExResp 73 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count 892 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 28544 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 43system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 12.3 # Layer utilization (%) 45system.cpu.dtb.fetch_hits 0 # ITB hits 46system.cpu.dtb.fetch_misses 0 # ITB misses 47system.cpu.dtb.fetch_acv 0 # ITB acv 48system.cpu.dtb.fetch_accesses 0 # ITB accesses 49system.cpu.dtb.read_hits 1183 # DTB read hits 50system.cpu.dtb.read_misses 7 # DTB read misses 51system.cpu.dtb.read_acv 0 # DTB read access violations 52system.cpu.dtb.read_accesses 1190 # DTB read accesses 53system.cpu.dtb.write_hits 865 # DTB write hits 54system.cpu.dtb.write_misses 3 # DTB write misses 55system.cpu.dtb.write_acv 0 # DTB write access violations 56system.cpu.dtb.write_accesses 868 # DTB write accesses 57system.cpu.dtb.data_hits 2048 # DTB hits 58system.cpu.dtb.data_misses 10 # DTB misses 59system.cpu.dtb.data_acv 0 # DTB access violations 60system.cpu.dtb.data_accesses 2058 # DTB accesses 61system.cpu.itb.fetch_hits 6401 # ITB hits 62system.cpu.itb.fetch_misses 17 # ITB misses 63system.cpu.itb.fetch_acv 0 # ITB acv 64system.cpu.itb.fetch_accesses 6418 # ITB accesses 65system.cpu.itb.read_hits 0 # DTB read hits 66system.cpu.itb.read_misses 0 # DTB read misses 67system.cpu.itb.read_acv 0 # DTB read access violations 68system.cpu.itb.read_accesses 0 # DTB read accesses 69system.cpu.itb.write_hits 0 # DTB write hits 70system.cpu.itb.write_misses 0 # DTB write misses 71system.cpu.itb.write_acv 0 # DTB write access violations 72system.cpu.itb.write_accesses 0 # DTB write accesses 73system.cpu.itb.data_hits 0 # DTB hits 74system.cpu.itb.data_misses 0 # DTB misses 75system.cpu.itb.data_acv 0 # DTB access violations 76system.cpu.itb.data_accesses 0 # DTB accesses 77system.cpu.workload.num_syscalls 17 # Number of system calls 78system.cpu.numCycles 65088 # number of cpu cycles simulated 79system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 80system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 81system.cpu.committedInsts 6390 # Number of instructions committed 82system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 83system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 84system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 85system.cpu.num_func_calls 251 # number of times a function call or return occured 86system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 87system.cpu.num_int_insts 6317 # number of integer instructions 88system.cpu.num_fp_insts 10 # number of float instructions 89system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 90system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 91system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 92system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 93system.cpu.num_mem_refs 2058 # number of memory refs 94system.cpu.num_load_insts 1190 # Number of load instructions 95system.cpu.num_store_insts 868 # Number of store instructions 96system.cpu.num_idle_cycles 0 # Number of idle cycles 97system.cpu.num_busy_cycles 65088 # Number of busy cycles 98system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 99system.cpu.idle_fraction 0 # Percentage of idle cycles 100system.cpu.icache.replacements 0 # number of replacements 101system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use 102system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. 103system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 104system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. 105system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 106system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor 107system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy 108system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy 109system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 110system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 111system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 112system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 113system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 114system.cpu.icache.overall_hits::total 6122 # number of overall hits 115system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 116system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 117system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 118system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 119system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 120system.cpu.icache.overall_misses::total 279 # number of overall misses 121system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles 122system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles 123system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles 124system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles 125system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles 126system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles 127system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 128system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 129system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 130system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 131system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 132system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 133system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 134system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 135system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 136system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 137system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 138system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 139system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency 140system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency 141system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 142system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency 143system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 144system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency 145system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 146system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 147system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 148system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 149system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 150system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 151system.cpu.icache.fast_writes 0 # number of fast writes performed 152system.cpu.icache.cache_copies 0 # number of cache copies performed 153system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 154system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 155system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 156system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 157system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 158system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 159system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 160system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 161system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 162system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 163system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 164system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 165system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 166system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 167system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 168system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 169system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 170system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 171system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 172system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 173system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 174system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 175system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 176system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 177system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 178system.cpu.l2cache.replacements 0 # number of replacements 179system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use 180system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 181system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 182system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 183system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 184system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor 185system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor 186system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 187system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 188system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy 189system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 190system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 191system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 192system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 193system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 194system.cpu.l2cache.overall_hits::total 1 # number of overall hits 195system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 196system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 197system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 198system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 199system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 200system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 201system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 202system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 203system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 204system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 205system.cpu.l2cache.overall_misses::total 446 # number of overall misses 206system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 207system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 208system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 209system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 210system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 211system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 212system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 213system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 214system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 215system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 216system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 217system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 218system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 219system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 220system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 221system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 222system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 223system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 224system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 225system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 226system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 227system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 228system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 229system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 230system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 231system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 232system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 233system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 234system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 235system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 236system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 237system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 238system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 239system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 240system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 241system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 242system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 243system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 244system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 245system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 246system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 247system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 248system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 249system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 250system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 251system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 253system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 254system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 255system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 256system.cpu.l2cache.fast_writes 0 # number of fast writes performed 257system.cpu.l2cache.cache_copies 0 # number of cache copies performed 258system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 259system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 260system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 261system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 262system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 263system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 264system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 265system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 266system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 267system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 268system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 269system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 270system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 271system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 272system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 273system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 274system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 275system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 276system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 277system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 278system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 279system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 280system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 281system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 282system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 283system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 284system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 285system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 286system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 287system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 288system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 289system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 290system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 291system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 292system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 293system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 294system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 295system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 296system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 297system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 298system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 299system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 301system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 302system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 303system.cpu.dcache.replacements 0 # number of replacements 304system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use 305system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. 306system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 307system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. 308system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 309system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor 310system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 311system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy 312system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 313system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 314system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 315system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 316system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 317system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 318system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 319system.cpu.dcache.overall_hits::total 1880 # number of overall hits 320system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 321system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 322system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 323system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 324system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 325system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 326system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 327system.cpu.dcache.overall_misses::total 168 # number of overall misses 328system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 329system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 330system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 331system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 332system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 333system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 334system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 335system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 336system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 337system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 338system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 339system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 340system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 341system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 342system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 343system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 344system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 345system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 346system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 347system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 348system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 349system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 350system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 351system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 352system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 353system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 354system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 355system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 356system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 357system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 358system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 359system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 360system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.dcache.fast_writes 0 # number of fast writes performed 367system.cpu.dcache.cache_copies 0 # number of cache copies performed 368system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 369system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 370system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 371system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 372system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 373system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 374system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 375system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 376system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 377system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 378system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 379system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 380system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 381system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 382system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 383system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 384system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 385system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 386system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 387system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 388system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 389system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 390system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 391system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 392system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 393system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 394system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 395system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 396system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 397system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 398system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 399system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 400system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 401system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s) 402system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution 403system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 404system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 405system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 406system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes) 407system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes) 408system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes) 409system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes) 410system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes) 411system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes) 412system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) 413system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 414system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 415system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 416system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 417system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 418system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 419system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 420 421---------- End Simulation Statistics ---------- 422