stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33007000 # Number of ticks simulated 5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 110064 # Simulator instruction rate (inst/s) 8host_tick_rate 566999999 # Simulator tick rate (ticks/s) 9host_mem_usage 206896 # Number of bytes of host memory used 10host_seconds 0.06 # Real time elapsed on the host 11sim_insts 6404 # Number of instructions simulated 12system.physmem.bytes_read 28544 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 446 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.dtb.fetch_hits 0 # ITB hits 22system.cpu.dtb.fetch_misses 0 # ITB misses 23system.cpu.dtb.fetch_acv 0 # ITB acv 24system.cpu.dtb.fetch_accesses 0 # ITB accesses 25system.cpu.dtb.read_hits 1185 # DTB read hits 26system.cpu.dtb.read_misses 7 # DTB read misses 27system.cpu.dtb.read_acv 0 # DTB read access violations 28system.cpu.dtb.read_accesses 1192 # DTB read accesses 29system.cpu.dtb.write_hits 865 # DTB write hits 30system.cpu.dtb.write_misses 3 # DTB write misses 31system.cpu.dtb.write_acv 0 # DTB write access violations 32system.cpu.dtb.write_accesses 868 # DTB write accesses 33system.cpu.dtb.data_hits 2050 # DTB hits 34system.cpu.dtb.data_misses 10 # DTB misses 35system.cpu.dtb.data_acv 0 # DTB access violations 36system.cpu.dtb.data_accesses 2060 # DTB accesses 37system.cpu.itb.fetch_hits 6415 # ITB hits 38system.cpu.itb.fetch_misses 17 # ITB misses 39system.cpu.itb.fetch_acv 0 # ITB acv 40system.cpu.itb.fetch_accesses 6432 # ITB accesses 41system.cpu.itb.read_hits 0 # DTB read hits 42system.cpu.itb.read_misses 0 # DTB read misses 43system.cpu.itb.read_acv 0 # DTB read access violations 44system.cpu.itb.read_accesses 0 # DTB read accesses 45system.cpu.itb.write_hits 0 # DTB write hits 46system.cpu.itb.write_misses 0 # DTB write misses 47system.cpu.itb.write_acv 0 # DTB write access violations 48system.cpu.itb.write_accesses 0 # DTB write accesses 49system.cpu.itb.data_hits 0 # DTB hits 50system.cpu.itb.data_misses 0 # DTB misses 51system.cpu.itb.data_acv 0 # DTB access violations 52system.cpu.itb.data_accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 17 # Number of system calls 54system.cpu.numCycles 66014 # number of cpu cycles simulated 55system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57system.cpu.num_insts 6404 # Number of instructions executed 58system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses 59system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 60system.cpu.num_func_calls 251 # number of times a function call or return occured 61system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls 62system.cpu.num_int_insts 6331 # number of integer instructions 63system.cpu.num_fp_insts 10 # number of float instructions 64system.cpu.num_int_register_reads 8304 # number of times the integer registers were read 65system.cpu.num_int_register_writes 4581 # number of times the integer registers were written 66system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 67system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 68system.cpu.num_mem_refs 2060 # number of memory refs 69system.cpu.num_load_insts 1192 # Number of load instructions 70system.cpu.num_store_insts 868 # Number of store instructions 71system.cpu.num_idle_cycles 0 # Number of idle cycles 72system.cpu.num_busy_cycles 66014 # Number of busy cycles 73system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 74system.cpu.idle_fraction 0 # Percentage of idle cycles 75system.cpu.icache.replacements 0 # number of replacements 76system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use 77system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. 78system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 79system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. 80system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 81system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context 82system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy 83system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits 84system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits 85system.cpu.icache.overall_hits 6136 # number of overall hits 86system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses 87system.cpu.icache.demand_misses 279 # number of demand (read+write) misses 88system.cpu.icache.overall_misses 279 # number of overall misses 89system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles 90system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles 91system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles 92system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) 93system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses 94system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses 95system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses 96system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses 97system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses 98system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency 99system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency 100system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency 101system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 102system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 104system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 105system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 106system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 107system.cpu.icache.fast_writes 0 # number of fast writes performed 108system.cpu.icache.cache_copies 0 # number of cache copies performed 109system.cpu.icache.writebacks 0 # number of writebacks 110system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 111system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 112system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses 113system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses 114system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses 115system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 116system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles 117system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles 118system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles 119system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 120system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses 121system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses 122system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses 123system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency 124system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency 125system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency 126system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 127system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 128system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 129system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 130system.cpu.dcache.replacements 0 # number of replacements 131system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use 132system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. 133system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 134system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. 135system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 136system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context 137system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy 138system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits 139system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits 140system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits 141system.cpu.dcache.overall_hits 1882 # number of overall hits 142system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses 143system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses 144system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses 145system.cpu.dcache.overall_misses 168 # number of overall misses 146system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles 147system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles 148system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles 149system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles 150system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) 151system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) 152system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses 153system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses 154system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses 155system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses 158system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 159system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 160system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 161system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 167system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 168system.cpu.dcache.fast_writes 0 # number of fast writes performed 169system.cpu.dcache.cache_copies 0 # number of cache copies performed 170system.cpu.dcache.writebacks 0 # number of writebacks 171system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 172system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 173system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses 175system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses 176system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses 177system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 178system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles 179system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles 180system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles 181system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles 182system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 183system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses 184system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses 185system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses 186system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses 187system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 188system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 189system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 190system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 191system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 192system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 193system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 194system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 195system.cpu.l2cache.replacements 0 # number of replacements 196system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use 197system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 198system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 199system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 200system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 201system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context 202system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy 203system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 204system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 205system.cpu.l2cache.overall_hits 1 # number of overall hits 206system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses 207system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 208system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses 209system.cpu.l2cache.overall_misses 446 # number of overall misses 210system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles 211system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles 212system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles 213system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles 214system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) 215system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 216system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses 217system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses 218system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses 219system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 220system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses 221system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses 222system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 223system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 224system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 225system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 226system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 227system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 228system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 229system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 230system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 231system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 232system.cpu.l2cache.fast_writes 0 # number of fast writes performed 233system.cpu.l2cache.cache_copies 0 # number of cache copies performed 234system.cpu.l2cache.writebacks 0 # number of writebacks 235system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 236system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 237system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses 238system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 239system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses 240system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses 241system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 242system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles 243system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles 244system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles 245system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles 246system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 247system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses 248system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 249system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses 250system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses 251system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 252system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 253system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 254system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 255system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 256system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 257system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 258system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 259 260---------- End Simulation Statistics ---------- 261