stats.txt revision 9838
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000033 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 32544000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79838Sandreas.hansson@arm.comhost_inst_rate 27670 # Simulator instruction rate (inst/s) 89838Sandreas.hansson@arm.comhost_op_rate 27667 # Simulator op (including micro ops) rate (op/s) 99838Sandreas.hansson@arm.comhost_tick_rate 140894748 # Simulator tick rate (ticks/s) 109838Sandreas.hansson@arm.comhost_mem_usage 224272 # Number of bytes of host memory used 119838Sandreas.hansson@arm.comhost_seconds 0.23 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6390 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6390 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28544 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 446 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) 309729Sandreas.hansson@arm.comsystem.membus.throughput 877089479 # Throughput (bytes/s) 319729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 373 # Transaction distribution 329729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 373 # Transaction distribution 339729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 349729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 359838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 369838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 379838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 389838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 399729Sandreas.hansson@arm.comsystem.membus.data_through_bus 28544 # Total data (bytes) 409729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 419729Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 429729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 439729Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) 449729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 12.3 # Layer utilization (%) 458428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 468428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 478428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 488428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 499150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1183 # DTB read hits 508428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 518428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 529150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1190 # DTB read accesses 538428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 548428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 558428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 568428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 579150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 2048 # DTB hits 588428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 598428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 609150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 2058 # DTB accesses 619150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 6401 # ITB hits 628428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 638428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 649150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 6418 # ITB accesses 658428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 668428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 678428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 688428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 698428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 708428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 718428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 728428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 738428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 748428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 758428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 768428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 778428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 789285Sandreas.hansson@arm.comsystem.cpu.numCycles 65088 # number of cpu cycles simulated 798428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 808428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 819150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6390 # Number of instructions committed 829150SAli.Saidi@ARM.comsystem.cpu.committedOps 6390 # Number of ops (including micro ops) committed 839150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 848428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 858428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 869150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 879150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 6317 # number of integer instructions 888428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 899150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 8285 # number of times the integer registers were read 909150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4568 # number of times the integer registers were written 918428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 928428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 939150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2058 # number of memory refs 949150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1190 # Number of load instructions 958428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 968428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 979285Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 65088 # Number of busy cycles 988428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 998428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 1009838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 1019838Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use 1029838Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. 1039838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 1049838Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. 1059838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1069838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor 1079838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy 1089838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy 1099150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 1109150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 1119150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 1129150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 1139150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 1149150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 6122 # number of overall hits 1158835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 1168835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 1178835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 1188835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 1198835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 1208835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 1219285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles 1229285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles 1239285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles 1249285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles 1259285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles 1269285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles 1279150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 1289150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 1299150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 1309150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 1319150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 1329150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 1339150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 1349150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 1359150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 1369150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 1379150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 1389150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 1399285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency 1409285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency 1419285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1429285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency 1439285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1449285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency 1458428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1468428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1478428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1488428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1498983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1508983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1518428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1528428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1538835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 1548835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 1558835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 1568835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 1578835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 1588835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 1598835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 1608835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 1618835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 1628835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 1638835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 1648835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 1659150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 1669150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 1679150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 1689150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 1699150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 1709150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 1718835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 1729055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 1738835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1749055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 1758835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1769055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 1778428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1789838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 1799838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use 1809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 1819838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 1829838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 1839838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1849838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor 1859838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor 1869797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 1879797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 1889838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy 1898835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 1908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 1918835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 1928835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 1938835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 1948835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 1958835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 1968835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 1978835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 1988835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 1998835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 2008835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 2018835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 2028835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 2038835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 2048835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 2058835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 2068835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 2078835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 2088835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 2098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 2108835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 2118835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 2128835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 2138835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 2148835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 2158835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 2168835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 2178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 2188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 2198835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 2208835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 2218835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 2228835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 2238835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 2248835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 2258835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 2268835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 2278835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 2288835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 2298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2309055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 2318835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2329055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2338835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 2348835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2359055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 2368835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 2378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2389055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 2398835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2408835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 2419055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 2428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 2439055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 2448835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2458835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 2469055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 2478835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 2499055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 2508428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2518428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2528428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2538428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2548983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2558983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2568428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 2573048SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 2829055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 2838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 2849055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 2879055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 2888835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 2898835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 2909055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 2918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 2928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 2939055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 2948835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 2959055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 2968835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 2978835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 2989055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 2998835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3008835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3019055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3028428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3039838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 3049838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use 3059838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. 3069838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 3079838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. 3089838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3099838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor 3109838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 3119838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy 3129481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 3139481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 3149481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 3159481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 3169481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 3179481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 3189481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 3199481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 1880 # number of overall hits 3209481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 3219481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 3229481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 3239481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 3249481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 3259481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 3269481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 3279481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 168 # number of overall misses 3289481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 3299481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 3309481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 3319481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 3329481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 3339481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 3349481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 3359481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 3369481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 3379481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 3389481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 3399481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 3409481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 3419481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 3429481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 3439481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 3449481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 3459481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 3469481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 3479481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 3489481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 3499481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 3509481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 3519481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 3529481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 3539481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 3549481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 3559481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 3569481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 3579481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 3589481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 3599481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 3609481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3619481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3629481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3639481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3649481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3659481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3669481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3679481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3689481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 3699481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 3709481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 3719481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 3729481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 3739481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 3749481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 3759481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 3769481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 3779481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 3789481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 3799481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 3809481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 3819481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 3829481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 3839481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 3849481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 3859481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 3869481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 3879481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 3889481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 3899481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 3909481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 3919481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 3929481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 3939481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 3949481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 3959481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 3969481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 3979481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 3989481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 3999481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 4009481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4019729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s) 4029729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution 4039729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 4049729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 4059729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 4069838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 4079838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 4089838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 4099838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 4109838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 4119838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 4129729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) 4139729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 4149729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 4159729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 4169729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 4179729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 4189729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 4199729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 4203048SN/A 4213048SN/A---------- End Simulation Statistics ---------- 422