stats.txt revision 9481
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000033 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 32544000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79481Snilay@cs.wisc.eduhost_inst_rate 97330 # Simulator instruction rate (inst/s) 89481Snilay@cs.wisc.eduhost_op_rate 97300 # Simulator op (including micro ops) rate (op/s) 99481Snilay@cs.wisc.eduhost_tick_rate 495402774 # Simulator tick rate (ticks/s) 109481Snilay@cs.wisc.eduhost_mem_usage 269640 # Number of bytes of host memory used 119481Snilay@cs.wisc.eduhost_seconds 0.07 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6390 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6390 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28544 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 446 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 318428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 328428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 338428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 349150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1183 # DTB read hits 358428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 368428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 379150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1190 # DTB read accesses 388428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 398428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 408428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 418428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 429150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 2048 # DTB hits 438428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 448428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 459150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 2058 # DTB accesses 469150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 6401 # ITB hits 478428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 488428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 499150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 6418 # ITB accesses 508428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 518428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 528428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 538428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 548428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 558428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 568428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 578428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 588428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 598428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 608428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 618428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 628428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 639285Sandreas.hansson@arm.comsystem.cpu.numCycles 65088 # number of cpu cycles simulated 648428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 658428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 669150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6390 # Number of instructions committed 679150SAli.Saidi@ARM.comsystem.cpu.committedOps 6390 # Number of ops (including micro ops) committed 689150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 698428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 708428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 719150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 729150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 6317 # number of integer instructions 738428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 749150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 8285 # number of times the integer registers were read 759150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4568 # number of times the integer registers were written 768428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 778428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 789150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2058 # number of memory refs 799150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1190 # Number of load instructions 808428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 818428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 829285Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 65088 # Number of busy cycles 838428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 848428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 858428SN/Asystem.cpu.icache.replacements 0 # number of replacements 869285Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use 879150SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 6122 # Total number of references to valid blocks. 888428SN/Asystem.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 899150SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. 908428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 919285Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor 929285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy 939285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy 949150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 959150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 969150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 979150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 989150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 999150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 6122 # number of overall hits 1008835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 1018835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 1028835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 1038835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 1048835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 1058835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 1069285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles 1079285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles 1089285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles 1099285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles 1109285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles 1119285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles 1129150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 1139150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 1149150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 1159150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 1169150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 1179150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 1189150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 1199150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 1209150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 1219150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 1229150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 1239150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 1249285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency 1259285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency 1269285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1279285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency 1289285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1299285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency 1308428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1318428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1328428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1338428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1348983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1358983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1368428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1378428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1388835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 1398835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 1408835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 1418835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 1428835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 1438835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 1448835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 1458835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 1468835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 1478835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 1488835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 1498835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 1509150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 1519150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 1529150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 1539150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 1549150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 1559150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 1568835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 1579055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 1588835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1599055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 1608835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 1619055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 1628428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1638428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 1649285Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use 1658428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 1668428SN/Asystem.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 1678428SN/Asystem.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 1688428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1699285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor 1709285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor 1719285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 1729285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 1739285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy 1748835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 1758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 1768835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 1778835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 1788835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 1798835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 1808835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 1818835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 1828835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 1838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 1848835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 1858835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 1868835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 1878835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 1888835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 1898835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 1908835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 1918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 1928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 1938835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 1948835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 1958835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 1968835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 1978835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 1988835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 1998835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 2008835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 2018835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 2028835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 2038835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 2048835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 2058835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 2068835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 2078835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 2088835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 2098835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 2108835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 2118835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 2128835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 2138835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 2148835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2159055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 2168835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2179055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2188835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 2198835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2209055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 2218835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 2228835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2239055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 2248835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 2269055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 2278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 2289055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 2298835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2308835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 2319055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 2328835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 2338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 2349055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 2358428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2368428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2378428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2388428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2398983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2408983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2418428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 2423048SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 2438835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 2448835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 2458835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 2468835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 2478835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 2498835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 2508835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 2518835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 2528835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 2538835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 2548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 2558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 2568835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 2578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 2679055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 2699055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 2729055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 2759055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 2789055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 2809055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 2839055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 2869055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 2878428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2889481Snilay@cs.wisc.edusystem.cpu.dcache.replacements 0 # number of replacements 2899481Snilay@cs.wisc.edusystem.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use 2909481Snilay@cs.wisc.edusystem.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. 2919481Snilay@cs.wisc.edusystem.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 2929481Snilay@cs.wisc.edusystem.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. 2939481Snilay@cs.wisc.edusystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2949481Snilay@cs.wisc.edusystem.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor 2959481Snilay@cs.wisc.edusystem.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 2969481Snilay@cs.wisc.edusystem.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy 2979481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 2989481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 2999481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 3009481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 3019481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 3029481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 3039481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 3049481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 1880 # number of overall hits 3059481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 3069481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 3079481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 3089481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 3099481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 3109481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 3119481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 3129481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 168 # number of overall misses 3139481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 3149481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 3159481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 3169481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 3179481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 3189481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 3199481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 3209481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 3219481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 3229481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 3239481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 3249481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 3259481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 3269481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 3279481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 3289481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 3299481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 3309481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 3319481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 3329481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 3339481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 3349481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 3359481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 3369481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 3379481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 3389481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 3399481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 3409481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 3419481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 3429481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 3439481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 3449481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 3459481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3469481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3479481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3489481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3499481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3509481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3519481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3529481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3539481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 3549481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 3559481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 3569481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 3579481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 3589481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 3599481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 3609481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 3619481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 3629481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 3639481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 3649481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 3659481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 3669481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 3679481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 3689481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 3699481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 3709481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 3719481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 3729481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 3739481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 3749481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 3759481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 3769481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 3779481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 3789481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 3799481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 3809481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 3819481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 3829481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 3839481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 3849481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 3859481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3863048SN/A 3873048SN/A---------- End Simulation Statistics ---------- 388