stats.txt revision 7670
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 332796 # Simulator instruction rate (inst/s) 4host_mem_usage 204128 # Number of bytes of host memory used 5host_seconds 0.02 # Real time elapsed on the host 6host_tick_rate 1691799077 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 6404 # Number of instructions simulated 9sim_seconds 0.000033 # Number of seconds simulated 10sim_ticks 33007000 # Number of ticks simulated 11system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) 12system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 13system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 14system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits 15system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles 16system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses 17system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses 18system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles 19system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses 20system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses 21system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) 22system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 23system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 24system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits 25system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles 26system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses 27system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses 28system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles 29system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses 30system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses 31system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 32system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 33system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. 34system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 35system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 36system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 37system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38system.cpu.dcache.cache_copies 0 # number of cache copies performed 39system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses 40system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 41system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 42system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits 43system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles 44system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses 45system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses 46system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 47system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles 48system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses 49system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses 50system.cpu.dcache.fast_writes 0 # number of fast writes performed 51system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 52system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 53system.cpu.dcache.occ_%::0 0.025313 # Average percentage of cache occupancy 54system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context 55system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses 56system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 57system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 58system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 59system.cpu.dcache.overall_hits 1882 # number of overall hits 60system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles 61system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses 62system.cpu.dcache.overall_misses 168 # number of overall misses 63system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 64system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles 65system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses 66system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses 67system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 68system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 69system.cpu.dcache.replacements 0 # number of replacements 70system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 71system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 72system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use 73system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. 74system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 75system.cpu.dcache.writebacks 0 # number of writebacks 76system.cpu.dtb.data_accesses 2060 # DTB accesses 77system.cpu.dtb.data_acv 0 # DTB access violations 78system.cpu.dtb.data_hits 2050 # DTB hits 79system.cpu.dtb.data_misses 10 # DTB misses 80system.cpu.dtb.fetch_accesses 0 # ITB accesses 81system.cpu.dtb.fetch_acv 0 # ITB acv 82system.cpu.dtb.fetch_hits 0 # ITB hits 83system.cpu.dtb.fetch_misses 0 # ITB misses 84system.cpu.dtb.read_accesses 1192 # DTB read accesses 85system.cpu.dtb.read_acv 0 # DTB read access violations 86system.cpu.dtb.read_hits 1185 # DTB read hits 87system.cpu.dtb.read_misses 7 # DTB read misses 88system.cpu.dtb.write_accesses 868 # DTB write accesses 89system.cpu.dtb.write_acv 0 # DTB write access violations 90system.cpu.dtb.write_hits 865 # DTB write hits 91system.cpu.dtb.write_misses 3 # DTB write misses 92system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) 93system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency 94system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency 95system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits 96system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles 97system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses 98system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses 99system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles 100system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses 101system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses 102system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 103system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 104system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. 105system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 107system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 108system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 109system.cpu.icache.cache_copies 0 # number of cache copies performed 110system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses 111system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency 112system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency 113system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits 114system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles 115system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses 116system.cpu.icache.demand_misses 279 # number of demand (read+write) misses 117system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 118system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles 119system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses 120system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses 121system.cpu.icache.fast_writes 0 # number of fast writes performed 122system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 123system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 124system.cpu.icache.occ_%::0 0.062443 # Average percentage of cache occupancy 125system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context 126system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses 127system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency 128system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency 129system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 130system.cpu.icache.overall_hits 6136 # number of overall hits 131system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles 132system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses 133system.cpu.icache.overall_misses 279 # number of overall misses 134system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 135system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles 136system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses 137system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses 138system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 139system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 140system.cpu.icache.replacements 0 # number of replacements 141system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 142system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 143system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use 144system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. 145system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 146system.cpu.icache.writebacks 0 # number of writebacks 147system.cpu.idle_fraction 0 # Percentage of idle cycles 148system.cpu.itb.data_accesses 0 # DTB accesses 149system.cpu.itb.data_acv 0 # DTB access violations 150system.cpu.itb.data_hits 0 # DTB hits 151system.cpu.itb.data_misses 0 # DTB misses 152system.cpu.itb.fetch_accesses 6432 # ITB accesses 153system.cpu.itb.fetch_acv 0 # ITB acv 154system.cpu.itb.fetch_hits 6415 # ITB hits 155system.cpu.itb.fetch_misses 17 # ITB misses 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.read_acv 0 # DTB read access violations 158system.cpu.itb.read_hits 0 # DTB read hits 159system.cpu.itb.read_misses 0 # DTB read misses 160system.cpu.itb.write_accesses 0 # DTB write accesses 161system.cpu.itb.write_acv 0 # DTB write access violations 162system.cpu.itb.write_hits 0 # DTB write hits 163system.cpu.itb.write_misses 0 # DTB write misses 164system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 165system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 166system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 167system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles 168system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 169system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 170system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles 171system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 172system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 173system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) 174system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 175system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 176system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 177system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles 178system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses 179system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses 180system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles 181system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses 182system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses 183system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 184system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 185system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 186system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 187system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 188system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 189system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 190system.cpu.l2cache.cache_copies 0 # number of cache copies performed 191system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses 192system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 193system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 194system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 195system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles 196system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses 197system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses 198system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 199system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles 200system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses 201system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses 202system.cpu.l2cache.fast_writes 0 # number of fast writes performed 203system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 204system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 205system.cpu.l2cache.occ_%::0 0.005626 # Average percentage of cache occupancy 206system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context 207system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses 208system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 209system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 210system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 211system.cpu.l2cache.overall_hits 1 # number of overall hits 212system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles 213system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses 214system.cpu.l2cache.overall_misses 446 # number of overall misses 215system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 216system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles 217system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses 218system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses 219system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 220system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 221system.cpu.l2cache.replacements 0 # number of replacements 222system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 223system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 224system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use 225system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 226system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.l2cache.writebacks 0 # number of writebacks 228system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 229system.cpu.numCycles 66014 # number of cpu cycles simulated 230system.cpu.num_insts 6404 # Number of instructions executed 231system.cpu.num_refs 2060 # Number of memory references 232system.cpu.workload.PROG:num_syscalls 17 # Number of system calls 233 234---------- End Simulation Statistics ---------- 235