stats.txt revision 3048
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 37119 # Simulator instruction rate (inst/s) 4host_mem_usage 158176 # Number of bytes of host memory used 5host_seconds 0.07 # Real time elapsed on the host 6host_tick_rate 54058 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 2578 # Number of instructions simulated 9sim_seconds 0.000000 # Number of seconds simulated 10sim_ticks 3777 # Number of ticks simulated 11system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) 12system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424 # average ReadReq miss latency 13system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency 14system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits 15system.cpu.dcache.ReadReq_miss_latency 160540198482307121152 # number of ReadReq miss cycles 16system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses 17system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses 18system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles 19system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses 20system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses 21system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) 22system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320 # average WriteReq miss latency 23system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency 24system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits 25system.cpu.dcache.WriteReq_miss_latency 120861284004822319104 # number of WriteReq miss cycles 26system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses 27system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses 28system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles 29system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses 30system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses 31system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 32system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 33system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks. 34system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 35system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked 36system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 37system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 38system.cpu.dcache.cache_copies 0 # number of cache copies performed 39system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses 40system.cpu.dcache.demand_avg_miss_latency 3431725396184505344 # average overall miss latency 41system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency 42system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits 43system.cpu.dcache.demand_miss_latency 281401482487129440256 # number of demand (read+write) miss cycles 44system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses 45system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses 46system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 47system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles 48system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses 49system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses 50system.cpu.dcache.fast_writes 0 # number of fast writes performed 51system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 52system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 53system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses 54system.cpu.dcache.overall_avg_miss_latency 3431725396184505344 # average overall miss latency 55system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency 56system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 57system.cpu.dcache.overall_hits 628 # number of overall hits 58system.cpu.dcache.overall_miss_latency 281401482487129440256 # number of overall miss cycles 59system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses 60system.cpu.dcache.overall_misses 82 # number of overall misses 61system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 62system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles 63system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses 64system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses 65system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 66system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 67system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 68system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 69system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 70system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 71system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 72system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 73system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 74system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 75system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 76system.cpu.dcache.replacements 0 # number of replacements 77system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. 78system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 79system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use 80system.cpu.dcache.total_refs 628 # Total number of references to valid blocks. 81system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 82system.cpu.dcache.writebacks 0 # number of writebacks 83system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) 84system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128 # average ReadReq miss latency 85system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency 86system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits 87system.cpu.icache.ReadReq_miss_latency 562005703046928072704 # number of ReadReq miss cycles 88system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses 89system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses 90system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles 91system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses 92system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses 93system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 94system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 95system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks. 96system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 97system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 98system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 99system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 100system.cpu.icache.cache_copies 0 # number of cache copies performed 101system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses 102system.cpu.icache.demand_avg_miss_latency 3447887748754160128 # average overall miss latency 103system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency 104system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits 105system.cpu.icache.demand_miss_latency 562005703046928072704 # number of demand (read+write) miss cycles 106system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses 107system.cpu.icache.demand_misses 163 # number of demand (read+write) misses 108system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 109system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles 110system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses 111system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses 112system.cpu.icache.fast_writes 0 # number of fast writes performed 113system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 114system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 115system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses 116system.cpu.icache.overall_avg_miss_latency 3447887748754160128 # average overall miss latency 117system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency 118system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 119system.cpu.icache.overall_hits 2416 # number of overall hits 120system.cpu.icache.overall_miss_latency 562005703046928072704 # number of overall miss cycles 121system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses 122system.cpu.icache.overall_misses 163 # number of overall misses 123system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 124system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles 125system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses 126system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses 127system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 128system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 129system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 130system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 131system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 132system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 133system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 134system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 135system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 136system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 137system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 138system.cpu.icache.replacements 0 # number of replacements 139system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. 140system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 141system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use 142system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. 143system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 144system.cpu.icache.writebacks 0 # number of writebacks 145system.cpu.idle_fraction 0 # Percentage of idle cycles 146system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) 147system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency 148system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency 149system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles 150system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 151system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses 152system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles 153system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses 154system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses 155system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 156system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 157system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. 158system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked 159system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked 160system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 161system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked 162system.cpu.l2cache.cache_copies 0 # number of cache copies performed 163system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses 164system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency 165system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency 166system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits 167system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles 168system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses 169system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses 170system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 171system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles 172system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses 173system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses 174system.cpu.l2cache.fast_writes 0 # number of fast writes performed 175system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 176system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 177system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses 178system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency 179system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency 180system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 181system.cpu.l2cache.overall_hits 0 # number of overall hits 182system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles 183system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses 184system.cpu.l2cache.overall_misses 245 # number of overall misses 185system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 186system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles 187system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses 188system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses 189system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 190system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 191system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 192system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 193system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 194system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 195system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 196system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 197system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 198system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 199system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 200system.cpu.l2cache.replacements 0 # number of replacements 201system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. 202system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 203system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use 204system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. 205system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 206system.cpu.l2cache.writebacks 0 # number of writebacks 207system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 208system.cpu.numCycles 0 # number of cpu cycles simulated 209system.cpu.num_insts 2578 # Number of instructions executed 210system.cpu.num_refs 710 # Number of memory references 211system.cpu.workload.PROG:num_syscalls 4 # Number of system calls 212 213---------- End Simulation Statistics ---------- 214