stats.txt revision 10726
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000033 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 32544500 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710726Sandreas.hansson@arm.comhost_inst_rate 643051 # Simulator instruction rate (inst/s) 810726Sandreas.hansson@arm.comhost_op_rate 642147 # Simulator op (including micro ops) rate (op/s) 910726Sandreas.hansson@arm.comhost_tick_rate 3266208350 # Simulator tick rate (ticks/s) 1010726Sandreas.hansson@arm.comhost_mem_usage 291356 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 0.01 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6390 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6390 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28544 # Number of bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 209055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 239055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 446 # Number of read requests responded to by this memory 2410726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) 2510726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) 2610726Sandreas.hansson@arm.comsystem.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) 2710726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) 2810726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) 2910726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) 3010726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) 3110726Sandreas.hansson@arm.comsystem.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) 3210036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 338428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 348428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 358428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 368428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 379150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1183 # DTB read hits 388428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 398428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 409150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1190 # DTB read accesses 418428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 428428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 438428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 448428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 459150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 2048 # DTB hits 468428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 478428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 489150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 2058 # DTB accesses 499150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 6401 # ITB hits 508428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 518428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 529150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 6418 # ITB accesses 538428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 548428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 558428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 568428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 578428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 588428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 598428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 608428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 618428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 628428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 638428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 648428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 658428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 6610726Sandreas.hansson@arm.comsystem.cpu.numCycles 65089 # number of cpu cycles simulated 678428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 688428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 699150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6390 # Number of instructions committed 709150SAli.Saidi@ARM.comsystem.cpu.committedOps 6390 # Number of ops (including micro ops) committed 719150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 728428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 738428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 749150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 759150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 6317 # number of integer instructions 768428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 779150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 8285 # number of times the integer registers were read 789150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4568 # number of times the integer registers were written 798428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 808428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 819150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2058 # number of memory refs 829150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1190 # Number of load instructions 838428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 848428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 8510726Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 65089 # Number of busy cycles 868428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 878428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 8810063Snilay@cs.wisc.edusystem.cpu.Branches 1050 # Number of branches fetched 8910220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 9010220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 9110220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 9210220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 9310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction 9410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction 9510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction 9610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction 9710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction 9810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction 9910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction 10010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction 10110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction 10210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction 10310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction 10410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction 10510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction 10610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction 10710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction 10810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction 10910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction 11010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction 11110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction 11210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction 11310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction 11410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction 11510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction 11610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction 11710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 11810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 11910220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 12010220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 12110220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 12210220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 12310220Sandreas.hansson@arm.comsystem.cpu.op_class::total 6400 # Class of executed instruction 1249838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 12510726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use 1269838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. 1279838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 1289838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. 1299838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 13010726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor 13110726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy 13210726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy 13310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 13410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 13510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 13610036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 13710036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses 13810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 4264 # Number of data accesses 1399481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 1409481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 1419481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 1429481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 1439481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 1449481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 1459481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 1469481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 1880 # number of overall hits 1479481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 1489481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 1499481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 1509481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 1519481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 1529481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 1539481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 1549481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 168 # number of overall misses 1559481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 1569481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 1579481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 1589481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 1599481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 1609481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 1619481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 1629481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 1639481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 1649481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 1659481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 1669481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 1679481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 1689481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 1699481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 1709481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 1719481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 1729481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 1739481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 1749481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 1759481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 1769481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 1779481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 1789481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 1799481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 1809481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 1819481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 1829481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 1839481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 1849481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 1859481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 1869481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 1879481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1889481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1899481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1909481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1919481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1929481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1939481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 1949481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 1959481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 1969481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 1979481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 1989481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 1999481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 2009481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 2019481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 2029481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 20310726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles 20410726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles 20510726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles 20610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles 20710726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles 20810726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles 20910726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles 21010726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles 2119481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 2129481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 2139481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 2149481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 2159481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 2169481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 2179481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 2189481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 21910726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency 22010726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency 22110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency 22210726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency 22310726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency 22410726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency 22510726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency 22610726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency 2279481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 22810726Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 22910726Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use 23010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. 23110726Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 23210726Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. 23310726Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 23410726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor 23510726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy 23610726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy 23710726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 23810726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 23910726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 24010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 24110726Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses 24210726Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 13081 # Number of data accesses 24310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 24410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 24510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 24610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 24710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 24810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 6122 # number of overall hits 24910726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 25010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 25110726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 25210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 25310726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 25410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 25510726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles 25610726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles 25710726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles 25810726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles 25910726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles 26010726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles 26110726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 26210726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 26310726Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 26410726Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 26510726Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 26610726Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 26710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 26810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 26910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 27010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 27110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 27210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 27310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency 27410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency 27510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency 27610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency 27710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency 27810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency 27910726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 28010726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 28110726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 28210726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 28310726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28410726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28510726Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 28610726Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 28710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 28810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 28910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 29010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 29110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 29210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 29310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles 29410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles 29510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles 29610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles 29710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles 29810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles 29910726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 30010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 30110726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 30210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 30310726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 30410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 30510726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency 30610726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency 30710726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency 30810726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency 30910726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency 31010726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency 31110726Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 31210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 31310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use 31410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 31510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 31610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 31710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 31810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor 31910726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor 32010726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 32110726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 32210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy 32310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 32410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 32510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 32610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 32710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 32810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses 32910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 33010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 33110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 33210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 33310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 33410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 33510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 33610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 33710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 33810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 33910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 34010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 34110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 34210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 34310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 34410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 34510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 34610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles 34710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles 34810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles 34910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles 35010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles 35110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles 35210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles 35310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles 35410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles 35510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles 35610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles 35710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 35810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 35910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 36010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 36110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 36210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 36310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 36410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 36510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 36610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 36710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 36810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 36910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 37010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 37110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 37210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 37310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 37410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 37510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 37610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 37710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 37810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 37910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency 38010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 38110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency 38210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 38310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 38410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency 38510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 38610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency 38710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency 38810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 38910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency 39010726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39110726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39210726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 39310726Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 39410726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39510726Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39610726Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 39710726Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 39810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 39910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 40010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 40110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 40210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 40310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 40410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 40510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 40610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 40710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 40810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 40910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles 41010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles 41110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles 41210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles 41310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles 41410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles 41510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles 41610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles 41710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles 41810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles 41910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles 42010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 42110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 42210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 42310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 42410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 42510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 42610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 42710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 42810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 42910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 43010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 43110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 43210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 43310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 43410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 43510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 43610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 43710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 43810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 43910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 44010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 44110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 44210726Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 4439729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution 4449729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 4459729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 4469729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 4479838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 4489838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 4499838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 45010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 45110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 45210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 45310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 45410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram 45510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 45610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 45710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 45910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram 46010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 46110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 46210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 46310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 46410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 4659729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 4669729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 4679729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 4689729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 4699729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 4709729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 47110726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 373 # Transaction distribution 47210726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 373 # Transaction distribution 47310726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 47410726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 47510726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 47610726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 47710726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 47810726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 47910726Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 48010726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 446 # Request fanout histogram 48110726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 48210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 48310726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 48410726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 48510726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 48610726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 48810726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 48910726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 446 # Request fanout histogram 49010726Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) 49110726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 49210726Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) 49310726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 6.9 # Layer utilization (%) 4943048SN/A 4953048SN/A---------- End Simulation Statistics ---------- 496