stats.txt revision 10409
13048SN/A 23048SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000033 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 32544000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 485157 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 484642 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 2465828156 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 286540 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 0.01 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6390 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6390 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 28544 # Number of bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 209055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 239055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 446 # Number of read requests responded to by this memory 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 309285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 319285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) 329729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 373 # Transaction distribution 339729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 373 # Transaction distribution 349729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 359729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 369838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 379838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 3810409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 3910409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 4010409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 4110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 446 # Request fanout histogram 4210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 4310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 4410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 4510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 4610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 4710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 4810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 4910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 5010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 446 # Request fanout histogram 519729Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 529729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 539729Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) 549729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 12.3 # Layer utilization (%) 5510036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 568428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 578428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 588428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 598428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 609150SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1183 # DTB read hits 618428SN/Asystem.cpu.dtb.read_misses 7 # DTB read misses 628428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 639150SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1190 # DTB read accesses 648428SN/Asystem.cpu.dtb.write_hits 865 # DTB write hits 658428SN/Asystem.cpu.dtb.write_misses 3 # DTB write misses 668428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 678428SN/Asystem.cpu.dtb.write_accesses 868 # DTB write accesses 689150SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 2048 # DTB hits 698428SN/Asystem.cpu.dtb.data_misses 10 # DTB misses 708428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 719150SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 2058 # DTB accesses 729150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 6401 # ITB hits 738428SN/Asystem.cpu.itb.fetch_misses 17 # ITB misses 748428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 759150SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 6418 # ITB accesses 768428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 778428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 788428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 798428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 808428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 818428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 828428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 838428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 848428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 858428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 868428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 878428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 888428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 899285Sandreas.hansson@arm.comsystem.cpu.numCycles 65088 # number of cpu cycles simulated 908428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 918428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 929150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6390 # Number of instructions committed 939150SAli.Saidi@ARM.comsystem.cpu.committedOps 6390 # Number of ops (including micro ops) committed 949150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 958428SN/Asystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 968428SN/Asystem.cpu.num_func_calls 251 # number of times a function call or return occured 979150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 989150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 6317 # number of integer instructions 998428SN/Asystem.cpu.num_fp_insts 10 # number of float instructions 1009150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 8285 # number of times the integer registers were read 1019150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4568 # number of times the integer registers were written 1028428SN/Asystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 1038428SN/Asystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 1049150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 2058 # number of memory refs 1059150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 1190 # Number of load instructions 1068428SN/Asystem.cpu.num_store_insts 868 # Number of store instructions 1078428SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 1089285Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 65088 # Number of busy cycles 1098428SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 1108428SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 11110063Snilay@cs.wisc.edusystem.cpu.Branches 1050 # Number of branches fetched 11210220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 11310220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 11410220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 11510220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 11610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction 11710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction 11810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction 11910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction 12010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction 12110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction 12210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction 12310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction 12410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction 12510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction 12610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction 12710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction 12810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction 12910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction 13010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction 13110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction 13210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction 13310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction 13410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction 13510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction 13610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction 13710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction 13810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction 13910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction 14010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 14110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 14210220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 14310220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 14410220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 14510220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 14610220Sandreas.hansson@arm.comsystem.cpu.op_class::total 6400 # Class of executed instruction 1479838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 1489838Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use 1499838Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. 1509838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 1519838Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. 1529838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1539838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor 1549838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy 1559838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy 15610036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 15710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 15810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 15910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 16010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses 16110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 13081 # Number of data accesses 1629150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 1639150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 1649150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 1659150SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 1669150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 1679150SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 6122 # number of overall hits 1688835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 1698835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 1708835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 1718835SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 1728835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 1738835SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 279 # number of overall misses 1749285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles 1759285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles 1769285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles 1779285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles 1789285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles 1799285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles 1809150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 1819150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 1829150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 1839150SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 1849150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 1859150SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 1869150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 1879150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 1889150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 1899150SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 1909150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 1919150SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses 1929285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency 1939285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency 1949285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1959285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency 1969285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency 1979285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency 1988428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1998428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2008428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2018428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 2028983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2038983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2048428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 2058428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 2068835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 2078835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 2088835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 2098835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 2108835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 2118835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 2128835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 2138835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 2148835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 2158835SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 2168835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 2178835SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 2189150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 2199150SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 2209150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 2219150SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 2229150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 2239150SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses 2248835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 2259055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 2268835SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 2279055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 2288835SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 2299055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 2308428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2319838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 2329838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use 2339838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 2349838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 2359838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 2369838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2379838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor 2389838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor 2399797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy 2409797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy 2419838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy 24210036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 24310036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 24410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 24510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 24610036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 24710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses 2488835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 2498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 2508835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 2518835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 2528835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 2538835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 2548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 2558835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 2568835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses 2578835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 2588835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 2598835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 2608835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 2618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 2628835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses 2638835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses 2648835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 446 # number of overall misses 2658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles 2668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles 2678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles 2688835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles 2698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles 2708835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles 2718835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles 2728835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles 2738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles 2748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles 2758835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles 2768835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) 2778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) 2788835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) 2798835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 2808835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 2818835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 2828835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 2838835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 2848835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 2858835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 2868835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 2878835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 2888835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 2899055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses 2908835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 2919055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 2928835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 2938835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 2949055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses 2958835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 2968835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 2979055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses 2988835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 2998835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 3009055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 3018835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 3029055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 3038835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 3048835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 3059055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 3068835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 3078835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 3089055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 3098428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3108428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3118428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 3128428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 3138983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3148983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3158428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 3163048SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 3178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 3188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 3198835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 3208835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 3218835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 3228835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 3238835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 3248835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 3258835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 3268835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 3278835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 3288835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles 3298835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles 3308835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles 3318835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles 3328835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles 3338835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 3348835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 3358835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 3368835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 3378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 3388835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 3398835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 3408835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 3419055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses 3428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 3439055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 3448835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 3458835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 3469055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses 3478835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 3488835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 3499055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses 3508835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 3518835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 3529055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 3538835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 3549055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 3558835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3568835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3579055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3588835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 3598835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 3609055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 3618428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3629838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 3639838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use 3649838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. 3659838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 3669838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. 3679838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3689838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor 3699838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 3709838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy 37110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 37210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 37310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 37410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 37510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses 37610036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 4264 # Number of data accesses 3779481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits 3789481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits 3799481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 3809481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 3819481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits 3829481Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits 3839481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits 3849481Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 1880 # number of overall hits 3859481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 3869481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 3879481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 3889481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 3899481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 3909481Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 3919481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 3929481Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 168 # number of overall misses 3939481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles 3949481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles 3959481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles 3969481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles 3979481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles 3989481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles 3999481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles 4009481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles 4019481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) 4029481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) 4039481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 4049481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 4059481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses 4069481Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses 4079481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses 4089481Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses 4099481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses 4109481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses 4119481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 4129481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 4139481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses 4149481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses 4159481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses 4169481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses 4179481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 4189481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 4199481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 4209481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 4219481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 4229481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 4239481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 4249481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 4259481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4269481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4279481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4289481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4299481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4309481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4319481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4329481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4339481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 4349481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 4359481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 4369481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 4379481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 4389481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 4399481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 4409481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 4419481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles 4429481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 4439481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 4449481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 4459481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 4469481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 4479481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 4489481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 4499481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses 4509481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses 4519481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 4529481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 4539481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses 4549481Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses 4559481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses 4569481Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses 4579481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 4589481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 4599481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 4609481Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 4619481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 4629481Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 4639481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 4649481Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 4659481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4669729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution 4679729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 4689729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 4699729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 4709838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 4719838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 4729838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 47310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 47410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 47510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 47610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 47710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram 47810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 47910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 48010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 48110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 48210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram 48310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 48410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 48610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 48710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 4889729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 4899729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 4909729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 4919729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 4929729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 4939729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 4943048SN/A 4953048SN/A---------- End Simulation Statistics ---------- 496