xref: /gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000033                       # Number of seconds simulated
sim_ticks                                    32544000                       # Number of ticks simulated
final_tick                                   32544000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 550056                       # Simulator instruction rate (inst/s)
host_op_rate                                   549394                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2794675827                       # Simulator tick rate (ticks/s)
host_mem_usage                                 262632                       # Number of bytes of host memory used
host_seconds                                     0.01                       # Real time elapsed on the host
sim_insts                                        6390                       # Number of instructions simulated
sim_ops                                          6390                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            546705998                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            330383481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               877089479                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       546705998                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          546705998                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           546705998                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           330383481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              877089479                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                    877089479                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                 373                       # Transaction distribution
system.membus.trans_dist::ReadResp                373                       # Transaction distribution
system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          892                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    892                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total               28544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                  28544                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy              446000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy            4014000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization             12.3                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                         1183                       # DTB read hits
system.cpu.dtb.read_misses                          7                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
system.cpu.dtb.write_hits                         865                       # DTB write hits
system.cpu.dtb.write_misses                         3                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                     868                       # DTB write accesses
system.cpu.dtb.data_hits                         2048                       # DTB hits
system.cpu.dtb.data_misses                         10                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                     2058                       # DTB accesses
system.cpu.itb.fetch_hits                        6401                       # ITB hits
system.cpu.itb.fetch_misses                        17                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   17                       # Number of system calls
system.cpu.numCycles                            65088                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        6390                       # Number of instructions committed
system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
system.cpu.num_func_calls                         251                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         6317                       # number of integer instructions
system.cpu.num_fp_insts                            10                       # number of float instructions
system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
system.cpu.num_mem_refs                          2058                       # number of memory refs
system.cpu.num_load_insts                        1190                       # Number of load instructions
system.cpu.num_store_insts                        868                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                      65088                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.Branches                              1050                       # Number of branches fetched
system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
system.cpu.op_class::IntAlu                      4320     67.50%     67.80% # Class of executed instruction
system.cpu.op_class::IntMult                        1      0.02%     67.81% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd                       2      0.03%     67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.84% # Class of executed instruction
system.cpu.op_class::MemRead                     1190     18.59%     86.44% # Class of executed instruction
system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                       6400                       # Class of executed instruction
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           127.998991                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                6122                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               279                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             21.942652                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   127.998991                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.062500                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.062500                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          279                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.136230                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             13081                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            13081                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst         6122                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            6122                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          6122                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             6122                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         6122                       # number of overall hits
system.cpu.icache.overall_hits::total            6122                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           279                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            279                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          279                       # number of overall misses
system.cpu.icache.overall_misses::total           279                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     15303000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     15303000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     15303000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     15303000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     15303000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     15303000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         6401                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         6401                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         6401                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         6401                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         6401                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         6401                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043587                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.043587                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.043587                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.043587                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.043587                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.043587                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54849.462366                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54849.462366                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          279                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          279                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14745000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     14745000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14745000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     14745000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14745000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     14745000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043587                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.043587                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.043587                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          184.497210                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              373                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.002681                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   128.017765                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data    56.479444                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003907                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.001724                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.005630                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          373                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011383                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4022                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4022                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          373                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14456000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4940000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     19396000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3796000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      3796000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     14456000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      8736000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     23192000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     14456000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      8736000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     23192000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          279                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          374                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          279                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          279                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.997326                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          373                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11120000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3800000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14920000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2920000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2920000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11120000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6720000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     17840000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11120000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6720000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     17840000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997326                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           103.762109                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1880                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.190476                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   103.762109                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.025333                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.025333                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.041016                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4264                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4264                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            792                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1880                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1880                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1880                       # number of overall hits
system.cpu.dcache.overall_hits::total            1880                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            95                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           73                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           73                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            168                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          168                       # number of overall misses
system.cpu.dcache.overall_misses::total           168                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      5225000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      5225000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      4015000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      4015000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data      9240000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total      9240000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data      9240000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total      9240000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1183                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1183                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2048                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2048                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2048                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2048                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080304                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.080304                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.084393                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.082031                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.082031                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.082031                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.082031                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5035000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      5035000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3869000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      3869000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8904000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      8904000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8904000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      8904000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput               879056047                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq            374                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp           374                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          558                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          336                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               894                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total          28608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus             28608                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy         223500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        418500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        252000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)

---------- End Simulation Statistics   ----------