xref: /gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000036                       # Number of seconds simulated
sim_ticks                                    36128500                       # Number of ticks simulated
final_tick                                   36128500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 739000                       # Simulator instruction rate (inst/s)
host_op_rate                                   738191                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             4160971439                       # Simulator tick rate (ticks/s)
host_mem_usage                                 251728                       # Number of bytes of host memory used
host_seconds                                     0.01                       # Real time elapsed on the host
sim_insts                                        6403                       # Number of instructions simulated
sim_ops                                          6403                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst            492464398                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            297604384                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               790068782                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst       492464398                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total          492464398                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst           492464398                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           297604384                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              790068782                       # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                         1185                       # DTB read hits
system.cpu.dtb.read_misses                          7                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
system.cpu.dtb.write_hits                         865                       # DTB write hits
system.cpu.dtb.write_misses                         3                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                     868                       # DTB write accesses
system.cpu.dtb.data_hits                         2050                       # DTB hits
system.cpu.dtb.data_misses                         10                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                     2060                       # DTB accesses
system.cpu.itb.fetch_hits                        6414                       # ITB hits
system.cpu.itb.fetch_misses                        17                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                    6431                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.numSyscalls                    17                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON        36128500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                            72257                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                        6403                       # Number of instructions committed
system.cpu.committedOps                          6403                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses                  6329                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
system.cpu.num_func_calls                         251                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts          754                       # number of instructions that are conditional controls
system.cpu.num_int_insts                         6329                       # number of integer instructions
system.cpu.num_fp_insts                            10                       # number of float instructions
system.cpu.num_int_register_reads                8297                       # number of times the integer registers were read
system.cpu.num_int_register_writes               4575                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
system.cpu.num_mem_refs                          2060                       # number of memory refs
system.cpu.num_load_insts                        1192                       # Number of load instructions
system.cpu.num_store_insts                        868                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                      72257                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.Branches                              1056                       # Number of branches fetched
system.cpu.op_class::No_OpClass                    19      0.30%      0.30% # Class of executed instruction
system.cpu.op_class::IntAlu                      4331     67.53%     67.83% # Class of executed instruction
system.cpu.op_class::IntMult                        1      0.02%     67.85% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd                       2      0.03%     67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.88% # Class of executed instruction
system.cpu.op_class::MemRead                     1191     18.57%     86.45% # Class of executed instruction
system.cpu.op_class::MemWrite                     861     13.43%     99.88% # Class of executed instruction
system.cpu.op_class::FloatMemRead                   1      0.02%     99.89% # Class of executed instruction
system.cpu.op_class::FloatMemWrite                  7      0.11%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                       6413                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements                 0                       # number of replacements
system.cpu.dcache.tags.tagsinuse           103.721081                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs                1882                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.202381                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   103.721081                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.025323                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.025323                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.041016                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses              4268                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses             4268                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data         1090                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1090                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            792                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1882                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1882                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1882                       # number of overall hits
system.cpu.dcache.overall_hits::total            1882                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            95                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data           73                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total           73                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            168                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          168                       # number of overall misses
system.cpu.dcache.overall_misses::total           168                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      5985000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      5985000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      4599000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      4599000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     10584000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     10584000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     10584000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     10584000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2050                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2050                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080169                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.080169                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.084393                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.081951                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.081951                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.081951                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.081951                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        63000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total        63000                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        63000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total        63000                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data        63000                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total        63000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data        63000                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total        63000                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5890000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      5890000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4526000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      4526000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10416000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total     10416000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10416000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total     10416000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        62000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        62000                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        62000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        62000                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        62000                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total        62000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        62000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total        62000                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements                 0                       # number of replacements
system.cpu.icache.tags.tagsinuse           127.170991                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs                6135                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs               279                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             21.989247                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   127.170991                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.062095                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.062095                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          279                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          185                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.136230                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses             13107                       # Number of tag accesses
system.cpu.icache.tags.data_accesses            13107                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst         6135                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total            6135                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst          6135                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total             6135                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst         6135                       # number of overall hits
system.cpu.icache.overall_hits::total            6135                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           279                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            279                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          279                       # number of overall misses
system.cpu.icache.overall_misses::total           279                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     17528500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     17528500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     17528500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     17528500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     17528500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     17528500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst         6414                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total         6414                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst         6414                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total         6414                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst         6414                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total         6414                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043499                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.043499                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.043499                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.043499                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.043499                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.043499                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 62826.164875                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 62826.164875                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          279                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          279                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     17249500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     17249500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     17249500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     17249500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     17249500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     17249500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043499                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043499                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043499                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.043499                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043499                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.043499                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse          230.937880                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs              446                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.002242                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.167974                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   103.769906                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003881                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.003167                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.007048                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024          446                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013611                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses             4022                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses            4022                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          278                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total          278                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data           95                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total           95                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4416500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      4416500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     16819500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total     16819500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      5747500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total      5747500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     16819500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data     10164000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     26983500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     16819500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data     10164000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     26983500                       # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          279                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total          279                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data           95                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total           95                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          279                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          279                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.996416                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total            1                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        60500                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        60500                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        60500                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        60500                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        60500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        60500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          278                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total          278                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data           95                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total           95                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3686500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3686500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     14039500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     14039500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      4797500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      4797500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     14039500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8484000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     22523500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     14039500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8484000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     22523500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.996416                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        50500                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        50500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        50500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        50500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests          447                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp           374                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq          279                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq           95                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          558                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          336                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total               894                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total              28608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples          447                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.002237                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.047298                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                446     99.78%     99.78% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  1      0.22%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total            447                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy         223500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy        418500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy        252000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests           446                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED     36128500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp                373                       # Transaction distribution
system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq           373                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          892                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                    892                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                   28544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples               446                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                     446    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                 446                       # Request fanout histogram
system.membus.reqLayer0.occupancy              446500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy            2230000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              6.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------