config.ini revision 11570
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63default_p_state=UNDEFINED 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload 91dcache_port=system.cpu.dcache.cpu_side 92icache_port=system.cpu.icache.cpu_side 93 94[system.cpu.dcache] 95type=Cache 96children=tags 97addr_ranges=0:18446744073709551615 98assoc=2 99clk_domain=system.cpu_clk_domain 100clusivity=mostly_incl 101default_p_state=UNDEFINED 102demand_mshr_reserve=1 103eventq_index=0 104hit_latency=2 105is_read_only=false 106max_miss_count=0 107mshrs=4 108p_state_clk_gate_bins=20 109p_state_clk_gate_max=1000000000000 110p_state_clk_gate_min=1000 111power_model=Null 112prefetch_on_access=false 113prefetcher=Null 114response_latency=2 115sequential_access=false 116size=262144 117system=system 118tags=system.cpu.dcache.tags 119tgts_per_mshr=20 120write_buffers=8 121writeback_clean=false 122cpu_side=system.cpu.dcache_port 123mem_side=system.cpu.toL2Bus.slave[1] 124 125[system.cpu.dcache.tags] 126type=LRU 127assoc=2 128block_size=64 129clk_domain=system.cpu_clk_domain 130default_p_state=UNDEFINED 131eventq_index=0 132hit_latency=2 133p_state_clk_gate_bins=20 134p_state_clk_gate_max=1000000000000 135p_state_clk_gate_min=1000 136power_model=Null 137sequential_access=false 138size=262144 139 140[system.cpu.dtb] 141type=AlphaTLB 142eventq_index=0 143size=64 144 145[system.cpu.icache] 146type=Cache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain 151clusivity=mostly_incl 152default_p_state=UNDEFINED 153demand_mshr_reserve=1 154eventq_index=0 155hit_latency=2 156is_read_only=true 157max_miss_count=0 158mshrs=4 159p_state_clk_gate_bins=20 160p_state_clk_gate_max=1000000000000 161p_state_clk_gate_min=1000 162power_model=Null 163prefetch_on_access=false 164prefetcher=Null 165response_latency=2 166sequential_access=false 167size=131072 168system=system 169tags=system.cpu.icache.tags 170tgts_per_mshr=20 171write_buffers=8 172writeback_clean=true 173cpu_side=system.cpu.icache_port 174mem_side=system.cpu.toL2Bus.slave[0] 175 176[system.cpu.icache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain 181default_p_state=UNDEFINED 182eventq_index=0 183hit_latency=2 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null 188sequential_access=false 189size=131072 190 191[system.cpu.interrupts] 192type=AlphaInterrupts 193eventq_index=0 194 195[system.cpu.isa] 196type=AlphaISA 197eventq_index=0 198system=system 199 200[system.cpu.itb] 201type=AlphaTLB 202eventq_index=0 203size=48 204 205[system.cpu.l2cache] 206type=Cache 207children=tags 208addr_ranges=0:18446744073709551615 209assoc=8 210clk_domain=system.cpu_clk_domain 211clusivity=mostly_incl 212default_p_state=UNDEFINED 213demand_mshr_reserve=1 214eventq_index=0 215hit_latency=20 216is_read_only=false 217max_miss_count=0 218mshrs=20 219p_state_clk_gate_bins=20 220p_state_clk_gate_max=1000000000000 221p_state_clk_gate_min=1000 222power_model=Null 223prefetch_on_access=false 224prefetcher=Null 225response_latency=20 226sequential_access=false 227size=2097152 228system=system 229tags=system.cpu.l2cache.tags 230tgts_per_mshr=12 231write_buffers=8 232writeback_clean=false 233cpu_side=system.cpu.toL2Bus.master[0] 234mem_side=system.membus.slave[1] 235 236[system.cpu.l2cache.tags] 237type=LRU 238assoc=8 239block_size=64 240clk_domain=system.cpu_clk_domain 241default_p_state=UNDEFINED 242eventq_index=0 243hit_latency=20 244p_state_clk_gate_bins=20 245p_state_clk_gate_max=1000000000000 246p_state_clk_gate_min=1000 247power_model=Null 248sequential_access=false 249size=2097152 250 251[system.cpu.toL2Bus] 252type=CoherentXBar 253children=snoop_filter 254clk_domain=system.cpu_clk_domain 255default_p_state=UNDEFINED 256eventq_index=0 257forward_latency=0 258frontend_latency=1 259p_state_clk_gate_bins=20 260p_state_clk_gate_max=1000000000000 261p_state_clk_gate_min=1000 262point_of_coherency=false 263power_model=Null 264response_latency=1 265snoop_filter=system.cpu.toL2Bus.snoop_filter 266snoop_response_latency=1 267system=system 268use_default_range=false 269width=32 270master=system.cpu.l2cache.cpu_side 271slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 272 273[system.cpu.toL2Bus.snoop_filter] 274type=SnoopFilter 275eventq_index=0 276lookup_latency=0 277max_capacity=8388608 278system=system 279 280[system.cpu.tracer] 281type=ExeTracer 282eventq_index=0 283 284[system.cpu.workload] 285type=LiveProcess 286cmd=hello 287cwd= 288drivers= 289egid=100 290env= 291errout=cerr 292euid=100 293eventq_index=0 294executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello 295gid=100 296input=cin 297kvmInSE=false 298max_stack_size=67108864 299output=cout 300pid=100 301ppid=99 302simpoint=0 303system=system 304uid=100 305useArchPT=false 306 307[system.cpu_clk_domain] 308type=SrcClockDomain 309clock=500 310domain_id=-1 311eventq_index=0 312init_perf_level=0 313voltage_domain=system.voltage_domain 314 315[system.dvfs_handler] 316type=DVFSHandler 317domains= 318enable=false 319eventq_index=0 320sys_clk_domain=system.clk_domain 321transition_latency=100000000 322 323[system.membus] 324type=CoherentXBar 325clk_domain=system.clk_domain 326default_p_state=UNDEFINED 327eventq_index=0 328forward_latency=4 329frontend_latency=3 330p_state_clk_gate_bins=20 331p_state_clk_gate_max=1000000000000 332p_state_clk_gate_min=1000 333point_of_coherency=true 334power_model=Null 335response_latency=2 336snoop_filter=Null 337snoop_response_latency=4 338system=system 339use_default_range=false 340width=16 341master=system.physmem.port 342slave=system.system_port system.cpu.l2cache.mem_side 343 344[system.physmem] 345type=SimpleMemory 346bandwidth=73.000000 347clk_domain=system.clk_domain 348conf_table_reported=true 349default_p_state=UNDEFINED 350eventq_index=0 351in_addr_map=true 352latency=30000 353latency_var=0 354null=false 355p_state_clk_gate_bins=20 356p_state_clk_gate_max=1000000000000 357p_state_clk_gate_min=1000 358power_model=Null 359range=0:134217727 360port=system.membus.master[0] 361 362[system.voltage_domain] 363type=VoltageDomain 364eventq_index=0 365voltage=1.000000 366 367