stats.txt revision 8835:7c68f84d7c4e
12810Srdreslin@umich.edu 29796Sprakash.ramrakhyani@arm.com---------- Begin Simulation Statistics ---------- 39347SAndreas.Sandberg@arm.comsim_seconds 0.000343 # Number of seconds simulated 49347SAndreas.Sandberg@arm.comsim_ticks 342698 # Number of ticks simulated 59347SAndreas.Sandberg@arm.comfinal_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 69347SAndreas.Sandberg@arm.comsim_freq 1000000000 # Frequency of simulated ticks 79347SAndreas.Sandberg@arm.comhost_inst_rate 61504 # Simulator instruction rate (inst/s) 89347SAndreas.Sandberg@arm.comhost_op_rate 61493 # Simulator op (including micro ops) rate (op/s) 99347SAndreas.Sandberg@arm.comhost_tick_rate 3290073 # Simulator tick rate (ticks/s) 109347SAndreas.Sandberg@arm.comhost_mem_usage 220236 # Number of bytes of host memory used 119347SAndreas.Sandberg@arm.comhost_seconds 0.10 # Real time elapsed on the host 129347SAndreas.Sandberg@arm.comsim_insts 6404 # Number of instructions simulated 139347SAndreas.Sandberg@arm.comsim_ops 6404 # Number of ops (including micro ops) simulated 142810Srdreslin@umich.edusystem.physmem.bytes_read 34460 # Number of bytes read from this memory 152810Srdreslin@umich.edusystem.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory 162810Srdreslin@umich.edusystem.physmem.bytes_written 6696 # Number of bytes written to this memory 172810Srdreslin@umich.edusystem.physmem.num_reads 7599 # Number of read requests responded to by this memory 182810Srdreslin@umich.edusystem.physmem.num_writes 865 # Number of write requests responded to by this memory 192810Srdreslin@umich.edusystem.physmem.num_other 0 # Number of other requests responded to by this memory 202810Srdreslin@umich.edusystem.physmem.bw_read 100555008 # Total read bandwidth from this memory (bytes/s) 212810Srdreslin@umich.edusystem.physmem.bw_inst_read 74864750 # Instruction read bandwidth from this memory (bytes/s) 222810Srdreslin@umich.edusystem.physmem.bw_write 19539069 # Write bandwidth from this memory (bytes/s) 232810Srdreslin@umich.edusystem.physmem.bw_total 120094077 # Total bandwidth to/from this memory (bytes/s) 242810Srdreslin@umich.edusystem.cpu.dtb.fetch_hits 0 # ITB hits 252810Srdreslin@umich.edusystem.cpu.dtb.fetch_misses 0 # ITB misses 262810Srdreslin@umich.edusystem.cpu.dtb.fetch_acv 0 # ITB acv 272810Srdreslin@umich.edusystem.cpu.dtb.fetch_accesses 0 # ITB accesses 282810Srdreslin@umich.edusystem.cpu.dtb.read_hits 1185 # DTB read hits 292810Srdreslin@umich.edusystem.cpu.dtb.read_misses 7 # DTB read misses 302810Srdreslin@umich.edusystem.cpu.dtb.read_acv 0 # DTB read access violations 312810Srdreslin@umich.edusystem.cpu.dtb.read_accesses 1192 # DTB read accesses 322810Srdreslin@umich.edusystem.cpu.dtb.write_hits 865 # DTB write hits 332810Srdreslin@umich.edusystem.cpu.dtb.write_misses 3 # DTB write misses 342810Srdreslin@umich.edusystem.cpu.dtb.write_acv 0 # DTB write access violations 352810Srdreslin@umich.edusystem.cpu.dtb.write_accesses 868 # DTB write accesses 362810Srdreslin@umich.edusystem.cpu.dtb.data_hits 2050 # DTB hits 372810Srdreslin@umich.edusystem.cpu.dtb.data_misses 10 # DTB misses 382810Srdreslin@umich.edusystem.cpu.dtb.data_acv 0 # DTB access violations 392810Srdreslin@umich.edusystem.cpu.dtb.data_accesses 2060 # DTB accesses 402810Srdreslin@umich.edusystem.cpu.itb.fetch_hits 6415 # ITB hits 412810Srdreslin@umich.edusystem.cpu.itb.fetch_misses 17 # ITB misses 422810Srdreslin@umich.edusystem.cpu.itb.fetch_acv 0 # ITB acv 432810Srdreslin@umich.edusystem.cpu.itb.fetch_accesses 6432 # ITB accesses 442810Srdreslin@umich.edusystem.cpu.itb.read_hits 0 # DTB read hits 452810Srdreslin@umich.edusystem.cpu.itb.read_misses 0 # DTB read misses 462810Srdreslin@umich.edusystem.cpu.itb.read_acv 0 # DTB read access violations 472810Srdreslin@umich.edusystem.cpu.itb.read_accesses 0 # DTB read accesses 486216Snate@binkert.orgsystem.cpu.itb.write_hits 0 # DTB write hits 496216Snate@binkert.orgsystem.cpu.itb.write_misses 0 # DTB write misses 502810Srdreslin@umich.edusystem.cpu.itb.write_acv 0 # DTB write access violations 512810Srdreslin@umich.edusystem.cpu.itb.write_accesses 0 # DTB write accesses 522810Srdreslin@umich.edusystem.cpu.itb.data_hits 0 # DTB hits 536216Snate@binkert.orgsystem.cpu.itb.data_misses 0 # DTB misses 548229Snate@binkert.orgsystem.cpu.itb.data_acv 0 # DTB access violations 555338Sstever@gmail.comsystem.cpu.itb.data_accesses 0 # DTB accesses 562810Srdreslin@umich.edusystem.cpu.workload.num_syscalls 17 # Number of system calls 579796Sprakash.ramrakhyani@arm.comsystem.cpu.numCycles 342698 # number of cpu cycles simulated 582810Srdreslin@umich.edusystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 592810Srdreslin@umich.edusystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 602810Srdreslin@umich.edusystem.cpu.committedInsts 6404 # Number of instructions committed 612810Srdreslin@umich.edusystem.cpu.committedOps 6404 # Number of ops (including micro ops) committed 622810Srdreslin@umich.edusystem.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses 632810Srdreslin@umich.edusystem.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 642810Srdreslin@umich.edusystem.cpu.num_func_calls 251 # number of times a function call or return occured 652810Srdreslin@umich.edusystem.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls 662810Srdreslin@umich.edusystem.cpu.num_int_insts 6331 # number of integer instructions 672810Srdreslin@umich.edusystem.cpu.num_fp_insts 10 # number of float instructions 682810Srdreslin@umich.edusystem.cpu.num_int_register_reads 8304 # number of times the integer registers were read 692810Srdreslin@umich.edusystem.cpu.num_int_register_writes 4581 # number of times the integer registers were written 702810Srdreslin@umich.edusystem.cpu.num_fp_register_reads 8 # number of times the floating registers were read 712810Srdreslin@umich.edusystem.cpu.num_fp_register_writes 2 # number of times the floating registers were written 722810Srdreslin@umich.edusystem.cpu.num_mem_refs 2060 # number of memory refs 732810Srdreslin@umich.edusystem.cpu.num_load_insts 1192 # Number of load instructions 742810Srdreslin@umich.edusystem.cpu.num_store_insts 868 # Number of store instructions 752810Srdreslin@umich.edusystem.cpu.num_idle_cycles 0 # Number of idle cycles 762810Srdreslin@umich.edusystem.cpu.num_busy_cycles 342698 # Number of busy cycles 772810Srdreslin@umich.edusystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 782810Srdreslin@umich.edusystem.cpu.idle_fraction 0 # Percentage of idle cycles 792810Srdreslin@umich.edu 802810Srdreslin@umich.edu---------- End Simulation Statistics ---------- 812810Srdreslin@umich.edu