stats.txt revision 11687:b3d5f0e9e258
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000112 # Number of seconds simulated 4sim_ticks 112490 # Number of ticks simulated 5final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 109209 # Simulator instruction rate (inst/s) 8host_op_rate 109187 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1917933 # Simulator tick rate (ticks/s) 10host_mem_usage 416076 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 6403 # Number of instructions simulated 13sim_ops 6403 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 17system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory 19system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory 20system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory 21system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory 22system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory 23system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory 24system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory 25system.mem_ctrls.bw_read::ruby.dir_cntrl0 984834207 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_read::total 984834207 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::ruby.dir_cntrl0 982558450 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_write::total 982558450 # Write bandwidth from this memory (bytes/s) 29system.mem_ctrls.bw_total::ruby.dir_cntrl0 1967392657 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.bw_total::total 1967392657 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrls.readReqs 1731 # Number of read requests accepted 32system.mem_ctrls.writeReqs 1727 # Number of write requests accepted 33system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue 34system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue 35system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM 36system.mem_ctrls.bytesReadWrQ 54080 # Total number of bytes read from write queue 37system.mem_ctrls.bytesWritten 57088 # Total number of bytes written to DRAM 38system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side 39system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side 40system.mem_ctrls.servicedByWrQ 845 # Number of DRAM read bursts serviced by the write queue 41system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one 42system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 43system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::1 50 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::2 70 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::3 63 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::4 108 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::11 36 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::13 270 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::14 81 # Per bank write bursts 58system.mem_ctrls.perBankRdBursts::15 24 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::0 82 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::3 60 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::10 50 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::11 33 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts 74system.mem_ctrls.perBankWrBursts::15 24 # Per bank write bursts 75system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 76system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 77system.mem_ctrls.totGap 112412 # Total gap between requests 78system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 84system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2) 85system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 91system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2) 92system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 123system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::21 60 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 187system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 188system.mem_ctrls.bytesPerActivate::samples 264 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::mean 424 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::gmean 260.079273 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::stdev 372.426347 # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::0-127 66 25.00% 25.00% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::128-255 58 21.97% 46.97% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::256-383 27 10.23% 57.20% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::384-511 16 6.06% 63.26% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::512-639 17 6.44% 69.70% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::640-767 8 3.03% 72.73% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::768-895 12 4.55% 77.27% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::896-1023 10 3.79% 81.06% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::1024-1151 50 18.94% 100.00% # Bytes accessed per row activation 201system.mem_ctrls.bytesPerActivate::total 264 # Bytes accessed per row activation 202system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::mean 15.818182 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::gmean 15.638991 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::stdev 2.938196 # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::12-13 3 5.45% 5.45% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::14-15 24 43.64% 49.09% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::16-17 23 41.82% 90.91% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes 211system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes 212system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::mean 16.218182 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::gmean 16.206001 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::stdev 0.658025 # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::16 49 89.09% 89.09% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::17 1 1.82% 90.91% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::18 4 7.27% 98.18% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads 220system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads 221system.mem_ctrls.totQLat 16225 # Total ticks spent queuing 222system.mem_ctrls.totMemAccLat 33059 # Total ticks spent from burst creation until serviced by the DRAM 223system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers 224system.mem_ctrls.avgQLat 18.31 # Average queueing delay per DRAM burst 225system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 226system.mem_ctrls.avgMemAccLat 37.31 # Average memory access latency per DRAM burst 227system.mem_ctrls.avgRdBW 504.08 # Average DRAM read bandwidth in MiByte/s 228system.mem_ctrls.avgWrBW 507.49 # Average achieved write bandwidth in MiByte/s 229system.mem_ctrls.avgRdBWSys 984.83 # Average system read bandwidth in MiByte/s 230system.mem_ctrls.avgWrBWSys 982.56 # Average system write bandwidth in MiByte/s 231system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 232system.mem_ctrls.busUtil 7.90 # Data bus utilization in percentage 233system.mem_ctrls.busUtilRead 3.94 # Data bus utilization in percentage for reads 234system.mem_ctrls.busUtilWrite 3.96 # Data bus utilization in percentage for writes 235system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 236system.mem_ctrls.avgWrQLen 26.10 # Average write queue length when enqueuing 237system.mem_ctrls.readRowHits 674 # Number of row buffer hits during reads 238system.mem_ctrls.writeRowHits 833 # Number of row buffer hits during writes 239system.mem_ctrls.readRowHitRate 76.07 # Row buffer hit rate for reads 240system.mem_ctrls.writeRowHitRate 90.15 # Row buffer hit rate for writes 241system.mem_ctrls.avgGap 32.51 # Average gap between requests 242system.mem_ctrls.pageHitRate 83.26 # Row buffer hit rate, read and write combined 243system.mem_ctrls_0.actEnergy 735420 # Energy for activate commands per rank (pJ) 244system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) 245system.mem_ctrls_0.readEnergy 4581024 # Energy for read commands per rank (pJ) 246system.mem_ctrls_0.writeEnergy 3532896 # Energy for write commands per rank (pJ) 247system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 248system.mem_ctrls_0.actBackEnergy 13923048 # Energy for active background per rank (pJ) 249system.mem_ctrls_0.preBackEnergy 195072 # Energy for precharge background per rank (pJ) 250system.mem_ctrls_0.actPowerDownEnergy 30921360 # Energy for active power-down per rank (pJ) 251system.mem_ctrls_0.prePowerDownEnergy 5237376 # Energy for precharge power-down per rank (pJ) 252system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 253system.mem_ctrls_0.totalEnergy 68117556 # Total energy per rank (pJ) 254system.mem_ctrls_0.averagePower 605.543213 # Core power per rank (mW) 255system.mem_ctrls_0.totalIdleTime 81406 # Total Idle time Per DRAM Rank 256system.mem_ctrls_0.memoryStateTime::IDLE 88 # Time in different power states 257system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states 258system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states 259system.mem_ctrls_0.memoryStateTime::PRE_PDN 13639 # Time in different power states 260system.mem_ctrls_0.memoryStateTime::ACT 27313 # Time in different power states 261system.mem_ctrls_0.memoryStateTime::ACT_PDN 67810 # Time in different power states 262system.mem_ctrls_1.actEnergy 1199520 # Energy for activate commands per rank (pJ) 263system.mem_ctrls_1.preEnergy 633696 # Energy for precharge commands per rank (pJ) 264system.mem_ctrls_1.readEnergy 5540640 # Energy for read commands per rank (pJ) 265system.mem_ctrls_1.writeEnergy 3917088 # Energy for write commands per rank (pJ) 266system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 267system.mem_ctrls_1.actBackEnergy 12524952 # Energy for active background per rank (pJ) 268system.mem_ctrls_1.preBackEnergy 314880 # Energy for precharge background per rank (pJ) 269system.mem_ctrls_1.actPowerDownEnergy 33139344 # Energy for active power-down per rank (pJ) 270system.mem_ctrls_1.prePowerDownEnergy 4427136 # Energy for precharge power-down per rank (pJ) 271system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 272system.mem_ctrls_1.totalEnergy 70302216 # Total energy per rank (pJ) 273system.mem_ctrls_1.averagePower 624.964139 # Core power per rank (mW) 274system.mem_ctrls_1.totalIdleTime 83983 # Total Idle time Per DRAM Rank 275system.mem_ctrls_1.memoryStateTime::IDLE 260 # Time in different power states 276system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states 277system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states 278system.mem_ctrls_1.memoryStateTime::PRE_PDN 11529 # Time in different power states 279system.mem_ctrls_1.memoryStateTime::ACT 24387 # Time in different power states 280system.mem_ctrls_1.memoryStateTime::ACT_PDN 72674 # Time in different power states 281system.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 282system.cpu.clk_domain.clock 1 # Clock period in ticks 283system.cpu.dtb.fetch_hits 0 # ITB hits 284system.cpu.dtb.fetch_misses 0 # ITB misses 285system.cpu.dtb.fetch_acv 0 # ITB acv 286system.cpu.dtb.fetch_accesses 0 # ITB accesses 287system.cpu.dtb.read_hits 1185 # DTB read hits 288system.cpu.dtb.read_misses 7 # DTB read misses 289system.cpu.dtb.read_acv 0 # DTB read access violations 290system.cpu.dtb.read_accesses 1192 # DTB read accesses 291system.cpu.dtb.write_hits 865 # DTB write hits 292system.cpu.dtb.write_misses 3 # DTB write misses 293system.cpu.dtb.write_acv 0 # DTB write access violations 294system.cpu.dtb.write_accesses 868 # DTB write accesses 295system.cpu.dtb.data_hits 2050 # DTB hits 296system.cpu.dtb.data_misses 10 # DTB misses 297system.cpu.dtb.data_acv 0 # DTB access violations 298system.cpu.dtb.data_accesses 2060 # DTB accesses 299system.cpu.itb.fetch_hits 6414 # ITB hits 300system.cpu.itb.fetch_misses 17 # ITB misses 301system.cpu.itb.fetch_acv 0 # ITB acv 302system.cpu.itb.fetch_accesses 6431 # ITB accesses 303system.cpu.itb.read_hits 0 # DTB read hits 304system.cpu.itb.read_misses 0 # DTB read misses 305system.cpu.itb.read_acv 0 # DTB read access violations 306system.cpu.itb.read_accesses 0 # DTB read accesses 307system.cpu.itb.write_hits 0 # DTB write hits 308system.cpu.itb.write_misses 0 # DTB write misses 309system.cpu.itb.write_acv 0 # DTB write access violations 310system.cpu.itb.write_accesses 0 # DTB write accesses 311system.cpu.itb.data_hits 0 # DTB hits 312system.cpu.itb.data_misses 0 # DTB misses 313system.cpu.itb.data_acv 0 # DTB access violations 314system.cpu.itb.data_accesses 0 # DTB accesses 315system.cpu.workload.num_syscalls 17 # Number of system calls 316system.cpu.pwrStateResidencyTicks::ON 112490 # Cumulative time (in ticks) in various power states 317system.cpu.numCycles 112490 # number of cpu cycles simulated 318system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 319system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 320system.cpu.committedInsts 6403 # Number of instructions committed 321system.cpu.committedOps 6403 # Number of ops (including micro ops) committed 322system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses 323system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 324system.cpu.num_func_calls 251 # number of times a function call or return occured 325system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls 326system.cpu.num_int_insts 6329 # number of integer instructions 327system.cpu.num_fp_insts 10 # number of float instructions 328system.cpu.num_int_register_reads 8297 # number of times the integer registers were read 329system.cpu.num_int_register_writes 4575 # number of times the integer registers were written 330system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 331system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 332system.cpu.num_mem_refs 2060 # number of memory refs 333system.cpu.num_load_insts 1192 # Number of load instructions 334system.cpu.num_store_insts 868 # Number of store instructions 335system.cpu.num_idle_cycles 0 # Number of idle cycles 336system.cpu.num_busy_cycles 112490 # Number of busy cycles 337system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 338system.cpu.idle_fraction 0 # Percentage of idle cycles 339system.cpu.Branches 1056 # Number of branches fetched 340system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 341system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction 342system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction 343system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction 344system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction 345system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction 346system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction 347system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction 348system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction 349system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction 350system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction 351system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction 352system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction 353system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction 354system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction 355system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction 356system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction 357system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction 358system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction 359system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction 360system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction 361system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction 362system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction 363system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction 364system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction 365system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction 366system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction 367system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction 368system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction 369system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction 370system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction 371system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction 372system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction 373system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction 374system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction 375system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction 376system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 377system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 378system.cpu.op_class::total 6413 # Class of executed instruction 379system.ruby.clk_domain.clock 1 # Clock period in ticks 380system.ruby.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 381system.ruby.delayHist::bucket_size 1 # delay histogram for all message 382system.ruby.delayHist::max_bucket 9 # delay histogram for all message 383system.ruby.delayHist::samples 3458 # delay histogram for all message 384system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 385system.ruby.delayHist::total 3458 # delay histogram for all message 386system.ruby.outstanding_req_hist_seqr::bucket_size 1 387system.ruby.outstanding_req_hist_seqr::max_bucket 9 388system.ruby.outstanding_req_hist_seqr::samples 8464 389system.ruby.outstanding_req_hist_seqr::mean 1 390system.ruby.outstanding_req_hist_seqr::gmean 1 391system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 392system.ruby.outstanding_req_hist_seqr::total 8464 393system.ruby.latency_hist_seqr::bucket_size 64 394system.ruby.latency_hist_seqr::max_bucket 639 395system.ruby.latency_hist_seqr::samples 8463 396system.ruby.latency_hist_seqr::mean 12.291977 397system.ruby.latency_hist_seqr::gmean 2.221869 398system.ruby.latency_hist_seqr::stdev 27.407806 399system.ruby.latency_hist_seqr | 7608 89.90% 89.90% | 798 9.43% 99.33% | 40 0.47% 99.80% | 5 0.06% 99.86% | 6 0.07% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 400system.ruby.latency_hist_seqr::total 8463 401system.ruby.hit_latency_hist_seqr::bucket_size 1 402system.ruby.hit_latency_hist_seqr::max_bucket 9 403system.ruby.hit_latency_hist_seqr::samples 6732 404system.ruby.hit_latency_hist_seqr::mean 1 405system.ruby.hit_latency_hist_seqr::gmean 1 406system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 407system.ruby.hit_latency_hist_seqr::total 6732 408system.ruby.miss_latency_hist_seqr::bucket_size 64 409system.ruby.miss_latency_hist_seqr::max_bucket 639 410system.ruby.miss_latency_hist_seqr::samples 1731 411system.ruby.miss_latency_hist_seqr::mean 56.207395 412system.ruby.miss_latency_hist_seqr::gmean 49.560362 413system.ruby.miss_latency_hist_seqr::stdev 35.333412 414system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 415system.ruby.miss_latency_hist_seqr::total 1731 416system.ruby.Directory.incomplete_times_seqr 1730 417system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 418system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits 419system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses 420system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses 421system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 422system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 423system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 424system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 425system.ruby.network.routers0.percent_links_utilized 7.685128 426system.ruby.network.routers0.msg_count.Control::2 1731 427system.ruby.network.routers0.msg_count.Data::2 1727 428system.ruby.network.routers0.msg_count.Response_Data::4 1731 429system.ruby.network.routers0.msg_count.Writeback_Control::3 1727 430system.ruby.network.routers0.msg_bytes.Control::2 13848 431system.ruby.network.routers0.msg_bytes.Data::2 124344 432system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 433system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 434system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 435system.ruby.network.routers1.percent_links_utilized 7.685128 436system.ruby.network.routers1.msg_count.Control::2 1731 437system.ruby.network.routers1.msg_count.Data::2 1727 438system.ruby.network.routers1.msg_count.Response_Data::4 1731 439system.ruby.network.routers1.msg_count.Writeback_Control::3 1727 440system.ruby.network.routers1.msg_bytes.Control::2 13848 441system.ruby.network.routers1.msg_bytes.Data::2 124344 442system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 443system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 444system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 445system.ruby.network.routers2.percent_links_utilized 7.685128 446system.ruby.network.routers2.msg_count.Control::2 1731 447system.ruby.network.routers2.msg_count.Data::2 1727 448system.ruby.network.routers2.msg_count.Response_Data::4 1731 449system.ruby.network.routers2.msg_count.Writeback_Control::3 1727 450system.ruby.network.routers2.msg_bytes.Control::2 13848 451system.ruby.network.routers2.msg_bytes.Data::2 124344 452system.ruby.network.routers2.msg_bytes.Response_Data::4 124632 453system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816 454system.ruby.network.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 455system.ruby.network.msg_count.Control 5193 456system.ruby.network.msg_count.Data 5181 457system.ruby.network.msg_count.Response_Data 5193 458system.ruby.network.msg_count.Writeback_Control 5181 459system.ruby.network.msg_byte.Control 41544 460system.ruby.network.msg_byte.Data 373032 461system.ruby.network.msg_byte.Response_Data 373896 462system.ruby.network.msg_byte.Writeback_Control 41448 463system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states 464system.ruby.network.routers0.throttle0.link_utilization 7.692239 465system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731 466system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727 467system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632 468system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816 469system.ruby.network.routers0.throttle1.link_utilization 7.678016 470system.ruby.network.routers0.throttle1.msg_count.Control::2 1731 471system.ruby.network.routers0.throttle1.msg_count.Data::2 1727 472system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848 473system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344 474system.ruby.network.routers1.throttle0.link_utilization 7.678016 475system.ruby.network.routers1.throttle0.msg_count.Control::2 1731 476system.ruby.network.routers1.throttle0.msg_count.Data::2 1727 477system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848 478system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344 479system.ruby.network.routers1.throttle1.link_utilization 7.692239 480system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731 481system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727 482system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632 483system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816 484system.ruby.network.routers2.throttle0.link_utilization 7.692239 485system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731 486system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727 487system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632 488system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816 489system.ruby.network.routers2.throttle1.link_utilization 7.678016 490system.ruby.network.routers2.throttle1.msg_count.Control::2 1731 491system.ruby.network.routers2.throttle1.msg_count.Data::2 1727 492system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848 493system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344 494system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 495system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 496system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1 497system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 498system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1 499system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 500system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 501system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2 502system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 503system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2 504system.ruby.LD.latency_hist_seqr::bucket_size 64 505system.ruby.LD.latency_hist_seqr::max_bucket 639 506system.ruby.LD.latency_hist_seqr::samples 1185 507system.ruby.LD.latency_hist_seqr::mean 33.356118 508system.ruby.LD.latency_hist_seqr::gmean 10.708915 509system.ruby.LD.latency_hist_seqr::stdev 36.387225 510system.ruby.LD.latency_hist_seqr | 862 72.74% 72.74% | 301 25.40% 98.14% | 16 1.35% 99.49% | 3 0.25% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 511system.ruby.LD.latency_hist_seqr::total 1185 512system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 513system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 514system.ruby.LD.hit_latency_hist_seqr::samples 457 515system.ruby.LD.hit_latency_hist_seqr::mean 1 516system.ruby.LD.hit_latency_hist_seqr::gmean 1 517system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 518system.ruby.LD.hit_latency_hist_seqr::total 457 519system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 520system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 521system.ruby.LD.miss_latency_hist_seqr::samples 728 522system.ruby.LD.miss_latency_hist_seqr::mean 53.667582 523system.ruby.LD.miss_latency_hist_seqr::gmean 47.442261 524system.ruby.LD.miss_latency_hist_seqr::stdev 32.940895 525system.ruby.LD.miss_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 526system.ruby.LD.miss_latency_hist_seqr::total 728 527system.ruby.ST.latency_hist_seqr::bucket_size 32 528system.ruby.ST.latency_hist_seqr::max_bucket 319 529system.ruby.ST.latency_hist_seqr::samples 865 530system.ruby.ST.latency_hist_seqr::mean 17.479769 531system.ruby.ST.latency_hist_seqr::gmean 3.361529 532system.ruby.ST.latency_hist_seqr::stdev 31.340829 533system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 160 18.50% 86.94% | 102 11.79% 98.73% | 0 0.00% 98.73% | 4 0.46% 99.19% | 4 0.46% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% 534system.ruby.ST.latency_hist_seqr::total 865 535system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 536system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 537system.ruby.ST.hit_latency_hist_seqr::samples 592 538system.ruby.ST.hit_latency_hist_seqr::mean 1 539system.ruby.ST.hit_latency_hist_seqr::gmean 1 540system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 541system.ruby.ST.hit_latency_hist_seqr::total 592 542system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 543system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 544system.ruby.ST.miss_latency_hist_seqr::samples 273 545system.ruby.ST.miss_latency_hist_seqr::mean 53.216117 546system.ruby.ST.miss_latency_hist_seqr::gmean 46.594106 547system.ruby.ST.miss_latency_hist_seqr::stdev 35.315815 548system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% 549system.ruby.ST.miss_latency_hist_seqr::total 273 550system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 551system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 552system.ruby.IFETCH.latency_hist_seqr::samples 6413 553system.ruby.IFETCH.latency_hist_seqr::mean 7.699984 554system.ruby.IFETCH.latency_hist_seqr::gmean 1.571280 555system.ruby.IFETCH.latency_hist_seqr::stdev 22.534194 556system.ruby.IFETCH.latency_hist_seqr | 5994 93.47% 93.47% | 395 6.16% 99.63% | 16 0.25% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 557system.ruby.IFETCH.latency_hist_seqr::total 6413 558system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 559system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 560system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683 561system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 562system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 563system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 564system.ruby.IFETCH.hit_latency_hist_seqr::total 5683 565system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 566system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 567system.ruby.IFETCH.miss_latency_hist_seqr::samples 730 568system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.858904 569system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.975537 570system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.310775 571system.ruby.IFETCH.miss_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 572system.ruby.IFETCH.miss_latency_hist_seqr::total 730 573system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 574system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 575system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731 576system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.207395 577system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.560362 578system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.333412 579system.ruby.Directory.miss_mach_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 580system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731 581system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 582system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 583system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 584system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan 585system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 586system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 587system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 588system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 589system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 590system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan 591system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 592system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 593system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 594system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 595system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 596system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan 597system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 598system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 599system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 600system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 601system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 602system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 603system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 604system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan 605system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 606system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 607system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 608system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 609system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728 610system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.667582 611system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.442261 612system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.940895 613system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 614system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728 615system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 616system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 617system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273 618system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.216117 619system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.594106 620system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.315815 621system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% 622system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273 623system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 624system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 625system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730 626system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.858904 627system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.975537 628system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.310775 629system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 630system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730 631system.ruby.Directory_Controller.GETX 1731 0.00% 0.00% 632system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00% 633system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00% 634system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00% 635system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00% 636system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00% 637system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00% 638system.ruby.Directory_Controller.MI.Memory_Ack 1727 0.00% 0.00% 639system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% 640system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% 641system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% 642system.ruby.L1Cache_Controller.Data 1731 0.00% 0.00% 643system.ruby.L1Cache_Controller.Replacement 1727 0.00% 0.00% 644system.ruby.L1Cache_Controller.Writeback_Ack 1727 0.00% 0.00% 645system.ruby.L1Cache_Controller.I.Load 728 0.00% 0.00% 646system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% 647system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% 648system.ruby.L1Cache_Controller.M.Load 457 0.00% 0.00% 649system.ruby.L1Cache_Controller.M.Ifetch 5683 0.00% 0.00% 650system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% 651system.ruby.L1Cache_Controller.M.Replacement 1727 0.00% 0.00% 652system.ruby.L1Cache_Controller.MI.Writeback_Ack 1727 0.00% 0.00% 653system.ruby.L1Cache_Controller.IS.Data 1458 0.00% 0.00% 654system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% 655 656---------- End Simulation Statistics ---------- 657