config.ini revision 5509
12810Srdreslin@umich.edu[root] 212500Snikos.nikoleris@arm.comtype=Root 311051Sandreas.hansson@arm.comchildren=system 411051Sandreas.hansson@arm.comdummy=0 511051Sandreas.hansson@arm.com 611051Sandreas.hansson@arm.com[system] 711051Sandreas.hansson@arm.comtype=System 811051Sandreas.hansson@arm.comchildren=cpu membus physmem 911051Sandreas.hansson@arm.commem_mode=atomic 1011051Sandreas.hansson@arm.comphysmem=system.physmem 1111051Sandreas.hansson@arm.com 1211051Sandreas.hansson@arm.com[system.cpu] 1311051Sandreas.hansson@arm.comtype=AtomicSimpleCPU 1411051Sandreas.hansson@arm.comchildren=dtb itb tracer workload 1511051Sandreas.hansson@arm.comclock=500 162810Srdreslin@umich.educpu_id=0 172810Srdreslin@umich.edudefer_registration=false 182810Srdreslin@umich.edudtb=system.cpu.dtb 192810Srdreslin@umich.edufunction_trace=false 202810Srdreslin@umich.edufunction_trace_start=0 212810Srdreslin@umich.eduitb=system.cpu.itb 222810Srdreslin@umich.edumax_insts_all_threads=0 232810Srdreslin@umich.edumax_insts_any_thread=0 242810Srdreslin@umich.edumax_loads_all_threads=0 252810Srdreslin@umich.edumax_loads_any_thread=0 262810Srdreslin@umich.eduphase=0 272810Srdreslin@umich.eduprogress_interval=0 282810Srdreslin@umich.edusimulate_data_stalls=false 292810Srdreslin@umich.edusimulate_inst_stalls=false 302810Srdreslin@umich.edusystem=system 312810Srdreslin@umich.edutracer=system.cpu.tracer 322810Srdreslin@umich.eduwidth=1 332810Srdreslin@umich.eduworkload=system.cpu.workload 342810Srdreslin@umich.edudcache_port=system.membus.port[2] 352810Srdreslin@umich.eduicache_port=system.membus.port[1] 362810Srdreslin@umich.edu 372810Srdreslin@umich.edu[system.cpu.dtb] 382810Srdreslin@umich.edutype=AlphaDTB 392810Srdreslin@umich.edusize=64 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu[system.cpu.itb] 4211051Sandreas.hansson@arm.comtype=AlphaITB 4311051Sandreas.hansson@arm.comsize=48 442810Srdreslin@umich.edu 4511051Sandreas.hansson@arm.com[system.cpu.tracer] 4611051Sandreas.hansson@arm.comtype=ExeTracer 4712349Snikos.nikoleris@arm.com 482810Srdreslin@umich.edu[system.cpu.workload] 492810Srdreslin@umich.edutype=LiveProcess 502810Srdreslin@umich.educmd=hello 512810Srdreslin@umich.educwd= 5211051Sandreas.hansson@arm.comegid=100 532810Srdreslin@umich.eduenv= 542810Srdreslin@umich.edueuid=100 5511051Sandreas.hansson@arm.comexecutable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 562810Srdreslin@umich.edugid=100 5712724Snikos.nikoleris@arm.cominput=cin 5812724Snikos.nikoleris@arm.commax_stack_size=67108864 5912724Snikos.nikoleris@arm.comoutput=cout 6012334Sgabeblack@google.compid=100 6112724Snikos.nikoleris@arm.comppid=99 6211051Sandreas.hansson@arm.comsimpoint=0 6311051Sandreas.hansson@arm.comsystem=system 6411051Sandreas.hansson@arm.comuid=100 6511288Ssteve.reinhardt@amd.com 6612724Snikos.nikoleris@arm.com[system.membus] 6711051Sandreas.hansson@arm.comtype=Bus 6811051Sandreas.hansson@arm.comblock_size=64 6912724Snikos.nikoleris@arm.combus_id=0 7012724Snikos.nikoleris@arm.comclock=1000 7112724Snikos.nikoleris@arm.comheader_cycles=1 7212724Snikos.nikoleris@arm.comresponder_set=false 7311051Sandreas.hansson@arm.comwidth=64 7411053Sandreas.hansson@arm.comport=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port 7511053Sandreas.hansson@arm.com 7612724Snikos.nikoleris@arm.com[system.physmem] 7711051Sandreas.hansson@arm.comtype=PhysicalMemory 7811051Sandreas.hansson@arm.comfile= 7911051Sandreas.hansson@arm.comlatency=1 8011051Sandreas.hansson@arm.comlatency_var=0 8111601Sandreas.hansson@arm.comnull=false 8211601Sandreas.hansson@arm.comrange=0:134217727 8311051Sandreas.hansson@arm.comzero=false 8412724Snikos.nikoleris@arm.comport=system.membus.port[0] 8511051Sandreas.hansson@arm.com 8612724Snikos.nikoleris@arm.com