stats.txt revision 9978
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21065000 # Number of ticks simulated 5final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 31290 # Simulator instruction rate (inst/s) 8host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 103426086 # Simulator tick rate (ticks/s) 10host_mem_usage 226120 # Number of bytes of host memory used 11host_seconds 0.20 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 16system.physmem.bytes_read::total 31168 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 487 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 488 # Number of read requests accepted 31system.physmem.writeReqs 0 # Number of write requests accepted 32system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue 33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 34system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM 35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 37system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side 38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.physmem.perBankRdBursts::0 69 # Per bank write bursts 43system.physmem.perBankRdBursts::1 34 # Per bank write bursts 44system.physmem.perBankRdBursts::2 32 # Per bank write bursts 45system.physmem.perBankRdBursts::3 47 # Per bank write bursts 46system.physmem.perBankRdBursts::4 43 # Per bank write bursts 47system.physmem.perBankRdBursts::5 21 # Per bank write bursts 48system.physmem.perBankRdBursts::6 1 # Per bank write bursts 49system.physmem.perBankRdBursts::7 3 # Per bank write bursts 50system.physmem.perBankRdBursts::8 0 # Per bank write bursts 51system.physmem.perBankRdBursts::9 1 # Per bank write bursts 52system.physmem.perBankRdBursts::10 23 # Per bank write bursts 53system.physmem.perBankRdBursts::11 24 # Per bank write bursts 54system.physmem.perBankRdBursts::12 14 # Per bank write bursts 55system.physmem.perBankRdBursts::13 119 # Per bank write bursts 56system.physmem.perBankRdBursts::14 45 # Per bank write bursts 57system.physmem.perBankRdBursts::15 12 # Per bank write bursts 58system.physmem.perBankWrBursts::0 0 # Per bank write bursts 59system.physmem.perBankWrBursts::1 0 # Per bank write bursts 60system.physmem.perBankWrBursts::2 0 # Per bank write bursts 61system.physmem.perBankWrBursts::3 0 # Per bank write bursts 62system.physmem.perBankWrBursts::4 0 # Per bank write bursts 63system.physmem.perBankWrBursts::5 0 # Per bank write bursts 64system.physmem.perBankWrBursts::6 0 # Per bank write bursts 65system.physmem.perBankWrBursts::7 0 # Per bank write bursts 66system.physmem.perBankWrBursts::8 0 # Per bank write bursts 67system.physmem.perBankWrBursts::9 0 # Per bank write bursts 68system.physmem.perBankWrBursts::10 0 # Per bank write bursts 69system.physmem.perBankWrBursts::11 0 # Per bank write bursts 70system.physmem.perBankWrBursts::12 0 # Per bank write bursts 71system.physmem.perBankWrBursts::13 0 # Per bank write bursts 72system.physmem.perBankWrBursts::14 0 # Per bank write bursts 73system.physmem.perBankWrBursts::15 0 # Per bank write bursts 74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 76system.physmem.totGap 21032000 # Total gap between requests 77system.physmem.readPktSize::0 0 # Read request sizes (log2) 78system.physmem.readPktSize::1 0 # Read request sizes (log2) 79system.physmem.readPktSize::2 0 # Read request sizes (log2) 80system.physmem.readPktSize::3 0 # Read request sizes (log2) 81system.physmem.readPktSize::4 0 # Read request sizes (log2) 82system.physmem.readPktSize::5 0 # Read request sizes (log2) 83system.physmem.readPktSize::6 488 # Read request sizes (log2) 84system.physmem.writePktSize::0 0 # Write request sizes (log2) 85system.physmem.writePktSize::1 0 # Write request sizes (log2) 86system.physmem.writePktSize::2 0 # Write request sizes (log2) 87system.physmem.writePktSize::3 0 # Write request sizes (log2) 88system.physmem.writePktSize::4 0 # Write request sizes (log2) 89system.physmem.writePktSize::5 0 # Write request sizes (log2) 90system.physmem.writePktSize::6 0 # Write request sizes (log2) 91system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 155system.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation 157system.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation 158system.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation 159system.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation 177system.physmem.totQLat 3258750 # Total ticks spent queuing 178system.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM 179system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers 180system.physmem.totBankLat 7590000 # Total ticks spent accessing banks 181system.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst 182system.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst 183system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 184system.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst 185system.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s 186system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 187system.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s 188system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 189system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 190system.physmem.busUtil 11.58 # Data bus utilization in percentage 191system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads 192system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 193system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing 194system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 195system.physmem.readRowHits 403 # Number of row buffer hits during reads 196system.physmem.writeRowHits 0 # Number of row buffer hits during writes 197system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads 198system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 199system.physmem.avgGap 43098.36 # Average gap between requests 200system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined 201system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state 202system.membus.throughput 1479610729 # Throughput (bytes/s) 203system.membus.trans_dist::ReadReq 415 # Transaction distribution 204system.membus.trans_dist::ReadResp 414 # Transaction distribution 205system.membus.trans_dist::ReadExReq 73 # Transaction distribution 206system.membus.trans_dist::ReadExResp 73 # Transaction distribution 207system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 208system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 209system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 210system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 211system.membus.data_through_bus 31168 # Total data (bytes) 212system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 213system.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks) 214system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 215system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) 216system.membus.respLayer1.utilization 21.6 # Layer utilization (%) 217system.cpu.branchPred.lookups 2884 # Number of BP lookups 218system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted 219system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect 220system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups 221system.cpu.branchPred.BTBHits 756 # Number of BTB hits 222system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 223system.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage 224system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. 225system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 226system.cpu.dtb.fetch_hits 0 # ITB hits 227system.cpu.dtb.fetch_misses 0 # ITB misses 228system.cpu.dtb.fetch_acv 0 # ITB acv 229system.cpu.dtb.fetch_accesses 0 # ITB accesses 230system.cpu.dtb.read_hits 2076 # DTB read hits 231system.cpu.dtb.read_misses 47 # DTB read misses 232system.cpu.dtb.read_acv 0 # DTB read access violations 233system.cpu.dtb.read_accesses 2123 # DTB read accesses 234system.cpu.dtb.write_hits 1063 # DTB write hits 235system.cpu.dtb.write_misses 31 # DTB write misses 236system.cpu.dtb.write_acv 0 # DTB write access violations 237system.cpu.dtb.write_accesses 1094 # DTB write accesses 238system.cpu.dtb.data_hits 3139 # DTB hits 239system.cpu.dtb.data_misses 78 # DTB misses 240system.cpu.dtb.data_acv 0 # DTB access violations 241system.cpu.dtb.data_accesses 3217 # DTB accesses 242system.cpu.itb.fetch_hits 2382 # ITB hits 243system.cpu.itb.fetch_misses 39 # ITB misses 244system.cpu.itb.fetch_acv 0 # ITB acv 245system.cpu.itb.fetch_accesses 2421 # ITB accesses 246system.cpu.itb.read_hits 0 # DTB read hits 247system.cpu.itb.read_misses 0 # DTB read misses 248system.cpu.itb.read_acv 0 # DTB read access violations 249system.cpu.itb.read_accesses 0 # DTB read accesses 250system.cpu.itb.write_hits 0 # DTB write hits 251system.cpu.itb.write_misses 0 # DTB write misses 252system.cpu.itb.write_acv 0 # DTB write access violations 253system.cpu.itb.write_accesses 0 # DTB write accesses 254system.cpu.itb.data_hits 0 # DTB hits 255system.cpu.itb.data_misses 0 # DTB misses 256system.cpu.itb.data_acv 0 # DTB access violations 257system.cpu.itb.data_accesses 0 # DTB accesses 258system.cpu.workload.num_syscalls 17 # Number of system calls 259system.cpu.numCycles 42131 # number of cpu cycles simulated 260system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 261system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 262system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss 263system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed 264system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered 265system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken 266system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked 267system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing 268system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked 269system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 270system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps 271system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched 272system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed 273system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle 291system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle 292system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle 293system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked 294system.cpu.decode.RunCycles 2764 # Number of cycles decode is running 295system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking 296system.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing 297system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch 298system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 299system.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode 300system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 301system.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing 302system.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle 303system.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking 304system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst 305system.cpu.rename.RunCycles 2623 # Number of cycles rename is running 306system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking 307system.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename 308system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 309system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 310system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full 311system.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed 312system.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made 313system.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups 314system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 315system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 316system.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing 317system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 318system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed 319system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer 320system.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit. 321system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. 322system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 323system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 324system.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec) 325system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ 326system.cpu.iq.iqInstsIssued 10771 # Number of instructions issued 327system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 328system.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling 329system.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph 330system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 331system.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle 348system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 349system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available 350system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available 351system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available 378system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available 379system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available 380system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 381system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 382system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 383system.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued 384system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued 385system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued 412system.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued 413system.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued 414system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 416system.cpu.iq.FU_type_0::total 10771 # Type of FU issued 417system.cpu.iq.rate 0.255655 # Inst issue rate 418system.cpu.iq.fu_busy_cnt 112 # FU busy when requested 419system.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst) 420system.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads 421system.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes 422system.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses 423system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 424system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 425system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 426system.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses 427system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 428system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 429system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 430system.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed 431system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 432system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 433system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed 434system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 435system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 436system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 437system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked 438system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 439system.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing 440system.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking 441system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking 442system.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ 443system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch 444system.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions 445system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions 446system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 447system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 448system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 449system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 450system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly 451system.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly 452system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute 453system.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions 454system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed 455system.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute 456system.cpu.iew.exec_swp 0 # number of swp insts executed 457system.cpu.iew.exec_nop 89 # number of nop insts executed 458system.cpu.iew.exec_refs 3230 # number of memory reference insts executed 459system.cpu.iew.exec_branches 1588 # Number of branches executed 460system.cpu.iew.exec_stores 1096 # Number of stores executed 461system.cpu.iew.exec_rate 0.238945 # Inst execution rate 462system.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit 463system.cpu.iew.wb_count 9608 # cumulative count of insts written-back 464system.cpu.iew.wb_producers 5048 # num instructions producing a value 465system.cpu.iew.wb_consumers 6764 # num instructions consuming a value 466system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 467system.cpu.iew.wb_rate 0.228051 # insts written-back per cycle 468system.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back 469system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 470system.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit 471system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 472system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted 473system.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle 490system.cpu.commit.committedInsts 6389 # Number of instructions committed 491system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 492system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 493system.cpu.commit.refs 2048 # Number of memory references committed 494system.cpu.commit.loads 1183 # Number of loads committed 495system.cpu.commit.membars 0 # Number of memory barriers committed 496system.cpu.commit.branches 1050 # Number of branches committed 497system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 498system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 499system.cpu.commit.function_calls 127 # Number of function calls committed. 500system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached 501system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 502system.cpu.rob.rob_reads 26469 # The number of ROB reads 503system.cpu.rob.rob_writes 27366 # The number of ROB writes 504system.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself 505system.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling 506system.cpu.committedInsts 6372 # Number of Instructions Simulated 507system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 508system.cpu.committedInsts_total 6372 # Number of Instructions Simulated 509system.cpu.cpi 6.611896 # CPI: Cycles Per Instruction 510system.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads 511system.cpu.ipc 0.151243 # IPC: Instructions Per Cycle 512system.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads 513system.cpu.int_regfile_reads 12780 # number of integer regfile reads 514system.cpu.int_regfile_writes 7264 # number of integer regfile writes 515system.cpu.fp_regfile_reads 8 # number of floating regfile reads 516system.cpu.fp_regfile_writes 2 # number of floating regfile writes 517system.cpu.misc_regfile_reads 1 # number of misc regfile reads 518system.cpu.misc_regfile_writes 1 # number of misc regfile writes 519system.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s) 520system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 521system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 522system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 523system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 524system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 525system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 526system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 527system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 528system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 529system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 530system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 531system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 532system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 533system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 534system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) 535system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) 536system.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks) 537system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 538system.cpu.icache.tags.replacements 0 # number of replacements 539system.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use 540system.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks. 541system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 542system.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks. 543system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 544system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor 545system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy 546system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy 547system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits 548system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits 549system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits 550system.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits 551system.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits 552system.cpu.icache.overall_hits::total 1893 # number of overall hits 553system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses 554system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses 555system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses 556system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses 557system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses 558system.cpu.icache.overall_misses::total 489 # number of overall misses 559system.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles 560system.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles 561system.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles 562system.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles 563system.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles 564system.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles 565system.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses) 566system.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses) 567system.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses 568system.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses 569system.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses 570system.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses 571system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses 572system.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses 573system.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses 574system.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses 575system.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses 576system.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses 577system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency 578system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency 579system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency 580system.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency 581system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency 582system.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency 583system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 584system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 585system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 586system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 587system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 588system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 589system.cpu.icache.fast_writes 0 # number of fast writes performed 590system.cpu.icache.cache_copies 0 # number of cache copies performed 591system.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits 592system.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits 593system.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits 594system.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits 595system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits 596system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits 597system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 598system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 599system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 600system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 601system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 602system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 603system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles 604system.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles 605system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles 606system.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles 607system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles 608system.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles 609system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses 610system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses 611system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses 612system.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses 613system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses 614system.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses 615system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency 616system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency 617system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency 618system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency 619system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency 620system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency 621system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 622system.cpu.l2cache.tags.replacements 0 # number of replacements 623system.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use 624system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 625system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 626system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 627system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 628system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor 629system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor 630system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy 633system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 634system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 635system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 636system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 637system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 638system.cpu.l2cache.overall_hits::total 1 # number of overall hits 639system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 640system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 641system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses 642system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 643system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 644system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 645system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 646system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 647system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 648system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 649system.cpu.l2cache.overall_misses::total 488 # number of overall misses 650system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles 651system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles 652system.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles 653system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles 654system.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles 655system.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles 656system.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles 657system.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles 658system.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles 659system.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles 660system.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles 661system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 662system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 663system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 664system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 665system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 666system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 667system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 668system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 669system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 670system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 671system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 672system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 673system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 674system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses 675system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 676system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 677system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 678system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 679system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 680system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 681system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 682system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 683system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency 684system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency 685system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency 686system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency 687system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency 688system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency 689system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency 690system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency 691system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency 692system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency 693system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency 694system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 695system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 696system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 697system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 698system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 699system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 700system.cpu.l2cache.fast_writes 0 # number of fast writes performed 701system.cpu.l2cache.cache_copies 0 # number of cache copies performed 702system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 703system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 704system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 705system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 706system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 707system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 708system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 709system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 710system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 711system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 712system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 713system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles 714system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles 715system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles 716system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles 717system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles 718system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles 719system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles 720system.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles 721system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles 722system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles 723system.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles 724system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 725system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 726system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 727system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 728system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 729system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 730system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 731system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 732system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 733system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 734system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 735system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency 736system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency 737system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency 738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency 739system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency 741system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency 742system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency 744system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency 745system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency 746system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 747system.cpu.dcache.tags.replacements 0 # number of replacements 748system.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use 749system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. 750system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 751system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. 752system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 753system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor 754system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy 755system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy 756system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits 757system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits 758system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 759system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 760system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits 761system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits 762system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits 763system.cpu.dcache.overall_hits::total 2230 # number of overall hits 764system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 765system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses 766system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 767system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 768system.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses 769system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses 770system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses 771system.cpu.dcache.overall_misses::total 529 # number of overall misses 772system.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles 773system.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles 774system.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles 775system.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles 776system.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles 777system.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles 778system.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles 779system.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles 780system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) 781system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 783system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 784system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses 785system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses 786system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses 787system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses 788system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 792system.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses 793system.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses 794system.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses 795system.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses 796system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency 797system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency 798system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency 799system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency 800system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency 801system.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency 802system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency 803system.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency 804system.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked 805system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 806system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 807system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 808system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked 809system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 810system.cpu.dcache.fast_writes 0 # number of fast writes performed 811system.cpu.dcache.cache_copies 0 # number of cache copies performed 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 816system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 817system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 818system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 819system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 820system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 821system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 822system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 823system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 824system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 825system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 826system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 827system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 828system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles 829system.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles 830system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles 831system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles 832system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles 833system.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles 834system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles 835system.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles 836system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses 837system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses 838system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 839system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 840system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses 841system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses 842system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses 843system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency 845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency 847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency 848system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency 849system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency 850system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency 851system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency 852system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 853 854---------- End Simulation Statistics ---------- 855