stats.txt revision 8983
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12450500 # Number of ticks simulated 5final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 42940 # Simulator instruction rate (inst/s) 8host_op_rate 42933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 83690683 # Simulator tick rate (ticks/s) 10host_mem_usage 215012 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host 12sim_insts 6386 # Number of instructions simulated 13sim_ops 6386 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 31360 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 490 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.fetch_hits 0 # ITB hits 24system.cpu.dtb.fetch_misses 0 # ITB misses 25system.cpu.dtb.fetch_acv 0 # ITB acv 26system.cpu.dtb.fetch_accesses 0 # ITB accesses 27system.cpu.dtb.read_hits 1943 # DTB read hits 28system.cpu.dtb.read_misses 53 # DTB read misses 29system.cpu.dtb.read_acv 0 # DTB read access violations 30system.cpu.dtb.read_accesses 1996 # DTB read accesses 31system.cpu.dtb.write_hits 1071 # DTB write hits 32system.cpu.dtb.write_misses 32 # DTB write misses 33system.cpu.dtb.write_acv 0 # DTB write access violations 34system.cpu.dtb.write_accesses 1103 # DTB write accesses 35system.cpu.dtb.data_hits 3014 # DTB hits 36system.cpu.dtb.data_misses 85 # DTB misses 37system.cpu.dtb.data_acv 0 # DTB access violations 38system.cpu.dtb.data_accesses 3099 # DTB accesses 39system.cpu.itb.fetch_hits 2367 # ITB hits 40system.cpu.itb.fetch_misses 26 # ITB misses 41system.cpu.itb.fetch_acv 0 # ITB acv 42system.cpu.itb.fetch_accesses 2393 # ITB accesses 43system.cpu.itb.read_hits 0 # DTB read hits 44system.cpu.itb.read_misses 0 # DTB read misses 45system.cpu.itb.read_acv 0 # DTB read access violations 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_acv 0 # DTB write access violations 50system.cpu.itb.write_accesses 0 # DTB write accesses 51system.cpu.itb.data_hits 0 # DTB hits 52system.cpu.itb.data_misses 0 # DTB misses 53system.cpu.itb.data_acv 0 # DTB access violations 54system.cpu.itb.data_accesses 0 # DTB accesses 55system.cpu.workload.num_syscalls 17 # Number of system calls 56system.cpu.numCycles 24902 # number of cpu cycles simulated 57system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 58system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 59system.cpu.BPredUnit.lookups 2873 # Number of BP lookups 60system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted 61system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect 62system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups 63system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits 64system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 65system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. 66system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. 67system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss 68system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed 69system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered 70system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken 71system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked 72system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing 73system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked 74system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 75system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps 76system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched 77system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed 78system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle 96system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle 97system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle 98system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked 99system.cpu.decode.RunCycles 2784 # Number of cycles decode is running 100system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking 101system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing 102system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch 103system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction 104system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode 105system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode 106system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing 107system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle 108system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking 109system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst 110system.cpu.rename.RunCycles 2587 # Number of cycles rename is running 111system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking 112system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename 113system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 114system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full 115system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed 116system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made 117system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups 118system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 119system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed 120system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing 121system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 122system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 123system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer 124system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. 125system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. 126system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 127system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 128system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) 129system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ 130system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued 131system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued 132system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling 133system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph 134system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 135system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle 152system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 153system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available 154system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available 155system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available 156system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available 157system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available 158system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available 159system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available 160system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available 161system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 182system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available 183system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available 184system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 185system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 186system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 187system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued 188system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued 189system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued 190system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued 191system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued 192system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued 193system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued 194system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued 195system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued 216system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued 217system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued 218system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 219system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 220system.cpu.iq.FU_type_0::total 10522 # Type of FU issued 221system.cpu.iq.rate 0.422536 # Inst issue rate 222system.cpu.iq.fu_busy_cnt 112 # FU busy when requested 223system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) 224system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads 225system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes 226system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses 227system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 228system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 229system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 230system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses 231system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 232system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores 233system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 234system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed 235system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 236system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 237system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed 238system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 239system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 240system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 241system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 242system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 243system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing 244system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking 245system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking 246system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ 247system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch 248system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions 249system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions 250system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 251system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 252system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 253system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 254system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly 255system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly 256system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute 257system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions 258system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed 259system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute 260system.cpu.iew.exec_swp 0 # number of swp insts executed 261system.cpu.iew.exec_nop 79 # number of nop insts executed 262system.cpu.iew.exec_refs 3117 # number of memory reference insts executed 263system.cpu.iew.exec_branches 1605 # Number of branches executed 264system.cpu.iew.exec_stores 1108 # Number of stores executed 265system.cpu.iew.exec_rate 0.396675 # Inst execution rate 266system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit 267system.cpu.iew.wb_count 9487 # cumulative count of insts written-back 268system.cpu.iew.wb_producers 4957 # num instructions producing a value 269system.cpu.iew.wb_consumers 6732 # num instructions consuming a value 270system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 271system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle 272system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back 273system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 274system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 275system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions 276system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit 277system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 278system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted 279system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 283system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle 284system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle 285system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle 296system.cpu.commit.committedInsts 6403 # Number of instructions committed 297system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed 298system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 299system.cpu.commit.refs 2050 # Number of memory references committed 300system.cpu.commit.loads 1185 # Number of loads committed 301system.cpu.commit.membars 0 # Number of memory barriers committed 302system.cpu.commit.branches 1051 # Number of branches committed 303system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 304system.cpu.commit.int_insts 6321 # Number of committed integer instructions. 305system.cpu.commit.function_calls 127 # Number of function calls committed. 306system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached 307system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 308system.cpu.rob.rob_reads 24667 # The number of ROB reads 309system.cpu.rob.rob_writes 26868 # The number of ROB writes 310system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself 311system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling 312system.cpu.committedInsts 6386 # Number of Instructions Simulated 313system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated 314system.cpu.committedInsts_total 6386 # Number of Instructions Simulated 315system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction 316system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads 317system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle 318system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads 319system.cpu.int_regfile_reads 12526 # number of integer regfile reads 320system.cpu.int_regfile_writes 7116 # number of integer regfile writes 321system.cpu.fp_regfile_reads 8 # number of floating regfile reads 322system.cpu.fp_regfile_writes 2 # number of floating regfile writes 323system.cpu.misc_regfile_reads 1 # number of misc regfile reads 324system.cpu.misc_regfile_writes 1 # number of misc regfile writes 325system.cpu.icache.replacements 0 # number of replacements 326system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use 327system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. 328system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. 329system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. 330system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 331system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor 332system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy 333system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy 334system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits 335system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits 336system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits 337system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits 338system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits 339system.cpu.icache.overall_hits::total 1909 # number of overall hits 340system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 341system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 342system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 343system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 344system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 345system.cpu.icache.overall_misses::total 458 # number of overall misses 346system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles 347system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles 348system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles 349system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles 350system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles 351system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles 352system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) 353system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) 354system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses 355system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses 356system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses 357system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses 358system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses 359system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses 360system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses 361system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency 362system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 363system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 364system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 365system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 366system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 367system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 368system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 369system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 370system.cpu.icache.fast_writes 0 # number of fast writes performed 371system.cpu.icache.cache_copies 0 # number of cache copies performed 372system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits 373system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits 374system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits 375system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits 376system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits 377system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits 378system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 379system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 380system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 381system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 382system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 383system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 384system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles 385system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles 386system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles 387system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles 388system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles 389system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles 390system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses 391system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses 392system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses 393system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency 394system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency 395system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency 396system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 397system.cpu.dcache.replacements 0 # number of replacements 398system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use 399system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. 400system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. 401system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. 402system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 403system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor 404system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy 405system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy 406system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits 407system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits 408system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits 409system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits 410system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits 411system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits 412system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits 413system.cpu.dcache.overall_hits::total 2244 # number of overall hits 414system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses 415system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses 416system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses 417system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses 418system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses 419system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses 420system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses 421system.cpu.dcache.overall_misses::total 500 # number of overall misses 422system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles 423system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles 424system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles 425system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles 426system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles 427system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles 428system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles 429system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles 430system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) 431system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 433system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses 435system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses 436system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses 437system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses 438system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses 439system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses 440system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses 441system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses 442system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency 445system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency 446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 452system.cpu.dcache.fast_writes 0 # number of fast writes performed 453system.cpu.dcache.cache_copies 0 # number of cache copies performed 454system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 455system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 458system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits 459system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits 460system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits 461system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits 462system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 463system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses 464system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 466system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses 467system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses 468system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses 469system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses 470system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles 471system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles 472system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles 473system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles 474system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles 475system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles 476system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles 477system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles 478system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses 479system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 480system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses 481system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses 482system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency 483system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency 484system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency 485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency 486system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 487system.cpu.l2cache.replacements 0 # number of replacements 488system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use 489system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 490system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. 491system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. 492system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 493system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor 494system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor 495system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy 496system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy 497system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy 498system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 499system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 500system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 501system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 502system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 503system.cpu.l2cache.overall_hits::total 1 # number of overall hits 504system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 505system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 506system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses 507system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 508system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 509system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 510system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses 511system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses 512system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 513system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses 514system.cpu.l2cache.overall_misses::total 490 # number of overall misses 515system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles 516system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles 517system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles 518system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles 519system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles 520system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles 521system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles 522system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles 523system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles 524system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles 525system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles 526system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 527system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) 528system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) 529system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 530system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 531system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 532system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses 533system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses 534system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 535system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses 536system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses 537system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 539system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 540system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 541system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 542system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 543system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 544system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency 545system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency 546system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency 547system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 548system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 551system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 552system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 555system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 557system.cpu.l2cache.fast_writes 0 # number of fast writes performed 558system.cpu.l2cache.cache_copies 0 # number of cache copies performed 559system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 560system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 561system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 563system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 564system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 565system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses 566system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses 567system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 568system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses 569system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses 570system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles 571system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles 572system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles 573system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles 574system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles 575system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles 576system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles 577system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles 578system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles 579system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles 580system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles 581system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 582system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 583system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 584system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 585system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency 589system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency 590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency 595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 596 597---------- End Simulation Statistics ---------- 598