stats.txt revision 11268:8b4b55d79ddd
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21900500 # Number of ticks simulated 5final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 48553 # Simulator instruction rate (inst/s) 8host_op_rate 48543 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 166810792 # Simulator tick rate (ticks/s) 10host_mem_usage 232316 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30784 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 481 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 481 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 68 # Per bank write bursts 45system.physmem.perBankRdBursts::1 32 # Per bank write bursts 46system.physmem.perBankRdBursts::2 32 # Per bank write bursts 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 41 # Per bank write bursts 49system.physmem.perBankRdBursts::5 20 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 22 # Per bank write bursts 55system.physmem.perBankRdBursts::11 25 # Per bank write bursts 56system.physmem.perBankRdBursts::12 14 # Per bank write bursts 57system.physmem.perBankRdBursts::13 118 # Per bank write bursts 58system.physmem.perBankRdBursts::14 45 # Per bank write bursts 59system.physmem.perBankRdBursts::15 12 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 21763000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 481 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 202system.physmem.totQLat 3965000 # Total ticks spent queuing 203system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 10.98 # Data bus utilization in percentage 214system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 387 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 45245.32 # Average gap between requests 223system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined 224system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 226system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ) 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 229system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 230system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) 231system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ) 232system.physmem_0.averagePower 870.058740 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states 234system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ) 240system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ) 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 243system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ) 246system.physmem_1.averagePower 855.521554 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.branchPred.lookups 2551 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 726 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 258system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. 261system.cpu_clk_domain.clock 500 # Clock period in ticks 262system.cpu.dtb.fetch_hits 0 # ITB hits 263system.cpu.dtb.fetch_misses 0 # ITB misses 264system.cpu.dtb.fetch_acv 0 # ITB acv 265system.cpu.dtb.fetch_accesses 0 # ITB accesses 266system.cpu.dtb.read_hits 2033 # DTB read hits 267system.cpu.dtb.read_misses 43 # DTB read misses 268system.cpu.dtb.read_acv 0 # DTB read access violations 269system.cpu.dtb.read_accesses 2076 # DTB read accesses 270system.cpu.dtb.write_hits 1052 # DTB write hits 271system.cpu.dtb.write_misses 28 # DTB write misses 272system.cpu.dtb.write_acv 0 # DTB write access violations 273system.cpu.dtb.write_accesses 1080 # DTB write accesses 274system.cpu.dtb.data_hits 3085 # DTB hits 275system.cpu.dtb.data_misses 71 # DTB misses 276system.cpu.dtb.data_acv 0 # DTB access violations 277system.cpu.dtb.data_accesses 3156 # DTB accesses 278system.cpu.itb.fetch_hits 2086 # ITB hits 279system.cpu.itb.fetch_misses 32 # ITB misses 280system.cpu.itb.fetch_acv 0 # ITB acv 281system.cpu.itb.fetch_accesses 2118 # ITB accesses 282system.cpu.itb.read_hits 0 # DTB read hits 283system.cpu.itb.read_misses 0 # DTB read misses 284system.cpu.itb.read_acv 0 # DTB read access violations 285system.cpu.itb.read_accesses 0 # DTB read accesses 286system.cpu.itb.write_hits 0 # DTB write hits 287system.cpu.itb.write_misses 0 # DTB write misses 288system.cpu.itb.write_acv 0 # DTB write access violations 289system.cpu.itb.write_accesses 0 # DTB write accesses 290system.cpu.itb.data_hits 0 # DTB hits 291system.cpu.itb.data_misses 0 # DTB misses 292system.cpu.itb.data_acv 0 # DTB access violations 293system.cpu.itb.data_accesses 0 # DTB accesses 294system.cpu.workload.num_syscalls 17 # Number of system calls 295system.cpu.numCycles 43802 # number of cpu cycles simulated 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 298system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss 299system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken 302system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked 303system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing 304system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 305system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps 306system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched 307system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed 308system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle 326system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle 327system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle 328system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked 329system.cpu.decode.RunCycles 2283 # Number of cycles decode is running 330system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking 331system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing 332system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch 333system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction 334system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode 335system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode 336system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing 337system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle 338system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking 339system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst 340system.cpu.rename.RunCycles 2297 # Number of cycles rename is running 341system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking 342system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename 343system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 344system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full 345system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full 346system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full 347system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed 348system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made 349system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups 350system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 351system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 352system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing 353system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 354system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 355system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer 356system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit. 357system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit. 358system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 359system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 360system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec) 361system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 362system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued 363system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling 365system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph 366system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 367system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle 384system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 385system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available 386system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 419system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued 420system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued 421system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued 448system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued 449system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued 450system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 452system.cpu.iq.FU_type_0::total 10150 # Type of FU issued 453system.cpu.iq.rate 0.231725 # Inst issue rate 454system.cpu.iq.fu_busy_cnt 132 # FU busy when requested 455system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst) 456system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads 457system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes 458system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses 459system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 460system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 461system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 462system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses 463system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 464system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores 465system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 466system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed 467system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 468system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 469system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed 470system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 471system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 472system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 473system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked 474system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 475system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing 476system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking 477system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking 478system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ 479system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch 480system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions 481system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions 482system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 483system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall 484system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall 485system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 486system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly 487system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly 488system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute 489system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions 490system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed 491system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 492system.cpu.iew.exec_swp 0 # number of swp insts executed 493system.cpu.iew.exec_nop 84 # number of nop insts executed 494system.cpu.iew.exec_refs 3158 # number of memory reference insts executed 495system.cpu.iew.exec_branches 1540 # Number of branches executed 496system.cpu.iew.exec_stores 1082 # Number of stores executed 497system.cpu.iew.exec_rate 0.222638 # Inst execution rate 498system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit 499system.cpu.iew.wb_count 9326 # cumulative count of insts written-back 500system.cpu.iew.wb_producers 4992 # num instructions producing a value 501system.cpu.iew.wb_consumers 6833 # num instructions consuming a value 502system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle 503system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back 504system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit 505system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 506system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted 507system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle 524system.cpu.commit.committedInsts 6389 # Number of instructions committed 525system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 526system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 527system.cpu.commit.refs 2048 # Number of memory references committed 528system.cpu.commit.loads 1183 # Number of loads committed 529system.cpu.commit.membars 0 # Number of memory barriers committed 530system.cpu.commit.branches 1050 # Number of branches committed 531system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 532system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 533system.cpu.commit.function_calls 127 # Number of function calls committed. 534system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 535system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 536system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 537system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 538system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 539system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 540system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 541system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 542system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 543system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 564system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 565system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 566system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 567system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 568system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 569system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached 570system.cpu.rob.rob_reads 24728 # The number of ROB reads 571system.cpu.rob.rob_writes 25475 # The number of ROB writes 572system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 573system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling 574system.cpu.committedInsts 6372 # Number of Instructions Simulated 575system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 576system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction 577system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads 578system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle 579system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads 580system.cpu.int_regfile_reads 12362 # number of integer regfile reads 581system.cpu.int_regfile_writes 7056 # number of integer regfile writes 582system.cpu.fp_regfile_reads 8 # number of floating regfile reads 583system.cpu.fp_regfile_writes 2 # number of floating regfile writes 584system.cpu.misc_regfile_reads 1 # number of misc regfile reads 585system.cpu.misc_regfile_writes 1 # number of misc regfile writes 586system.cpu.dcache.tags.replacements 0 # number of replacements 587system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use 588system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. 589system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. 590system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks. 591system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 592system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor 593system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy 594system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy 595system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id 596system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 597system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 598system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id 599system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses 600system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses 601system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits 602system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits 603system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 604system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 605system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits 606system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits 607system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits 608system.cpu.dcache.overall_hits::total 2276 # number of overall hits 609system.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses 610system.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses 611system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 612system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 613system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses 614system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses 615system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses 616system.cpu.dcache.overall_misses::total 512 # number of overall misses 617system.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles 618system.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles 619system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles 620system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles 621system.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles 622system.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles 623system.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles 624system.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles 625system.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses) 626system.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) 627system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 628system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 629system.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses 630system.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses 631system.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses 632system.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses 633system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079563 # miss rate for ReadReq accesses 634system.cpu.dcache.ReadReq_miss_rate::total 0.079563 # miss rate for ReadReq accesses 635system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 636system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 637system.cpu.dcache.demand_miss_rate::cpu.data 0.183644 # miss rate for demand accesses 638system.cpu.dcache.demand_miss_rate::total 0.183644 # miss rate for demand accesses 639system.cpu.dcache.overall_miss_rate::cpu.data 0.183644 # miss rate for overall accesses 640system.cpu.dcache.overall_miss_rate::total 0.183644 # miss rate for overall accesses 641system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366 # average ReadReq miss latency 642system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency 643system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency 644system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency 645system.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency 646system.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency 648system.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency 649system.cpu.dcache.blocked_cycles::no_mshrs 2328 # number of cycles access was blocked 650system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked 652system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.428571 # average number of cycles each access was blocked 654system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.cpu.dcache.fast_writes 0 # number of fast writes performed 656system.cpu.dcache.cache_copies 0 # number of cache copies performed 657system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits 658system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits 659system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 661system.cpu.dcache.demand_mshr_hits::cpu.data 341 # number of demand (read+write) MSHR hits 662system.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits 663system.cpu.dcache.overall_mshr_hits::cpu.data 341 # number of overall MSHR hits 664system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits 665system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 666system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 669system.cpu.dcache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses 670system.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses 671system.cpu.dcache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses 672system.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses 673system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8341000 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_miss_latency::total 8341000 # number of ReadReq MSHR miss cycles 675system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles 677system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14010500 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.demand_mshr_miss_latency::total 14010500 # number of demand (read+write) MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14010500 # number of overall MSHR miss cycles 680system.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles 681system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051482 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051482 # mshr miss rate for ReadReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 685system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for demand accesses 686system.cpu.dcache.demand_mshr_miss_rate::total 0.061334 # mshr miss rate for demand accesses 687system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for overall accesses 688system.cpu.dcache.overall_mshr_miss_rate::total 0.061334 # mshr miss rate for overall accesses 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253 # average ReadReq mshr miss latency 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 697system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.icache.tags.replacements 0 # number of replacements 699system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use 700system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. 701system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. 702system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. 703system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 704system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor 705system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy 706system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy 707system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id 708system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 709system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 710system.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id 711system.cpu.icache.tags.tag_accesses 4483 # Number of tag accesses 712system.cpu.icache.tags.data_accesses 4483 # Number of data accesses 713system.cpu.icache.ReadReq_hits::cpu.inst 1627 # number of ReadReq hits 714system.cpu.icache.ReadReq_hits::total 1627 # number of ReadReq hits 715system.cpu.icache.demand_hits::cpu.inst 1627 # number of demand (read+write) hits 716system.cpu.icache.demand_hits::total 1627 # number of demand (read+write) hits 717system.cpu.icache.overall_hits::cpu.inst 1627 # number of overall hits 718system.cpu.icache.overall_hits::total 1627 # number of overall hits 719system.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses 720system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses 721system.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses 722system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses 723system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses 724system.cpu.icache.overall_misses::total 459 # number of overall misses 725system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles 726system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles 727system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles 728system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles 729system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles 730system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles 731system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) 732system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) 733system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses 734system.cpu.icache.demand_accesses::total 2086 # number of demand (read+write) accesses 735system.cpu.icache.overall_accesses::cpu.inst 2086 # number of overall (read+write) accesses 736system.cpu.icache.overall_accesses::total 2086 # number of overall (read+write) accesses 737system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.220038 # miss rate for ReadReq accesses 738system.cpu.icache.ReadReq_miss_rate::total 0.220038 # miss rate for ReadReq accesses 739system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 # miss rate for demand accesses 740system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses 741system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses 742system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses 743system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency 744system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency 745system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency 746system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency 747system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency 748system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency 749system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.icache.fast_writes 0 # number of fast writes performed 756system.cpu.icache.cache_copies 0 # number of cache copies performed 757system.cpu.icache.ReadReq_mshr_hits::cpu.inst 148 # number of ReadReq MSHR hits 758system.cpu.icache.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits 759system.cpu.icache.demand_mshr_hits::cpu.inst 148 # number of demand (read+write) MSHR hits 760system.cpu.icache.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits 761system.cpu.icache.overall_mshr_hits::cpu.inst 148 # number of overall MSHR hits 762system.cpu.icache.overall_mshr_hits::total 148 # number of overall MSHR hits 763system.cpu.icache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses 764system.cpu.icache.ReadReq_mshr_misses::total 311 # number of ReadReq MSHR misses 765system.cpu.icache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses 766system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses 767system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses 768system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses 769system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles 770system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles 771system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles 772system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles 773system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles 774system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles 775system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses 776system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses 777system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses 778system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses 779system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses 780system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses 781system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency 782system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency 783system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency 784system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency 785system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency 786system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency 787system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 788system.cpu.l2cache.tags.replacements 0 # number of replacements 789system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use 790system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 791system.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks. 792system.cpu.l2cache.tags.avg_refs 0.002445 # Average number of references to valid blocks. 793system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.816586 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_blocks::cpu.data 60.394993 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004816 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.data 0.001843 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::total 0.006659 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 802system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012482 # Percentage of cache occupancy per task id 803system.cpu.l2cache.tags.tag_accesses 4337 # Number of tag accesses 804system.cpu.l2cache.tags.data_accesses 4337 # Number of data accesses 805system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 806system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 807system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 808system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 809system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 810system.cpu.l2cache.overall_hits::total 1 # number of overall hits 811system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 812system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 813system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 310 # number of ReadCleanReq misses 814system.cpu.l2cache.ReadCleanReq_misses::total 310 # number of ReadCleanReq misses 815system.cpu.l2cache.ReadSharedReq_misses::cpu.data 99 # number of ReadSharedReq misses 816system.cpu.l2cache.ReadSharedReq_misses::total 99 # number of ReadSharedReq misses 817system.cpu.l2cache.demand_misses::cpu.inst 310 # number of demand (read+write) misses 818system.cpu.l2cache.demand_misses::cpu.data 171 # number of demand (read+write) misses 819system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses 820system.cpu.l2cache.overall_misses::cpu.inst 310 # number of overall misses 821system.cpu.l2cache.overall_misses::cpu.data 171 # number of overall misses 822system.cpu.l2cache.overall_misses::total 481 # number of overall misses 823system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5558500 # number of ReadExReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::total 5558500 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23380000 # number of ReadCleanReq miss cycles 826system.cpu.l2cache.ReadCleanReq_miss_latency::total 23380000 # number of ReadCleanReq miss cycles 827system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8185000 # number of ReadSharedReq miss cycles 828system.cpu.l2cache.ReadSharedReq_miss_latency::total 8185000 # number of ReadSharedReq miss cycles 829system.cpu.l2cache.demand_miss_latency::cpu.inst 23380000 # number of demand (read+write) miss cycles 830system.cpu.l2cache.demand_miss_latency::cpu.data 13743500 # number of demand (read+write) miss cycles 831system.cpu.l2cache.demand_miss_latency::total 37123500 # number of demand (read+write) miss cycles 832system.cpu.l2cache.overall_miss_latency::cpu.inst 23380000 # number of overall miss cycles 833system.cpu.l2cache.overall_miss_latency::cpu.data 13743500 # number of overall miss cycles 834system.cpu.l2cache.overall_miss_latency::total 37123500 # number of overall miss cycles 835system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 836system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 837system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 311 # number of ReadCleanReq accesses(hits+misses) 838system.cpu.l2cache.ReadCleanReq_accesses::total 311 # number of ReadCleanReq accesses(hits+misses) 839system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 840system.cpu.l2cache.ReadSharedReq_accesses::total 99 # number of ReadSharedReq accesses(hits+misses) 841system.cpu.l2cache.demand_accesses::cpu.inst 311 # number of demand (read+write) accesses 842system.cpu.l2cache.demand_accesses::cpu.data 171 # number of demand (read+write) accesses 843system.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses 844system.cpu.l2cache.overall_accesses::cpu.inst 311 # number of overall (read+write) accesses 845system.cpu.l2cache.overall_accesses::cpu.data 171 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::total 482 # number of overall (read+write) accesses 847system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 848system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 849system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996785 # miss rate for ReadCleanReq accesses 850system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996785 # miss rate for ReadCleanReq accesses 851system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 852system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 853system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996785 # miss rate for demand accesses 854system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 855system.cpu.l2cache.demand_miss_rate::total 0.997925 # miss rate for demand accesses 856system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996785 # miss rate for overall accesses 857system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 858system.cpu.l2cache.overall_miss_rate::total 0.997925 # miss rate for overall accesses 859system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency 860system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency 861system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839 # average ReadCleanReq miss latency 862system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839 # average ReadCleanReq miss latency 863system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677 # average ReadSharedReq miss latency 864system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677 # average ReadSharedReq miss latency 865system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency 866system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency 867system.cpu.l2cache.demand_avg_miss_latency::total 77179.833680 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency 870system.cpu.l2cache.overall_avg_miss_latency::total 77179.833680 # average overall miss latency 871system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 874system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.l2cache.fast_writes 0 # number of fast writes performed 878system.cpu.l2cache.cache_copies 0 # number of cache copies performed 879system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 880system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 881system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses 882system.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses 883system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 99 # number of ReadSharedReq MSHR misses 884system.cpu.l2cache.ReadSharedReq_mshr_misses::total 99 # number of ReadSharedReq MSHR misses 885system.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses 886system.cpu.l2cache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses 887system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses 888system.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses 889system.cpu.l2cache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses 890system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses 891system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles 892system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles 893system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20280000 # number of ReadCleanReq MSHR miss cycles 894system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20280000 # number of ReadCleanReq MSHR miss cycles 895system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles 896system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles 897system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles 898system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles 899system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles 900system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles 901system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles 902system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles 903system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 904system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 905system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses 906system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses 907system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 908system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 909system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses 910system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 911system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses 912system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses 913system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 914system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency 916system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency 917system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency 918system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency 919system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency 920system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency 921system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 922system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 923system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 924system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 925system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 926system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 927system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 928system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. 929system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 930system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 931system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 932system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 933system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 934system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution 939system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 944system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 945system.cpu.toL2Bus.snoops 0 # Total snoops (count) 946system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram 957system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 958system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 959system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) 960system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 961system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) 962system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 963system.membus.trans_dist::ReadResp 409 # Transaction distribution 964system.membus.trans_dist::ReadExReq 72 # Transaction distribution 965system.membus.trans_dist::ReadExResp 72 # Transaction distribution 966system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution 967system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes) 968system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes) 969system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes) 970system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes) 971system.membus.snoops 0 # Total snoops (count) 972system.membus.snoop_fanout::samples 481 # Request fanout histogram 973system.membus.snoop_fanout::mean 0 # Request fanout histogram 974system.membus.snoop_fanout::stdev 0 # Request fanout histogram 975system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 976system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram 977system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 978system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 979system.membus.snoop_fanout::min_value 0 # Request fanout histogram 980system.membus.snoop_fanout::max_value 0 # Request fanout histogram 981system.membus.snoop_fanout::total 481 # Request fanout histogram 982system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks) 983system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 984system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks) 985system.membus.respLayer1.utilization 11.7 # Layer utilization (%) 986 987---------- End Simulation Statistics ---------- 988