stats.txt revision 10433:821cbe4a183b
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 20537500 # Number of ticks simulated 5final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 69014 # Simulator instruction rate (inst/s) 8host_op_rate 69006 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 222388397 # Simulator tick rate (ticks/s) 10host_mem_usage 237256 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31168 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 487 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 487 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 69 # Per bank write bursts 45system.physmem.perBankRdBursts::1 33 # Per bank write bursts 46system.physmem.perBankRdBursts::2 32 # Per bank write bursts 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 42 # Per bank write bursts 49system.physmem.perBankRdBursts::5 20 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 23 # Per bank write bursts 55system.physmem.perBankRdBursts::11 25 # Per bank write bursts 56system.physmem.perBankRdBursts::12 14 # Per bank write bursts 57system.physmem.perBankRdBursts::13 120 # Per bank write bursts 58system.physmem.perBankRdBursts::14 45 # Per bank write bursts 59system.physmem.perBankRdBursts::15 12 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 20412000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 487 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation 203system.physmem.totQLat 4742750 # Total ticks spent queuing 204system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.86 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 390 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 41913.76 # Average gap between requests 224system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 22000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15339250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.physmem.actEnergy::0 234360 # Energy for activate commands per rank (pJ) 231system.physmem.actEnergy::1 332640 # Energy for activate commands per rank (pJ) 232system.physmem.preEnergy::0 127875 # Energy for precharge commands per rank (pJ) 233system.physmem.preEnergy::1 181500 # Energy for precharge commands per rank (pJ) 234system.physmem.readEnergy::0 1755000 # Energy for read commands per rank (pJ) 235system.physmem.readEnergy::1 1365000 # Energy for read commands per rank (pJ) 236system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 237system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 238system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) 239system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) 240system.physmem.actBackEnergy::0 10809765 # Energy for active background per rank (pJ) 241system.physmem.actBackEnergy::1 10569510 # Energy for active background per rank (pJ) 242system.physmem.preBackEnergy::0 38250 # Energy for precharge background per rank (pJ) 243system.physmem.preBackEnergy::1 249000 # Energy for precharge background per rank (pJ) 244system.physmem.totalEnergy::0 13982370 # Total energy per rank (pJ) 245system.physmem.totalEnergy::1 13714770 # Total energy per rank (pJ) 246system.physmem.averagePower::0 881.195525 # Core power per rank (mW) 247system.physmem.averagePower::1 864.330865 # Core power per rank (mW) 248system.membus.trans_dist::ReadReq 415 # Transaction distribution 249system.membus.trans_dist::ReadResp 415 # Transaction distribution 250system.membus.trans_dist::ReadExReq 72 # Transaction distribution 251system.membus.trans_dist::ReadExResp 72 # Transaction distribution 252system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) 253system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) 254system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 255system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 256system.membus.snoops 0 # Total snoops (count) 257system.membus.snoop_fanout::samples 487 # Request fanout histogram 258system.membus.snoop_fanout::mean 0 # Request fanout histogram 259system.membus.snoop_fanout::stdev 0 # Request fanout histogram 260system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 261system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram 262system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 263system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 264system.membus.snoop_fanout::min_value 0 # Request fanout histogram 265system.membus.snoop_fanout::max_value 0 # Request fanout histogram 266system.membus.snoop_fanout::total 487 # Request fanout histogram 267system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) 268system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 269system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) 270system.membus.respLayer1.utilization 22.2 # Layer utilization (%) 271system.cpu_clk_domain.clock 500 # Clock period in ticks 272system.cpu.branchPred.lookups 2806 # Number of BP lookups 273system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted 274system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect 275system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups 276system.cpu.branchPred.BTBHits 686 # Number of BTB hits 277system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 278system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage 279system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. 280system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. 281system.cpu.dtb.fetch_hits 0 # ITB hits 282system.cpu.dtb.fetch_misses 0 # ITB misses 283system.cpu.dtb.fetch_acv 0 # ITB acv 284system.cpu.dtb.fetch_accesses 0 # ITB accesses 285system.cpu.dtb.read_hits 2085 # DTB read hits 286system.cpu.dtb.read_misses 55 # DTB read misses 287system.cpu.dtb.read_acv 0 # DTB read access violations 288system.cpu.dtb.read_accesses 2140 # DTB read accesses 289system.cpu.dtb.write_hits 1069 # DTB write hits 290system.cpu.dtb.write_misses 30 # DTB write misses 291system.cpu.dtb.write_acv 0 # DTB write access violations 292system.cpu.dtb.write_accesses 1099 # DTB write accesses 293system.cpu.dtb.data_hits 3154 # DTB hits 294system.cpu.dtb.data_misses 85 # DTB misses 295system.cpu.dtb.data_acv 0 # DTB access violations 296system.cpu.dtb.data_accesses 3239 # DTB accesses 297system.cpu.itb.fetch_hits 2196 # ITB hits 298system.cpu.itb.fetch_misses 38 # ITB misses 299system.cpu.itb.fetch_acv 0 # ITB acv 300system.cpu.itb.fetch_accesses 2234 # ITB accesses 301system.cpu.itb.read_hits 0 # DTB read hits 302system.cpu.itb.read_misses 0 # DTB read misses 303system.cpu.itb.read_acv 0 # DTB read access violations 304system.cpu.itb.read_accesses 0 # DTB read accesses 305system.cpu.itb.write_hits 0 # DTB write hits 306system.cpu.itb.write_misses 0 # DTB write misses 307system.cpu.itb.write_acv 0 # DTB write access violations 308system.cpu.itb.write_accesses 0 # DTB write accesses 309system.cpu.itb.data_hits 0 # DTB hits 310system.cpu.itb.data_misses 0 # DTB misses 311system.cpu.itb.data_acv 0 # DTB access violations 312system.cpu.itb.data_accesses 0 # DTB accesses 313system.cpu.workload.num_syscalls 17 # Number of system calls 314system.cpu.numCycles 41076 # number of cpu cycles simulated 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 317system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss 318system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed 319system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered 320system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken 321system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked 322system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing 323system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 324system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps 325system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched 326system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed 327system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle 345system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle 346system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle 347system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked 348system.cpu.decode.RunCycles 2410 # Number of cycles decode is running 349system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking 350system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing 351system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch 352system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction 353system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode 354system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode 355system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing 356system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle 357system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking 358system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst 359system.cpu.rename.RunCycles 2422 # Number of cycles rename is running 360system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking 361system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename 362system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full 363system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 364system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full 365system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full 366system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed 367system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made 368system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups 369system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 370system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 371system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing 372system.cpu.rename.serializingInsts 32 # count of serializing insts renamed 373system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 374system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer 375system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. 376system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. 377system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. 378system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 379system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) 380system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 381system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued 382system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued 383system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling 384system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph 385system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 386system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle 403system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available 406system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available 433system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available 434system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 436system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 437system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 438system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued 439system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued 440system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 446system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 467system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued 468system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued 469system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 470system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 471system.cpu.iq.FU_type_0::total 10718 # Type of FU issued 472system.cpu.iq.rate 0.260931 # Inst issue rate 473system.cpu.iq.fu_busy_cnt 145 # FU busy when requested 474system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) 475system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads 476system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes 477system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses 478system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 479system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 480system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 481system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses 482system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 483system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 484system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 485system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed 486system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 487system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 488system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed 489system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 490system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 491system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 492system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked 493system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 494system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing 495system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking 496system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 497system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ 498system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch 499system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions 500system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions 501system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 502system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 503system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 504system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 505system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly 506system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly 507system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute 508system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions 509system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed 510system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute 511system.cpu.iew.exec_swp 0 # number of swp insts executed 512system.cpu.iew.exec_nop 89 # number of nop insts executed 513system.cpu.iew.exec_refs 3244 # number of memory reference insts executed 514system.cpu.iew.exec_branches 1603 # Number of branches executed 515system.cpu.iew.exec_stores 1101 # Number of stores executed 516system.cpu.iew.exec_rate 0.248904 # Inst execution rate 517system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit 518system.cpu.iew.wb_count 9793 # cumulative count of insts written-back 519system.cpu.iew.wb_producers 5300 # num instructions producing a value 520system.cpu.iew.wb_consumers 7279 # num instructions consuming a value 521system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 522system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle 523system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back 524system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 525system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit 526system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 527system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted 528system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle 545system.cpu.commit.committedInsts 6389 # Number of instructions committed 546system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 547system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 548system.cpu.commit.refs 2048 # Number of memory references committed 549system.cpu.commit.loads 1183 # Number of loads committed 550system.cpu.commit.membars 0 # Number of memory barriers committed 551system.cpu.commit.branches 1050 # Number of branches committed 552system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 553system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 554system.cpu.commit.function_calls 127 # Number of function calls committed. 555system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 556system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 557system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 558system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 559system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 560system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 561system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 562system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 563system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 564system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 579system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 580system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 581system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 582system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 583system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 584system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 585system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 586system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 587system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 588system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 589system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 590system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached 591system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 592system.cpu.rob.rob_reads 25507 # The number of ROB reads 593system.cpu.rob.rob_writes 27214 # The number of ROB writes 594system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself 595system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling 596system.cpu.committedInsts 6372 # Number of Instructions Simulated 597system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 598system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction 599system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads 600system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle 601system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads 602system.cpu.int_regfile_reads 12991 # number of integer regfile reads 603system.cpu.int_regfile_writes 7455 # number of integer regfile writes 604system.cpu.fp_regfile_reads 8 # number of floating regfile reads 605system.cpu.fp_regfile_writes 2 # number of floating regfile writes 606system.cpu.misc_regfile_reads 1 # number of misc regfile reads 607system.cpu.misc_regfile_writes 1 # number of misc regfile writes 608system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 612system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 614system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.snoops 0 # Total snoops (count) 619system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 628system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram 630system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) 631system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 632system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) 633system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 634system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) 635system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 636system.cpu.icache.tags.replacements 0 # number of replacements 637system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use 638system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. 639system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 640system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. 641system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 642system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor 643system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy 644system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy 645system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 646system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 647system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 648system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id 649system.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses 650system.cpu.icache.tags.data_accesses 4706 # Number of data accesses 651system.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits 652system.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits 653system.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits 654system.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits 655system.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits 656system.cpu.icache.overall_hits::total 1718 # number of overall hits 657system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses 658system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses 659system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses 660system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses 661system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses 662system.cpu.icache.overall_misses::total 478 # number of overall misses 663system.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles 664system.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles 665system.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles 666system.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles 667system.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles 668system.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles 669system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) 670system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) 671system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses 672system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses 673system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses 674system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses 675system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses 676system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses 677system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses 678system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses 679system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses 680system.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses 681system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency 682system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency 683system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency 684system.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency 685system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency 686system.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency 687system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.cpu.icache.fast_writes 0 # number of fast writes performed 694system.cpu.icache.cache_copies 0 # number of cache copies performed 695system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits 696system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits 697system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits 698system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits 699system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits 700system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits 701system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 702system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 703system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 704system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 705system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 706system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses 707system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22315500 # number of ReadReq MSHR miss cycles 708system.cpu.icache.ReadReq_mshr_miss_latency::total 22315500 # number of ReadReq MSHR miss cycles 709system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22315500 # number of demand (read+write) MSHR miss cycles 710system.cpu.icache.demand_mshr_miss_latency::total 22315500 # number of demand (read+write) MSHR miss cycles 711system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22315500 # number of overall MSHR miss cycles 712system.cpu.icache.overall_mshr_miss_latency::total 22315500 # number of overall MSHR miss cycles 713system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for ReadReq accesses 714system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142987 # mshr miss rate for ReadReq accesses 715system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for demand accesses 716system.cpu.icache.demand_mshr_miss_rate::total 0.142987 # mshr miss rate for demand accesses 717system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for overall accesses 718system.cpu.icache.overall_mshr_miss_rate::total 0.142987 # mshr miss rate for overall accesses 719system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338 # average ReadReq mshr miss latency 720system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338 # average ReadReq mshr miss latency 721system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency 722system.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency 723system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency 724system.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency 725system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 726system.cpu.l2cache.tags.replacements 0 # number of replacements 727system.cpu.l2cache.tags.tagsinuse 218.773509 # Cycle average of tags in use 728system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 729system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. 730system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. 731system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 732system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.460945 # Average occupied blocks per requestor 733system.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor 734system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy 735system.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 736system.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy 737system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id 738system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 739system.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id 740system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id 741system.cpu.l2cache.tags.tag_accesses 4391 # Number of tag accesses 742system.cpu.l2cache.tags.data_accesses 4391 # Number of data accesses 743system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 744system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 745system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 746system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 747system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 748system.cpu.l2cache.overall_hits::total 1 # number of overall hits 749system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses 750system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 751system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses 752system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 753system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 754system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 756system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses 757system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses 758system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 759system.cpu.l2cache.overall_misses::total 487 # number of overall misses 760system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21990500 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7915750 # number of ReadReq miss cycles 762system.cpu.l2cache.ReadReq_miss_latency::total 29906250 # number of ReadReq miss cycles 763system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5408750 # number of ReadExReq miss cycles 764system.cpu.l2cache.ReadExReq_miss_latency::total 5408750 # number of ReadExReq miss cycles 765system.cpu.l2cache.demand_miss_latency::cpu.inst 21990500 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.data 13324500 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles 768system.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles 771system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 775system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 776system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses 777system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 778system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses 779system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses 780system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 781system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses 782system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses 785system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 786system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 787system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 788system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 789system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses 790system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 791system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 792system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses 793system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70257.188498 # average ReadReq miss latency 794system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157 # average ReadReq miss latency 795system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012 # average ReadReq miss latency 796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778 # average ReadExReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778 # average ReadExReq miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency 800system.cpu.l2cache.demand_avg_miss_latency::total 72515.400411 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::total 72515.400411 # average overall miss latency 804system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 809system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 810system.cpu.l2cache.fast_writes 0 # number of fast writes performed 811system.cpu.l2cache.cache_copies 0 # number of cache copies performed 812system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 813system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 814system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 815system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 816system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 817system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 818system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 819system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 821system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 822system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses 823system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18043000 # number of ReadReq MSHR miss cycles 824system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles 825system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles 826system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles 827system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles 828system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles 829system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles 832system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles 833system.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses 835system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 836system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 837system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 838system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 839system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 840system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 841system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses 842system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 843system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 844system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses 845system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency 846system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency 847system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency 848system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency 849system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency 850system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency 851system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency 853system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency 856system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 857system.cpu.dcache.tags.replacements 0 # number of replacements 858system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use 859system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. 860system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 861system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. 862system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 863system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor 864system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy 865system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy 866system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 867system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 868system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 869system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id 870system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses 871system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses 872system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits 873system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits 874system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 875system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 876system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits 877system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits 878system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits 879system.cpu.dcache.overall_hits::total 2314 # number of overall hits 880system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses 881system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses 882system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 883system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 884system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses 885system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses 886system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses 887system.cpu.dcache.overall_misses::total 522 # number of overall misses 888system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles 889system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles 890system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles 891system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles 892system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles 893system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles 894system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles 895system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles 896system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) 897system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) 898system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 899system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 900system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses 901system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses 902system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses 903system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses 904system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses 905system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses 906system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 907system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 908system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses 909system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses 910system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses 911system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses 912system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency 913system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency 914system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency 915system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency 916system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency 917system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency 918system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency 919system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency 920system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked 921system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked 923system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked 925system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.dcache.fast_writes 0 # number of fast writes performed 927system.cpu.dcache.cache_copies 0 # number of cache copies performed 928system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 929system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits 930system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 931system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 932system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits 933system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits 934system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits 935system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits 936system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 937system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 938system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 939system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 940system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 941system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 942system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 943system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 944system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles 945system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles 946system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles 947system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles 948system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles 949system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles 950system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles 951system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles 952system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses 953system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses 954system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 955system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 956system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses 957system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses 958system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses 959system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses 960system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency 961system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency 962system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency 963system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency 964system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency 965system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency 966system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency 967system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency 968system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 969 970---------- End Simulation Statistics ---------- 971