stats.txt revision 6291
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 76035 # Simulator instruction rate (inst/s) 4host_mem_usage 189864 # Number of bytes of host memory used 5host_seconds 0.08 # Real time elapsed on the host 6host_tick_rate 148017846 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 6386 # Number of instructions simulated 9sim_seconds 0.000012 # Number of seconds simulated 10sim_ticks 12474500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 2263 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 1051 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% 76.62% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% 89.72% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% 93.65% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% 95.80% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% 97.04% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.87% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% 98.65% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% 99.07% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle 39system.cpu.commit.COM:count 6403 # Number of instructions committed 40system.cpu.commit.COM:loads 1185 # Number of loads committed 41system.cpu.commit.COM:membars 0 # Number of memory barriers committed 42system.cpu.commit.COM:refs 2050 # Number of memory references committed 43system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 44system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted 45system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 46system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 47system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit 48system.cpu.committedInsts 6386 # Number of Instructions Simulated 49system.cpu.committedInsts_total 6386 # Number of Instructions Simulated 50system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction 51system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads 52system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) 53system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency 54system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency 55system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits 56system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles 57system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses 58system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses 59system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits 60system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles 61system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses 62system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses 63system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) 64system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency 65system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency 66system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits 67system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles 68system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses 70system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits 71system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles 72system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses 73system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses 74system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 76system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. 77system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 79system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81system.cpu.dcache.cache_copies 0 # number of cache copies performed 82system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses 83system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency 84system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency 85system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits 86system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles 87system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses 88system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses 89system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits 90system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles 91system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses 92system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses 93system.cpu.dcache.fast_writes 0 # number of fast writes performed 94system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 95system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 96system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses 97system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency 98system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency 99system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 100system.cpu.dcache.overall_hits 2104 # number of overall hits 101system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles 102system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses 103system.cpu.dcache.overall_misses 554 # number of overall misses 104system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits 105system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles 106system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses 107system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses 108system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 109system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 110system.cpu.dcache.replacements 0 # number of replacements 111system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 112system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 113system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use 114system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. 115system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.dcache.writebacks 0 # number of writebacks 117system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked 118system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction 119system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch 120system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode 121system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle 122system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running 123system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing 124system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode 125system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking 126system.cpu.dtb.data_accesses 2951 # DTB accesses 127system.cpu.dtb.data_acv 0 # DTB access violations 128system.cpu.dtb.data_hits 2890 # DTB hits 129system.cpu.dtb.data_misses 61 # DTB misses 130system.cpu.dtb.fetch_accesses 0 # ITB accesses 131system.cpu.dtb.fetch_acv 0 # ITB acv 132system.cpu.dtb.fetch_hits 0 # ITB hits 133system.cpu.dtb.fetch_misses 0 # ITB misses 134system.cpu.dtb.read_accesses 1876 # DTB read accesses 135system.cpu.dtb.read_acv 0 # DTB read access violations 136system.cpu.dtb.read_hits 1840 # DTB read hits 137system.cpu.dtb.read_misses 36 # DTB read misses 138system.cpu.dtb.write_accesses 1075 # DTB write accesses 139system.cpu.dtb.write_acv 0 # DTB write access violations 140system.cpu.dtb.write_hits 1050 # DTB write hits 141system.cpu.dtb.write_misses 25 # DTB write misses 142system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered 143system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched 144system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked 145system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed 146system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed 147system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing 148system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle 149system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss 150system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken 151system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle 152system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) 153system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) 154system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) 155system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 156system.cpu.fetch.rateDist::0-1 10844 81.45% 81.45% # Number of instructions fetched each cycle (Total) 157system.cpu.fetch.rateDist::1-2 252 1.89% 83.34% # Number of instructions fetched each cycle (Total) 158system.cpu.fetch.rateDist::2-3 238 1.79% 85.13% # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::3-4 230 1.73% 86.86% # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::4-5 272 2.04% 88.90% # Number of instructions fetched each cycle (Total) 161system.cpu.fetch.rateDist::5-6 162 1.22% 90.12% # Number of instructions fetched each cycle (Total) 162system.cpu.fetch.rateDist::6-7 232 1.74% 91.86% # Number of instructions fetched each cycle (Total) 163system.cpu.fetch.rateDist::7-8 129 0.97% 92.83% # Number of instructions fetched each cycle (Total) 164system.cpu.fetch.rateDist::8 955 7.17% 100.00% # Number of instructions fetched each cycle (Total) 165system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 166system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 167system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 168system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) 169system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) 170system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency 171system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency 172system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits 173system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles 174system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses 175system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses 176system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits 177system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles 178system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses 179system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses 180system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 181system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 182system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. 183system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 184system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 185system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 186system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 187system.cpu.icache.cache_copies 0 # number of cache copies performed 188system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses 189system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency 190system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency 191system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits 192system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles 193system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses 194system.cpu.icache.demand_misses 424 # number of demand (read+write) misses 195system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits 196system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles 197system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses 198system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses 199system.cpu.icache.fast_writes 0 # number of fast writes performed 200system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 201system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 202system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses 203system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency 204system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency 205system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 206system.cpu.icache.overall_hits 1378 # number of overall hits 207system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles 208system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses 209system.cpu.icache.overall_misses 424 # number of overall misses 210system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits 211system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles 212system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses 213system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses 214system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 215system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 216system.cpu.icache.replacements 0 # number of replacements 217system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. 218system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 219system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use 220system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. 221system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 222system.cpu.icache.writebacks 0 # number of writebacks 223system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling 224system.cpu.iew.EXEC:branches 1450 # Number of branches executed 225system.cpu.iew.EXEC:nop 82 # number of nop insts executed 226system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate 227system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed 228system.cpu.iew.EXEC:stores 1077 # Number of stores executed 229system.cpu.iew.EXEC:swp 0 # number of swp insts executed 230system.cpu.iew.WB:consumers 6020 # num instructions consuming a value 231system.cpu.iew.WB:count 8734 # cumulative count of insts written-back 232system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back 233system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 234system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 235system.cpu.iew.WB:producers 4491 # num instructions producing a value 236system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle 237system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit 238system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute 239system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking 240system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions 241system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions 242system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch 243system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions 244system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ 245system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed 246system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute 247system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions 248system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall 249system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 250system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 251system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing 252system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking 253system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 254system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 255system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores 256system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 257system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 258system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 259system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations 260system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 261system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed 262system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed 263system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations 264system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly 265system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly 266system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle 267system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads 268system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 269system.cpu.iq.ISSUE:FU_type_0::IntAlu 6254 66.92% 66.94% # Type of FU issued 270system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.96% # Type of FU issued 271system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.96% # Type of FU issued 272system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.98% # Type of FU issued 273system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.98% # Type of FU issued 274system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.98% # Type of FU issued 275system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.98% # Type of FU issued 276system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.98% # Type of FU issued 277system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.98% # Type of FU issued 278system.cpu.iq.ISSUE:FU_type_0::MemRead 1986 21.25% 88.23% # Type of FU issued 279system.cpu.iq.ISSUE:FU_type_0::MemWrite 1100 11.77% 100.00% # Type of FU issued 280system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 281system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 282system.cpu.iq.ISSUE:FU_type_0::total 9345 # Type of FU issued 283system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested 284system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) 285system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 286system.cpu.iq.ISSUE:fu_full::IntAlu 14 13.33% 13.33% # attempts to use FU when none available 287system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.33% # attempts to use FU when none available 288system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.33% # attempts to use FU when none available 289system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.33% # attempts to use FU when none available 290system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.33% # attempts to use FU when none available 291system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.33% # attempts to use FU when none available 292system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.33% # attempts to use FU when none available 293system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.33% # attempts to use FU when none available 294system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.33% # attempts to use FU when none available 295system.cpu.iq.ISSUE:fu_full::MemRead 56 53.33% 66.67% # attempts to use FU when none available 296system.cpu.iq.ISSUE:fu_full::MemWrite 35 33.33% 100.00% # attempts to use FU when none available 297system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 298system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 299system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 # Number of insts issued each cycle 300system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 # Number of insts issued each cycle 301system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 # Number of insts issued each cycle 302system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 303system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% 68.45% # Number of insts issued each cycle 304system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% 81.34% # Number of insts issued each cycle 305system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% 89.38% # Number of insts issued each cycle 306system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% 94.82% # Number of insts issued each cycle 307system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% 97.49% # Number of insts issued each cycle 308system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% 98.78% # Number of insts issued each cycle 309system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% 99.65% # Number of insts issued each cycle 310system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% 99.90% # Number of insts issued each cycle 311system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle 312system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 313system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 314system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 315system.cpu.iq.ISSUE:issued_per_cycle::total 13314 # Number of insts issued each cycle 316system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate 317system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) 318system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued 319system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ 320system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling 321system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued 322system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed 323system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph 324system.cpu.itb.data_accesses 0 # DTB accesses 325system.cpu.itb.data_acv 0 # DTB access violations 326system.cpu.itb.data_hits 0 # DTB hits 327system.cpu.itb.data_misses 0 # DTB misses 328system.cpu.itb.fetch_accesses 1838 # ITB accesses 329system.cpu.itb.fetch_acv 0 # ITB acv 330system.cpu.itb.fetch_hits 1802 # ITB hits 331system.cpu.itb.fetch_misses 36 # ITB misses 332system.cpu.itb.read_accesses 0 # DTB read accesses 333system.cpu.itb.read_acv 0 # DTB read access violations 334system.cpu.itb.read_hits 0 # DTB read hits 335system.cpu.itb.read_misses 0 # DTB read misses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.write_acv 0 # DTB write access violations 338system.cpu.itb.write_hits 0 # DTB write hits 339system.cpu.itb.write_misses 0 # DTB write misses 340system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 341system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency 342system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency 343system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 345system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 346system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles 347system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 348system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 349system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) 350system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency 351system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency 352system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 353system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles 354system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses 355system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses 356system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles 357system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses 358system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses 359system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) 360system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency 361system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency 362system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles 363system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 364system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses 365system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles 366system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses 367system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses 368system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 369system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 370system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. 371system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.cache_copies 0 # number of cache copies performed 376system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency 378system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency 379system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 380system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles 381system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses 382system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses 383system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 384system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles 385system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses 386system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.fast_writes 0 # number of fast writes performed 388system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 389system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 390system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses 391system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency 392system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency 393system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 394system.cpu.l2cache.overall_hits 1 # number of overall hits 395system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles 396system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses 397system.cpu.l2cache.overall_misses 480 # number of overall misses 398system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 399system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses 401system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses 402system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 403system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 404system.cpu.l2cache.replacements 0 # number of replacements 405system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. 406system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 407system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use 408system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 409system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 410system.cpu.l2cache.writebacks 0 # number of writebacks 411system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. 412system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 413system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. 414system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. 415system.cpu.numCycles 24950 # number of cpu cycles simulated 416system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking 417system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed 418system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full 419system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle 420system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full 421system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made 422system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename 423system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed 424system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running 425system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing 426system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking 427system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing 428system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst 429system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed 430system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer 431system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed 432system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself 433system.cpu.workload.PROG:num_syscalls 17 # Number of system calls 434 435---------- End Simulation Statistics ---------- 436