stats.txt revision 5520
1 2---------- Begin Simulation Statistics ---------- 3global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4global.BPredUnit.BTBHits 649 # Number of BTB hits 5global.BPredUnit.BTBLookups 1748 # Number of BTB lookups 6global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 7global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect 8global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted 9global.BPredUnit.lookups 2108 # Number of BP lookups 10global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target. 11host_inst_rate 87257 # Simulator instruction rate (inst/s) 12host_mem_usage 198272 # Number of bytes of host memory used 13host_seconds 0.07 # Real time elapsed on the host 14host_tick_rate 171219532 # Simulator tick rate (ticks/s) 15memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. 16memdepunit.memDep.conflictingStores 28 # Number of conflicting stores. 17memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit. 18memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit. 19sim_freq 1000000000000 # Frequency of simulated ticks 20sim_insts 6297 # Number of instructions simulated 21sim_seconds 0.000012 # Number of seconds simulated 22sim_ticks 12391500 # Number of ticks simulated 23system.cpu.commit.COM:branches 1012 # Number of branches committed 24system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached 25system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 26system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle.samples 12114 28system.cpu.commit.COM:committed_per_cycle.min_value 0 29 0 9249 7634.97% 30 1 1607 1326.56% 31 2 479 395.41% 32 3 271 223.71% 33 4 137 113.09% 34 5 121 99.88% 35 6 87 71.82% 36 7 43 35.50% 37 8 120 99.06% 38system.cpu.commit.COM:committed_per_cycle.max_value 8 39system.cpu.commit.COM:committed_per_cycle.end_dist 40 41system.cpu.commit.COM:count 6314 # Number of instructions committed 42system.cpu.commit.COM:loads 1168 # Number of loads committed 43system.cpu.commit.COM:membars 0 # Number of memory barriers committed 44system.cpu.commit.COM:refs 2030 # Number of memory references committed 45system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 46system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted 47system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions 48system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 49system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit 50system.cpu.committedInsts 6297 # Number of Instructions Simulated 51system.cpu.committedInsts_total 6297 # Number of Instructions Simulated 52system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction 53system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads 54system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses) 55system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency 56system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency 57system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits 58system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles 59system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses 60system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses 61system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits 62system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles 63system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses 64system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses 65system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) 66system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency 67system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency 68system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits 69system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles 70system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses 71system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses 72system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses 75system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses 76system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 77system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 78system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks. 79system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked 81system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.cache_copies 0 # number of cache copies performed 84system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses 85system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency 86system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency 87system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits 88system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles 89system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses 90system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses 91system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits 92system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles 93system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses 94system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses 95system.cpu.dcache.fast_writes 0 # number of fast writes performed 96system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 97system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 98system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses 99system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency 100system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency 101system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 102system.cpu.dcache.overall_hits 2058 # number of overall hits 103system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles 104system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses 105system.cpu.dcache.overall_misses 542 # number of overall misses 106system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits 107system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles 108system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses 109system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses 110system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 111system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 112system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 113system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 114system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 115system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 116system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 117system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 118system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 119system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 120system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 121system.cpu.dcache.replacements 0 # number of replacements 122system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks. 123system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 124system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use 125system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks. 126system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 127system.cpu.dcache.writebacks 0 # number of writebacks 128system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked 129system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction 130system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch 131system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode 132system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle 133system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running 134system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing 135system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode 136system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking 137system.cpu.dtb.accesses 2892 # DTB accesses 138system.cpu.dtb.acv 0 # DTB access violations 139system.cpu.dtb.hits 2831 # DTB hits 140system.cpu.dtb.misses 61 # DTB misses 141system.cpu.dtb.read_accesses 1821 # DTB read accesses 142system.cpu.dtb.read_acv 0 # DTB read access violations 143system.cpu.dtb.read_hits 1785 # DTB read hits 144system.cpu.dtb.read_misses 36 # DTB read misses 145system.cpu.dtb.write_accesses 1071 # DTB write accesses 146system.cpu.dtb.write_acv 0 # DTB write access violations 147system.cpu.dtb.write_hits 1046 # DTB write hits 148system.cpu.dtb.write_misses 25 # DTB write misses 149system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered 150system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched 151system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked 152system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed 153system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed 154system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing 155system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle 156system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss 157system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken 158system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle 159system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist.samples 12970 161system.cpu.fetch.rateDist.min_value 0 162 0 10663 8221.28% 163 1 241 185.81% 164 2 214 165.00% 165 3 169 130.30% 166 4 208 160.37% 167 5 163 125.67% 168 6 215 165.77% 169 7 128 98.69% 170 8 969 747.11% 171system.cpu.fetch.rateDist.max_value 8 172system.cpu.fetch.rateDist.end_dist 173 174system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses) 175system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency 176system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency 177system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits 178system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles 179system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses 180system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses 181system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits 182system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles 183system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses 184system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses 185system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 186system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 187system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks. 188system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked 189system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked 190system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 191system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 192system.cpu.icache.cache_copies 0 # number of cache copies performed 193system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses 194system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency 195system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency 196system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits 197system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles 198system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses 199system.cpu.icache.demand_misses 426 # number of demand (read+write) misses 200system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits 201system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles 202system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses 203system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses 204system.cpu.icache.fast_writes 0 # number of fast writes performed 205system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 206system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 207system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses 208system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency 209system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency 210system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 211system.cpu.icache.overall_hits 1278 # number of overall hits 212system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles 213system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses 214system.cpu.icache.overall_misses 426 # number of overall misses 215system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits 216system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles 217system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses 218system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses 219system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 220system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 221system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 222system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 223system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 224system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 225system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 226system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 227system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 228system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 229system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 230system.cpu.icache.replacements 0 # number of replacements 231system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks. 232system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 233system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use 234system.cpu.icache.total_refs 1278 # Total number of references to valid blocks. 235system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 236system.cpu.icache.writebacks 0 # number of writebacks 237system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling 238system.cpu.iew.EXEC:branches 1375 # Number of branches executed 239system.cpu.iew.EXEC:nop 76 # number of nop insts executed 240system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate 241system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed 242system.cpu.iew.EXEC:stores 1073 # Number of stores executed 243system.cpu.iew.EXEC:swp 0 # number of swp insts executed 244system.cpu.iew.WB:consumers 5878 # num instructions consuming a value 245system.cpu.iew.WB:count 8512 # cumulative count of insts written-back 246system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back 247system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 248system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 249system.cpu.iew.WB:producers 4396 # num instructions producing a value 250system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle 251system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit 252system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute 253system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking 254system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions 255system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions 256system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch 257system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions 258system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ 259system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed 260system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute 261system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions 262system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 263system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 264system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 265system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing 266system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking 267system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 268system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 269system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores 270system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 271system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 272system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 273system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations 274system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled 275system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed 276system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed 277system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations 278system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly 279system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly 280system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle 281system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads 282system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued 283system.cpu.iq.ISSUE:FU_type_0.start_dist 284 No_OpClass 2 0.02% # Type of FU issued 285 IntAlu 6072 66.72% # Type of FU issued 286 IntMult 1 0.01% # Type of FU issued 287 IntDiv 0 0.00% # Type of FU issued 288 FloatAdd 2 0.02% # Type of FU issued 289 FloatCmp 0 0.00% # Type of FU issued 290 FloatCvt 0 0.00% # Type of FU issued 291 FloatMult 0 0.00% # Type of FU issued 292 FloatDiv 0 0.00% # Type of FU issued 293 FloatSqrt 0 0.00% # Type of FU issued 294 MemRead 1928 21.18% # Type of FU issued 295 MemWrite 1096 12.04% # Type of FU issued 296 IprAccess 0 0.00% # Type of FU issued 297 InstPrefetch 0 0.00% # Type of FU issued 298system.cpu.iq.ISSUE:FU_type_0.end_dist 299system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested 300system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst) 301system.cpu.iq.ISSUE:fu_full.start_dist 302 No_OpClass 0 0.00% # attempts to use FU when none available 303 IntAlu 2 2.15% # attempts to use FU when none available 304 IntMult 0 0.00% # attempts to use FU when none available 305 IntDiv 0 0.00% # attempts to use FU when none available 306 FloatAdd 0 0.00% # attempts to use FU when none available 307 FloatCmp 0 0.00% # attempts to use FU when none available 308 FloatCvt 0 0.00% # attempts to use FU when none available 309 FloatMult 0 0.00% # attempts to use FU when none available 310 FloatDiv 0 0.00% # attempts to use FU when none available 311 FloatSqrt 0 0.00% # attempts to use FU when none available 312 MemRead 56 60.22% # attempts to use FU when none available 313 MemWrite 35 37.63% # attempts to use FU when none available 314 IprAccess 0 0.00% # attempts to use FU when none available 315 InstPrefetch 0 0.00% # attempts to use FU when none available 316system.cpu.iq.ISSUE:fu_full.end_dist 317system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle 318system.cpu.iq.ISSUE:issued_per_cycle.samples 12970 319system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 320 0 8890 6854.28% 321 1 1667 1285.27% 322 2 1037 799.54% 323 3 696 536.62% 324 4 340 262.14% 325 5 189 145.72% 326 6 103 79.41% 327 7 35 26.99% 328 8 13 10.02% 329system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 330system.cpu.iq.ISSUE:issued_per_cycle.end_dist 331 332system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate 333system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec) 334system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued 335system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ 336system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling 337system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued 338system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed 339system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph 340system.cpu.itb.accesses 1737 # ITB accesses 341system.cpu.itb.acv 0 # ITB acv 342system.cpu.itb.hits 1704 # ITB hits 343system.cpu.itb.misses 33 # ITB misses 344system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 345system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency 346system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency 347system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles 348system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 349system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 350system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles 351system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 352system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 353system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses) 354system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency 355system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency 356system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 357system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles 358system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses 359system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses 360system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles 361system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses 362system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses 363system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) 364system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency 365system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency 366system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles 367system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 368system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses 369system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles 370system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses 371system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses 372system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 373system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 374system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. 375system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked 376system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked 377system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 378system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked 379system.cpu.l2cache.cache_copies 0 # number of cache copies performed 380system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses 381system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency 382system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency 383system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 384system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles 385system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses 386system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses 387system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 388system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles 389system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses 390system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses 391system.cpu.l2cache.fast_writes 0 # number of fast writes performed 392system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 393system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 394system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses 395system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency 396system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency 397system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 398system.cpu.l2cache.overall_hits 1 # number of overall hits 399system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles 400system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses 401system.cpu.l2cache.overall_misses 479 # number of overall misses 402system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 403system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles 404system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses 405system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 407system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 408system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 409system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 410system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 411system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 412system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 413system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 414system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 415system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 416system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 417system.cpu.l2cache.replacements 0 # number of replacements 418system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. 419system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 420system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use 421system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 422system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 423system.cpu.l2cache.writebacks 0 # number of writebacks 424system.cpu.numCycles 24784 # number of cpu cycles simulated 425system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking 426system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed 427system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full 428system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle 429system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full 430system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made 431system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename 432system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed 433system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running 434system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing 435system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking 436system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing 437system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst 438system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed 439system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer 440system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed 441system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself 442system.cpu.workload.PROG:num_syscalls 17 # Number of system calls 443 444---------- End Simulation Statistics ---------- 445