stats.txt revision 10242
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000021 # Number of seconds simulated 410220Sandreas.hansson@arm.comsim_ticks 21025000 # Number of ticks simulated 510220Sandreas.hansson@arm.comfinal_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710242Ssteve.reinhardt@amd.comhost_inst_rate 63804 # Simulator instruction rate (inst/s) 810242Ssteve.reinhardt@amd.comhost_op_rate 63793 # Simulator op (including micro ops) rate (op/s) 910242Ssteve.reinhardt@amd.comhost_tick_rate 210460029 # Simulator tick rate (ticks/s) 1010242Ssteve.reinhardt@amd.comhost_mem_usage 221600 # Number of bytes of host memory used 1110242Ssteve.reinhardt@amd.comhost_seconds 0.10 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 179322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31168 # Number of bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 209729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 219729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 229322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 239729Sandreas.hansson@arm.comsystem.physmem.num_reads::total 487 # Number of read requests responded to by this memory 2410220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) 2510220Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) 2610220Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) 2710220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) 2810220Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) 2910220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) 3010220Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) 3110220Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) 329978Sandreas.hansson@arm.comsystem.physmem.readReqs 488 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 399978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 31232 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 69 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 34 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 32 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 43 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 21 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 23 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 119 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 12 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810220Sandreas.hansson@arm.comsystem.physmem.totGap 20992000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 488 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see 9410242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 9510242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 9610242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 979729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 19010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation 19110242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::gmean 222.888418 # Bytes accessed per row activation 19210242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::stdev 329.838248 # Bytes accessed per row activation 19310242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::0-127 22 27.85% 27.85% # Bytes accessed per row activation 19410242Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::128-255 18 22.78% 50.63% # Bytes accessed per row activation 19510220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation 19610220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation 19710220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation 19810220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation 19910220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation 20010220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation 20110220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation 20210220Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 20310242Ssteve.reinhardt@amd.comsystem.physmem.totQLat 4169250 # Total ticks spent queuing 20410242Ssteve.reinhardt@amd.comsystem.physmem.totMemAccLat 13319250 # Total ticks spent from burst creation until serviced by the DRAM 2059978Sandreas.hansson@arm.comsystem.physmem.totBusLat 2440000 # Total ticks spent in databus transfers 20610242Ssteve.reinhardt@amd.comsystem.physmem.avgQLat 8543.55 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810242Ssteve.reinhardt@amd.comsystem.physmem.avgMemAccLat 27293.55 # Average memory access latency per DRAM burst 20910220Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110220Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410220Sandreas.hansson@arm.comsystem.physmem.busUtil 11.61 # Data bus utilization in percentage 21510220Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710220Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910148Sandreas.hansson@arm.comsystem.physmem.readRowHits 394 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110148Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310220Sandreas.hansson@arm.comsystem.physmem.avgGap 43016.39 # Average gap between requests 22410148Sandreas.hansson@arm.comsystem.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined 22510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 22000 # Time in different power states 22610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22810220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 15304250 # Time in different power states 22910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23010220Sandreas.hansson@arm.comsystem.membus.throughput 1482425684 # Throughput (bytes/s) 23110242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadReq 416 # Transaction distribution 23210242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadResp 415 # Transaction distribution 23310242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExReq 72 # Transaction distribution 23410242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExResp 72 # Transaction distribution 2359838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 2369838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 2379838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 2389838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 2399729Sandreas.hansson@arm.comsystem.membus.data_through_bus 31168 # Total data (bytes) 2409729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 24110242Ssteve.reinhardt@amd.comsystem.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) 2429978Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 24310242Ssteve.reinhardt@amd.comsystem.membus.respLayer1.occupancy 4554750 # Layer occupancy (ticks) 24410220Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 21.7 # Layer utilization (%) 24510036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 24610242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.lookups 2922 # Number of BP lookups 24710242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.condPredicted 1714 # Number of conditional branches predicted 24810148Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect 24910242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.BTBLookups 2236 # Number of BTB lookups 25010242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.BTBHits 763 # Number of BTB hits 2519481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25210242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.BTBHitPct 34.123435 # BTB Hit Percentage 25310242Ssteve.reinhardt@amd.comsystem.cpu.branchPred.usedRAS 417 # Number of times the RAS was used to get a target. 2549490Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 2558428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2568428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2578428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2588428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 25910242Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_hits 2080 # DTB read hits 2609729Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 47 # DTB read misses 2618428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 26210242Ssteve.reinhardt@amd.comsystem.cpu.dtb.read_accesses 2127 # DTB read accesses 26310242Ssteve.reinhardt@amd.comsystem.cpu.dtb.write_hits 1064 # DTB write hits 2649729Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 31 # DTB write misses 2658428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 26610242Ssteve.reinhardt@amd.comsystem.cpu.dtb.write_accesses 1095 # DTB write accesses 26710242Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_hits 3144 # DTB hits 2689729Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 78 # DTB misses 2698428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 27010242Ssteve.reinhardt@amd.comsystem.cpu.dtb.data_accesses 3222 # DTB accesses 27110242Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_hits 2403 # ITB hits 2729729Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 39 # ITB misses 2738428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 27410242Ssteve.reinhardt@amd.comsystem.cpu.itb.fetch_accesses 2442 # ITB accesses 2758428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2768428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2778428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2788428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2798428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2808428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2818428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2828428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2838428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2848428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2858428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2868428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2878428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 28810220Sandreas.hansson@arm.comsystem.cpu.numCycles 42051 # number of cpu cycles simulated 2898428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2908428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29110242Ssteve.reinhardt@amd.comsystem.cpu.fetch.icacheStallCycles 8528 # Number of cycles fetch is stalled on an Icache miss 29210242Ssteve.reinhardt@amd.comsystem.cpu.fetch.Insts 16754 # Number of instructions fetch has processed 29310242Ssteve.reinhardt@amd.comsystem.cpu.fetch.Branches 2922 # Number of branches that fetch encountered 29410242Ssteve.reinhardt@amd.comsystem.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 29510242Ssteve.reinhardt@amd.comsystem.cpu.fetch.Cycles 2995 # Number of cycles fetch has run and was not squashing or blocked 29610242Ssteve.reinhardt@amd.comsystem.cpu.fetch.SquashCycles 1927 # Number of cycles fetch has spent squashing 29710242Ssteve.reinhardt@amd.comsystem.cpu.fetch.BlockedCycles 1100 # Number of cycles fetch has spent blocked 2989729Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2999797Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps 30010242Ssteve.reinhardt@amd.comsystem.cpu.fetch.CacheLines 2403 # Number of cache lines fetched 30110242Ssteve.reinhardt@amd.comsystem.cpu.fetch.IcacheSquashes 389 # Number of outstanding Icache misses that were squashed 30210242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::samples 14718 # Number of instructions fetched each cycle (Total) 30310242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::mean 1.138334 # Number of instructions fetched each cycle (Total) 30410242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::stdev 2.533627 # Number of instructions fetched each cycle (Total) 3056291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 30610242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::0 11723 79.65% 79.65% # Number of instructions fetched each cycle (Total) 30710242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::1 324 2.20% 81.85% # Number of instructions fetched each cycle (Total) 30810242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::2 234 1.59% 83.44% # Number of instructions fetched each cycle (Total) 30910242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::3 214 1.45% 84.90% # Number of instructions fetched each cycle (Total) 31010242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::4 255 1.73% 86.63% # Number of instructions fetched each cycle (Total) 31110242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::5 243 1.65% 88.28% # Number of instructions fetched each cycle (Total) 31210242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::6 264 1.79% 90.07% # Number of instructions fetched each cycle (Total) 31310242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::7 187 1.27% 91.34% # Number of instructions fetched each cycle (Total) 31410242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::8 1274 8.66% 100.00% # Number of instructions fetched each cycle (Total) 3156291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3166291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3176291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 31810242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rateDist::total 14718 # Number of instructions fetched each cycle (Total) 31910242Ssteve.reinhardt@amd.comsystem.cpu.fetch.branchRate 0.069487 # Number of branch fetches per cycle 32010242Ssteve.reinhardt@amd.comsystem.cpu.fetch.rate 0.398421 # Number of inst fetches per cycle 32110242Ssteve.reinhardt@amd.comsystem.cpu.decode.IdleCycles 9297 # Number of cycles decode is idle 32210242Ssteve.reinhardt@amd.comsystem.cpu.decode.BlockedCycles 1311 # Number of cycles decode is blocked 32310242Ssteve.reinhardt@amd.comsystem.cpu.decode.RunCycles 2827 # Number of cycles decode is running 32410242Ssteve.reinhardt@amd.comsystem.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking 32510242Ssteve.reinhardt@amd.comsystem.cpu.decode.SquashCycles 1242 # Number of cycles decode is squashing 32610242Ssteve.reinhardt@amd.comsystem.cpu.decode.BranchResolved 247 # Number of times decode resolved a branch 32710148Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction 32810242Ssteve.reinhardt@amd.comsystem.cpu.decode.DecodedInsts 15491 # Number of instructions handled by decode 3299729Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 33010242Ssteve.reinhardt@amd.comsystem.cpu.rename.SquashCycles 1242 # Number of cycles rename is squashing 33110242Ssteve.reinhardt@amd.comsystem.cpu.rename.IdleCycles 9496 # Number of cycles rename is idle 33210242Ssteve.reinhardt@amd.comsystem.cpu.rename.BlockCycles 220 # Number of cycles rename is blocking 33310242Ssteve.reinhardt@amd.comsystem.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst 33410242Ssteve.reinhardt@amd.comsystem.cpu.rename.RunCycles 2672 # Number of cycles rename is running 33510242Ssteve.reinhardt@amd.comsystem.cpu.rename.UnblockCycles 534 # Number of cycles rename is unblocking 33610242Ssteve.reinhardt@amd.comsystem.cpu.rename.RenamedInsts 14802 # Number of instructions processed by rename 33710242Ssteve.reinhardt@amd.comsystem.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full 33810242Ssteve.reinhardt@amd.comsystem.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full 33910242Ssteve.reinhardt@amd.comsystem.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full 34010242Ssteve.reinhardt@amd.comsystem.cpu.rename.SQFullEvents 481 # Number of times rename has blocked due to SQ full 34110242Ssteve.reinhardt@amd.comsystem.cpu.rename.RenamedOperands 11114 # Number of destination operands rename has renamed 34210242Ssteve.reinhardt@amd.comsystem.cpu.rename.RenameLookups 18470 # Number of register rename lookups that rename has made 34310242Ssteve.reinhardt@amd.comsystem.cpu.rename.int_rename_lookups 18461 # Number of integer rename lookups 3449924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 3459150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 34610242Ssteve.reinhardt@amd.comsystem.cpu.rename.UndoneMaps 6544 # Number of HB maps that are undone due to squashing 34710242Ssteve.reinhardt@amd.comsystem.cpu.rename.serializingInsts 31 # count of serializing insts renamed 34810242Ssteve.reinhardt@amd.comsystem.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed 34910242Ssteve.reinhardt@amd.comsystem.cpu.rename.skidInsts 484 # count of insts added to the skid buffer 35010242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 35110242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.insertedStores 1358 # Number of stores inserted to the mem dependence unit. 35210242Ssteve.reinhardt@amd.comsystem.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 3538428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 35410242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqInstsAdded 13092 # Number of instructions added to the IQ (excludes non-spec) 3559797Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ 35610242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqInstsIssued 10822 # Number of instructions issued 35710242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedInstsIssued 61 # Number of squashed instructions issued 35810242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedInstsExamined 6316 # Number of squashed instructions iterated over during squash; mainly for profiling 35910242Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedOperandsExamined 3704 # Number of squashed operands that are examined and possibly removed from graph 3609797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 36110242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::samples 14718 # Number of insts issued each cycle 36210242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::mean 0.735290 # Number of insts issued each cycle 36310242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::stdev 1.419888 # Number of insts issued each cycle 3648428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 36510242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::0 10506 71.38% 71.38% # Number of insts issued each cycle 36610242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::1 1362 9.25% 80.64% # Number of insts issued each cycle 36710242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::2 966 6.56% 87.20% # Number of insts issued each cycle 36810242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::3 797 5.42% 92.61% # Number of insts issued each cycle 36910242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::4 583 3.96% 96.58% # Number of insts issued each cycle 37010242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::5 288 1.96% 98.53% # Number of insts issued each cycle 37110242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::6 161 1.09% 99.63% # Number of insts issued each cycle 37210242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::7 41 0.28% 99.90% # Number of insts issued each cycle 37310242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 3748428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3758428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3768428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 37710242Ssteve.reinhardt@amd.comsystem.cpu.iq.issued_per_cycle::total 14718 # Number of insts issued each cycle 3788428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 37910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::IntAlu 18 15.38% 15.38% # attempts to use FU when none available 38010242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 15.38% # attempts to use FU when none available 38110242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 15.38% # attempts to use FU when none available 38210242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 15.38% # attempts to use FU when none available 38310242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 15.38% # attempts to use FU when none available 38410242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 15.38% # attempts to use FU when none available 38510242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 15.38% # attempts to use FU when none available 38610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 15.38% # attempts to use FU when none available 38710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.38% # attempts to use FU when none available 38810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 15.38% # attempts to use FU when none available 38910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.38% # attempts to use FU when none available 39010242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 15.38% # attempts to use FU when none available 39110242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 15.38% # attempts to use FU when none available 39210242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 15.38% # attempts to use FU when none available 39310242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 15.38% # attempts to use FU when none available 39410242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 15.38% # attempts to use FU when none available 39510242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.38% # attempts to use FU when none available 39610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 15.38% # attempts to use FU when none available 39710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.38% # attempts to use FU when none available 39810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.38% # attempts to use FU when none available 39910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.38% # attempts to use FU when none available 40010242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.38% # attempts to use FU when none available 40110242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.38% # attempts to use FU when none available 40210242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.38% # attempts to use FU when none available 40310242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.38% # attempts to use FU when none available 40410242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.38% # attempts to use FU when none available 40510242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.38% # attempts to use FU when none available 40610242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.38% # attempts to use FU when none available 40710242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.38% # attempts to use FU when none available 40810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::MemRead 61 52.14% 67.52% # attempts to use FU when none available 40910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_full::MemWrite 38 32.48% 100.00% # attempts to use FU when none available 4108428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4118428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4128241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 41310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::IntAlu 7283 67.30% 67.32% # Type of FU issued 41410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.33% # Type of FU issued 41510242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.33% # Type of FU issued 41610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.34% # Type of FU issued 41710242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued 41810242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued 41910242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued 42010242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued 42110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued 42210242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued 42310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued 42410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued 42510242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued 42610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued 42710242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued 42810242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued 42910242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued 43010242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued 43110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued 43210242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued 43310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued 43410242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued 43510242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued 43610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued 43710242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued 43810242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued 43910242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued 44010242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued 44110242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued 44210242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::MemRead 2401 22.19% 89.53% # Type of FU issued 44310242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::MemWrite 1133 10.47% 100.00% # Type of FU issued 4448241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4458241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 44610242Ssteve.reinhardt@amd.comsystem.cpu.iq.FU_type_0::total 10822 # Type of FU issued 44710242Ssteve.reinhardt@amd.comsystem.cpu.iq.rate 0.257354 # Inst issue rate 44810242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_busy_cnt 117 # FU busy when requested 44910242Ssteve.reinhardt@amd.comsystem.cpu.iq.fu_busy_rate 0.010811 # FU busy rate (busy events/executed inst) 45010242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_reads 36519 # Number of integer instruction queue reads 45110242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_writes 19441 # Number of integer instruction queue writes 45210242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9646 # Number of integer instruction queue wakeup accesses 4538428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4548428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4558428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 45610242Ssteve.reinhardt@amd.comsystem.cpu.iq.int_alu_accesses 10926 # Number of integer alu accesses 4578428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 45810242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.forwLoads 74 # Number of loads that had data forwarded from stores 4598428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 46010242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.squashedLoads 1607 # Number of loads squashed 46110242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 46210148Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 46310242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.squashedStores 493 # Number of stores squashed 4648428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4658428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4668428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 46710242Ssteve.reinhardt@amd.comsystem.cpu.iew.lsq.thread0.cacheBlocked 138 # Number of times an access to memory failed due to the cache being blocked 4688428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 46910242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewSquashCycles 1242 # Number of cycles IEW is squashing 47010242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewBlockCycles 105 # Number of cycles IEW is blocking 47110242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 47210242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispatchedInsts 13210 # Number of instructions dispatched to IQ 47310242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch 47410242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 47510242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewDispStoreInsts 1358 # Number of dispatched store instructions 4769797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 4779348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 47810242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall 47910148Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 48010242Ssteve.reinhardt@amd.comsystem.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly 48110242Ssteve.reinhardt@amd.comsystem.cpu.iew.predictedNotTakenIncorrect 383 # Number of branches that were predicted not taken incorrectly 48210242Ssteve.reinhardt@amd.comsystem.cpu.iew.branchMispredicts 506 # Number of branch mispredicts detected at execute 48310242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewExecutedInsts 10117 # Number of executed instructions 48410242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewExecLoadInsts 2138 # Number of load instructions executed 48510242Ssteve.reinhardt@amd.comsystem.cpu.iew.iewExecSquashedInsts 705 # Number of squashed instructions skipped in execute 4868428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4879729Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 89 # number of nop insts executed 48810242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_refs 3235 # number of memory reference insts executed 48910242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_branches 1594 # Number of branches executed 49010242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_stores 1097 # Number of stores executed 49110242Ssteve.reinhardt@amd.comsystem.cpu.iew.exec_rate 0.240589 # Inst execution rate 49210242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_sent 9800 # cumulative count of insts sent to commit 49310242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_count 9656 # cumulative count of insts written-back 49410242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_producers 5168 # num instructions producing a value 49510242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_consumers 7004 # num instructions consuming a value 4968428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 49710242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_rate 0.229626 # insts written-back per cycle 49810242Ssteve.reinhardt@amd.comsystem.cpu.iew.wb_fanout 0.737864 # average fanout of values written-back 4998428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 50010242Ssteve.reinhardt@amd.comsystem.cpu.commit.commitSquashedInsts 6822 # The number of squashed insts skipped by commit 5018428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 50210148Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted 50310242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::samples 13476 # Number of insts commited each cycle 50410242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::mean 0.474102 # Number of insts commited each cycle 50510242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::stdev 1.366169 # Number of insts commited each cycle 5068428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 50710242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::0 10977 81.46% 81.46% # Number of insts commited each cycle 50810242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::1 1202 8.92% 90.38% # Number of insts commited each cycle 50910242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::2 500 3.71% 94.09% # Number of insts commited each cycle 51010242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::3 222 1.65% 95.73% # Number of insts commited each cycle 51110242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::4 141 1.05% 96.78% # Number of insts commited each cycle 51210242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::5 79 0.59% 97.37% # Number of insts commited each cycle 51310242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::6 99 0.73% 98.10% # Number of insts commited each cycle 51410242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::7 80 0.59% 98.69% # Number of insts commited each cycle 51510242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::8 176 1.31% 100.00% # Number of insts commited each cycle 5168428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5178428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5188428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 51910242Ssteve.reinhardt@amd.comsystem.cpu.commit.committed_per_cycle::total 13476 # Number of insts commited each cycle 5209150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 5219150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 5228428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5239150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 5249150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 5258428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5269150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 5278428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 5289150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 5298428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 53010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 53110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 53210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 53310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 53410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 53510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 53610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 53710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 53810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 53910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 54010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 54210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 54310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 54410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 54510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 54610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 54710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 54810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 54910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 55010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 55110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 55210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 55310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 55610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 55710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 55810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 55910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 56010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 56110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 56210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 56310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 56410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 6389 # Class of committed instruction 56510242Ssteve.reinhardt@amd.comsystem.cpu.commit.bw_lim_events 176 # number cycles where commit BW limit reached 5668428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 56710242Ssteve.reinhardt@amd.comsystem.cpu.rob.rob_reads 26160 # The number of ROB reads 56810242Ssteve.reinhardt@amd.comsystem.cpu.rob.rob_writes 27673 # The number of ROB writes 56910242Ssteve.reinhardt@amd.comsystem.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself 57010242Ssteve.reinhardt@amd.comsystem.cpu.idleCycles 27333 # Total number of cycles that the CPU has spent unscheduled due to idling 5719150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 5729150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 57310220Sandreas.hansson@arm.comsystem.cpu.cpi 6.599341 # CPI: Cycles Per Instruction 57410220Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads 57510220Sandreas.hansson@arm.comsystem.cpu.ipc 0.151530 # IPC: Instructions Per Cycle 57610220Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads 57710242Ssteve.reinhardt@amd.comsystem.cpu.int_regfile_reads 12844 # number of integer regfile reads 57810242Ssteve.reinhardt@amd.comsystem.cpu.int_regfile_writes 7306 # number of integer regfile writes 5798428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5808428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5818428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5828428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 58310220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) 58410242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadReq 417 # Transaction distribution 58510242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution 58610242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 58710242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 5889838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 5899838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 5909838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 5919838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 5929838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 5939838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 5949729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 5959729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5969729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 5979729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 59810220Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) 5999978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) 60010242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer1.occupancy 276750 # Layer occupancy (ticks) 6019978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 6029838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 60310242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tagsinuse 159.493349 # Cycle average of tags in use 60410242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.total_refs 1913 # Total number of references to valid blocks. 6059838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 60610242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.avg_refs 6.092357 # Average number of references to valid blocks. 6079838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60810242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 159.493349 # Average occupied blocks per requestor 60910242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077878 # Average percentage of cache occupancy 61010242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.occ_percent::total 0.077878 # Average percentage of cache occupancy 61110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 61210148Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 61310148Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 61410036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id 61510242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.tag_accesses 5120 # Number of tag accesses 61610242Ssteve.reinhardt@amd.comsystem.cpu.icache.tags.data_accesses 5120 # Number of data accesses 61710242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1913 # number of ReadReq hits 61810242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_hits::total 1913 # number of ReadReq hits 61910242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::cpu.inst 1913 # number of demand (read+write) hits 62010242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_hits::total 1913 # number of demand (read+write) hits 62110242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::cpu.inst 1913 # number of overall hits 62210242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_hits::total 1913 # number of overall hits 62310242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses 62410242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses 62510242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses 62610242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses 62710242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses 62810242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_misses::total 490 # number of overall misses 62910242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31404750 # number of ReadReq miss cycles 63010242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_latency::total 31404750 # number of ReadReq miss cycles 63110242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31404750 # number of demand (read+write) miss cycles 63210242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_latency::total 31404750 # number of demand (read+write) miss cycles 63310242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31404750 # number of overall miss cycles 63410242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_latency::total 31404750 # number of overall miss cycles 63510242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2403 # number of ReadReq accesses(hits+misses) 63610242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_accesses::total 2403 # number of ReadReq accesses(hits+misses) 63710242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::cpu.inst 2403 # number of demand (read+write) accesses 63810242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_accesses::total 2403 # number of demand (read+write) accesses 63910242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::cpu.inst 2403 # number of overall (read+write) accesses 64010242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_accesses::total 2403 # number of overall (read+write) accesses 64110242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.203912 # miss rate for ReadReq accesses 64210242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_miss_rate::total 0.203912 # miss rate for ReadReq accesses 64310242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.203912 # miss rate for demand accesses 64410242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_miss_rate::total 0.203912 # miss rate for demand accesses 64510242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.203912 # miss rate for overall accesses 64610242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_miss_rate::total 0.203912 # miss rate for overall accesses 64710242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64091.326531 # average ReadReq miss latency 64810242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 64091.326531 # average ReadReq miss latency 64910242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency 65010242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_miss_latency::total 64091.326531 # average overall miss latency 65110242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency 65210242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_miss_latency::total 64091.326531 # average overall miss latency 6538428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6548428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6558428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6568428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 6578983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6588983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6598428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6608428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 66110242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits 66210242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits 66310242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits 66410242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits 66510242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits 66610242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 6679729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 6689729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 6699729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 6709729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 6719729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 6729729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 67310242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22044500 # number of ReadReq MSHR miss cycles 67410242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 22044500 # number of ReadReq MSHR miss cycles 67510242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 22044500 # number of demand (read+write) MSHR miss cycles 67610242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_latency::total 22044500 # number of demand (read+write) MSHR miss cycles 67710242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 22044500 # number of overall MSHR miss cycles 67810242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_latency::total 22044500 # number of overall MSHR miss cycles 67910242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for ReadReq accesses 68010242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.131086 # mshr miss rate for ReadReq accesses 68110242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for demand accesses 68210242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.131086 # mshr miss rate for demand accesses 68310242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for overall accesses 68410242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.131086 # mshr miss rate for overall accesses 68510242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69982.539683 # average ReadReq mshr miss latency 68610242Ssteve.reinhardt@amd.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69982.539683 # average ReadReq mshr miss latency 68710242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency 68810242Ssteve.reinhardt@amd.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency 68910242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency 69010242Ssteve.reinhardt@amd.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency 6918428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6929838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 69310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.tagsinuse 219.991091 # Cycle average of tags in use 6949838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 69510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. 69610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. 6979838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 159.576725 # Average occupied blocks per requestor 69910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 60.414366 # Average occupied blocks per requestor 70010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004870 # Average percentage of cache occupancy 70110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy 70210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy 70310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id 70410148Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 70510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id 70610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id 70710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses 70810036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses 7098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 7108835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 7118835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 7128835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 7138835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 7148835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 7159729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 71610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 71710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses 71810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 71910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 7209729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 7219322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 7229729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 7239729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 7249322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 7259729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 488 # number of overall misses 72610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21718500 # number of ReadReq miss cycles 72710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7799500 # number of ReadReq miss cycles 72810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_latency::total 29518000 # number of ReadReq miss cycles 72910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5388750 # number of ReadExReq miss cycles 73010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5388750 # number of ReadExReq miss cycles 73110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21718500 # number of demand (read+write) miss cycles 73210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 13188250 # number of demand (read+write) miss cycles 73310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_miss_latency::total 34906750 # number of demand (read+write) miss cycles 73410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21718500 # number of overall miss cycles 73510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 13188250 # number of overall miss cycles 73610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_miss_latency::total 34906750 # number of overall miss cycles 7379729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 73810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 73910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) 74010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 74110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 7429729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 7439322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 7449729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 7459729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 7469322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 7479729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 7489729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 7498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 75010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses 7518835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 7529055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 7539729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 7548835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 7559729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 7569729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 7578835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 7589729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 75910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69167.197452 # average ReadReq miss latency 76010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76465.686275 # average ReadReq miss latency 76110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 70956.730769 # average ReadReq miss latency 76210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74843.750000 # average ReadExReq miss latency 76310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74843.750000 # average ReadExReq miss latency 76410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency 76510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency 76610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71530.225410 # average overall miss latency 76710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency 76810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency 76910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71530.225410 # average overall miss latency 7708428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7718428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7728428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7738428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7748983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7758983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7768428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7778428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7789729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 77910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 78010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses 78110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 78210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 7839729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 7849322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 7859729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 7869729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 7879322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 7889729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 78910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17765000 # number of ReadReq MSHR miss cycles 79010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6546500 # number of ReadReq MSHR miss cycles 79110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 24311500 # number of ReadReq MSHR miss cycles 79210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4505750 # number of ReadExReq MSHR miss cycles 79310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4505750 # number of ReadExReq MSHR miss cycles 79410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17765000 # number of demand (read+write) MSHR miss cycles 79510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11052250 # number of demand (read+write) MSHR miss cycles 79610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28817250 # number of demand (read+write) MSHR miss cycles 79710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17765000 # number of overall MSHR miss cycles 79810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11052250 # number of overall MSHR miss cycles 79910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28817250 # number of overall MSHR miss cycles 8009729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 8018835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 80210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses 8038835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8049055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 8059729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 8068835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 8079729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 8089729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 8098835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 8109729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 81110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56576.433121 # average ReadReq mshr miss latency 81210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64181.372549 # average ReadReq mshr miss latency 81310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58441.105769 # average ReadReq mshr miss latency 81410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62579.861111 # average ReadExReq mshr miss latency 81510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62579.861111 # average ReadExReq mshr miss latency 81610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency 81710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency 81810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency 81910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency 82010242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency 82110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency 8228428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8239838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 82410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tagsinuse 107.281632 # Cycle average of tags in use 82510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.total_refs 2231 # Total number of references to valid blocks. 8269838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 82710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.avg_refs 12.821839 # Average number of references to valid blocks. 8289838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 82910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 107.281632 # Average occupied blocks per requestor 83010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026192 # Average percentage of cache occupancy 83110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_percent::total 0.026192 # Average percentage of cache occupancy 83210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 83310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 83410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 83510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id 83610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.tag_accesses 5696 # Number of tag accesses 83710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.data_accesses 5696 # Number of data accesses 83810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1725 # number of ReadReq hits 83910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_hits::total 1725 # number of ReadReq hits 8409348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 8419348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 84210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::cpu.data 2231 # number of demand (read+write) hits 84310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_hits::total 2231 # number of demand (read+write) hits 84410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::cpu.data 2231 # number of overall hits 84510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_hits::total 2231 # number of overall hits 84610148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses 84710148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses 8489348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 8499348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 85010148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses 85110148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses 85210148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses 85310148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 530 # number of overall misses 85410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11477000 # number of ReadReq miss cycles 85510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_latency::total 11477000 # number of ReadReq miss cycles 85610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 23139722 # number of WriteReq miss cycles 85710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_miss_latency::total 23139722 # number of WriteReq miss cycles 85810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_latency::cpu.data 34616722 # number of demand (read+write) miss cycles 85910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_latency::total 34616722 # number of demand (read+write) miss cycles 86010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_latency::cpu.data 34616722 # number of overall miss cycles 86110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_latency::total 34616722 # number of overall miss cycles 86210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1896 # number of ReadReq accesses(hits+misses) 86310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_accesses::total 1896 # number of ReadReq accesses(hits+misses) 8649348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 8659348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 86610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::cpu.data 2761 # number of demand (read+write) accesses 86710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_accesses::total 2761 # number of demand (read+write) accesses 86810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::cpu.data 2761 # number of overall (read+write) accesses 86910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_accesses::total 2761 # number of overall (read+write) accesses 87010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090190 # miss rate for ReadReq accesses 87110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.090190 # miss rate for ReadReq accesses 8729348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 8739348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 87410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.191959 # miss rate for demand accesses 87510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_miss_rate::total 0.191959 # miss rate for demand accesses 87610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.191959 # miss rate for overall accesses 87710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_miss_rate::total 0.191959 # miss rate for overall accesses 87810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67116.959064 # average ReadReq miss latency 87910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 67116.959064 # average ReadReq miss latency 88010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64456.050139 # average WriteReq miss latency 88110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 64456.050139 # average WriteReq miss latency 88210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency 88310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_miss_latency::total 65314.569811 # average overall miss latency 88410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency 88510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_miss_latency::total 65314.569811 # average overall miss latency 88610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.blocked_cycles::no_mshrs 1676 # number of cycles access was blocked 8879348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked 8899348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 89010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 41.900000 # average number of cycles each access was blocked 8919348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8929348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8939348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8949729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 8959729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 89610148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 89710148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 89810148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits 89910148Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits 90010148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits 90110148Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits 90210148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 90310148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 90410148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 90510148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 9069348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 9079348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 9089348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 9099348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 91010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7909000 # number of ReadReq MSHR miss cycles 91110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7909000 # number of ReadReq MSHR miss cycles 91210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5463750 # number of WriteReq MSHR miss cycles 91310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5463750 # number of WriteReq MSHR miss cycles 91410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 13372750 # number of demand (read+write) MSHR miss cycles 91510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_latency::total 13372750 # number of demand (read+write) MSHR miss cycles 91610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 13372750 # number of overall MSHR miss cycles 91710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_latency::total 13372750 # number of overall MSHR miss cycles 91810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053797 # mshr miss rate for ReadReq accesses 91910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053797 # mshr miss rate for ReadReq accesses 92010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 92110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 92210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for demand accesses 92310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.063021 # mshr miss rate for demand accesses 92410242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for overall accesses 92510242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.063021 # mshr miss rate for overall accesses 92610242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77539.215686 # average ReadReq mshr miss latency 92710242Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77539.215686 # average ReadReq mshr miss latency 92810242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75885.416667 # average WriteReq mshr miss latency 92910242Ssteve.reinhardt@amd.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75885.416667 # average WriteReq mshr miss latency 93010242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency 93110242Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency 93210242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency 93310242Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency 9349348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9353096SN/A 9363096SN/A---------- End Simulation Statistics ---------- 937