config.ini revision 11268:8b4b55d79ddd
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.clk_domain] 41type=SrcClockDomain 42clock=1000 43domain_id=-1 44eventq_index=0 45init_perf_level=0 46voltage_domain=system.voltage_domain 47 48[system.cpu] 49type=DerivO3CPU 50children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55SQEntries=32 56SSITSize=1024 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=0 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=TournamentBP 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152 153[system.cpu.dcache] 154type=Cache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160demand_mshr_reserve=1 161eventq_index=0 162forward_snoops=true 163hit_latency=2 164is_read_only=false 165max_miss_count=0 166mshrs=4 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=262144 172system=system 173tags=system.cpu.dcache.tags 174tgts_per_mshr=20 175write_buffers=8 176writeback_clean=false 177cpu_side=system.cpu.dcache_port 178mem_side=system.cpu.toL2Bus.slave[1] 179 180[system.cpu.dcache.tags] 181type=LRU 182assoc=2 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=262144 189 190[system.cpu.dtb] 191type=AlphaTLB 192eventq_index=0 193size=64 194 195[system.cpu.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 199eventq_index=0 200 201[system.cpu.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 205eventq_index=0 206opList=system.cpu.fuPool.FUList0.opList 207 208[system.cpu.fuPool.FUList0.opList] 209type=OpDesc 210eventq_index=0 211opClass=IntAlu 212opLat=1 213pipelined=true 214 215[system.cpu.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 219eventq_index=0 220opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 221 222[system.cpu.fuPool.FUList1.opList0] 223type=OpDesc 224eventq_index=0 225opClass=IntMult 226opLat=3 227pipelined=true 228 229[system.cpu.fuPool.FUList1.opList1] 230type=OpDesc 231eventq_index=0 232opClass=IntDiv 233opLat=20 234pipelined=false 235 236[system.cpu.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 240eventq_index=0 241opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 242 243[system.cpu.fuPool.FUList2.opList0] 244type=OpDesc 245eventq_index=0 246opClass=FloatAdd 247opLat=2 248pipelined=true 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc 252eventq_index=0 253opClass=FloatCmp 254opLat=2 255pipelined=true 256 257[system.cpu.fuPool.FUList2.opList2] 258type=OpDesc 259eventq_index=0 260opClass=FloatCvt 261opLat=2 262pipelined=true 263 264[system.cpu.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 268eventq_index=0 269opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 270 271[system.cpu.fuPool.FUList3.opList0] 272type=OpDesc 273eventq_index=0 274opClass=FloatMult 275opLat=4 276pipelined=true 277 278[system.cpu.fuPool.FUList3.opList1] 279type=OpDesc 280eventq_index=0 281opClass=FloatDiv 282opLat=12 283pipelined=false 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc 287eventq_index=0 288opClass=FloatSqrt 289opLat=24 290pipelined=false 291 292[system.cpu.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 296eventq_index=0 297opList=system.cpu.fuPool.FUList4.opList 298 299[system.cpu.fuPool.FUList4.opList] 300type=OpDesc 301eventq_index=0 302opClass=MemRead 303opLat=1 304pipelined=true 305 306[system.cpu.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 310eventq_index=0 311opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 312 313[system.cpu.fuPool.FUList5.opList00] 314type=OpDesc 315eventq_index=0 316opClass=SimdAdd 317opLat=1 318pipelined=true 319 320[system.cpu.fuPool.FUList5.opList01] 321type=OpDesc 322eventq_index=0 323opClass=SimdAddAcc 324opLat=1 325pipelined=true 326 327[system.cpu.fuPool.FUList5.opList02] 328type=OpDesc 329eventq_index=0 330opClass=SimdAlu 331opLat=1 332pipelined=true 333 334[system.cpu.fuPool.FUList5.opList03] 335type=OpDesc 336eventq_index=0 337opClass=SimdCmp 338opLat=1 339pipelined=true 340 341[system.cpu.fuPool.FUList5.opList04] 342type=OpDesc 343eventq_index=0 344opClass=SimdCvt 345opLat=1 346pipelined=true 347 348[system.cpu.fuPool.FUList5.opList05] 349type=OpDesc 350eventq_index=0 351opClass=SimdMisc 352opLat=1 353pipelined=true 354 355[system.cpu.fuPool.FUList5.opList06] 356type=OpDesc 357eventq_index=0 358opClass=SimdMult 359opLat=1 360pipelined=true 361 362[system.cpu.fuPool.FUList5.opList07] 363type=OpDesc 364eventq_index=0 365opClass=SimdMultAcc 366opLat=1 367pipelined=true 368 369[system.cpu.fuPool.FUList5.opList08] 370type=OpDesc 371eventq_index=0 372opClass=SimdShift 373opLat=1 374pipelined=true 375 376[system.cpu.fuPool.FUList5.opList09] 377type=OpDesc 378eventq_index=0 379opClass=SimdShiftAcc 380opLat=1 381pipelined=true 382 383[system.cpu.fuPool.FUList5.opList10] 384type=OpDesc 385eventq_index=0 386opClass=SimdSqrt 387opLat=1 388pipelined=true 389 390[system.cpu.fuPool.FUList5.opList11] 391type=OpDesc 392eventq_index=0 393opClass=SimdFloatAdd 394opLat=1 395pipelined=true 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc 399eventq_index=0 400opClass=SimdFloatAlu 401opLat=1 402pipelined=true 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc 406eventq_index=0 407opClass=SimdFloatCmp 408opLat=1 409pipelined=true 410 411[system.cpu.fuPool.FUList5.opList14] 412type=OpDesc 413eventq_index=0 414opClass=SimdFloatCvt 415opLat=1 416pipelined=true 417 418[system.cpu.fuPool.FUList5.opList15] 419type=OpDesc 420eventq_index=0 421opClass=SimdFloatDiv 422opLat=1 423pipelined=true 424 425[system.cpu.fuPool.FUList5.opList16] 426type=OpDesc 427eventq_index=0 428opClass=SimdFloatMisc 429opLat=1 430pipelined=true 431 432[system.cpu.fuPool.FUList5.opList17] 433type=OpDesc 434eventq_index=0 435opClass=SimdFloatMult 436opLat=1 437pipelined=true 438 439[system.cpu.fuPool.FUList5.opList18] 440type=OpDesc 441eventq_index=0 442opClass=SimdFloatMultAcc 443opLat=1 444pipelined=true 445 446[system.cpu.fuPool.FUList5.opList19] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatSqrt 450opLat=1 451pipelined=true 452 453[system.cpu.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 457eventq_index=0 458opList=system.cpu.fuPool.FUList6.opList 459 460[system.cpu.fuPool.FUList6.opList] 461type=OpDesc 462eventq_index=0 463opClass=MemWrite 464opLat=1 465pipelined=true 466 467[system.cpu.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 471eventq_index=0 472opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 473 474[system.cpu.fuPool.FUList7.opList0] 475type=OpDesc 476eventq_index=0 477opClass=MemRead 478opLat=1 479pipelined=true 480 481[system.cpu.fuPool.FUList7.opList1] 482type=OpDesc 483eventq_index=0 484opClass=MemWrite 485opLat=1 486pipelined=true 487 488[system.cpu.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 492eventq_index=0 493opList=system.cpu.fuPool.FUList8.opList 494 495[system.cpu.fuPool.FUList8.opList] 496type=OpDesc 497eventq_index=0 498opClass=IprAccess 499opLat=3 500pipelined=false 501 502[system.cpu.icache] 503type=Cache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=2 507clk_domain=system.cpu_clk_domain 508clusivity=mostly_incl 509demand_mshr_reserve=1 510eventq_index=0 511forward_snoops=true 512hit_latency=2 513is_read_only=true 514max_miss_count=0 515mshrs=4 516prefetch_on_access=false 517prefetcher=Null 518response_latency=2 519sequential_access=false 520size=131072 521system=system 522tags=system.cpu.icache.tags 523tgts_per_mshr=20 524write_buffers=8 525writeback_clean=true 526cpu_side=system.cpu.icache_port 527mem_side=system.cpu.toL2Bus.slave[0] 528 529[system.cpu.icache.tags] 530type=LRU 531assoc=2 532block_size=64 533clk_domain=system.cpu_clk_domain 534eventq_index=0 535hit_latency=2 536sequential_access=false 537size=131072 538 539[system.cpu.interrupts] 540type=AlphaInterrupts 541eventq_index=0 542 543[system.cpu.isa] 544type=AlphaISA 545eventq_index=0 546system=system 547 548[system.cpu.itb] 549type=AlphaTLB 550eventq_index=0 551size=48 552 553[system.cpu.l2cache] 554type=Cache 555children=tags 556addr_ranges=0:18446744073709551615 557assoc=8 558clk_domain=system.cpu_clk_domain 559clusivity=mostly_incl 560demand_mshr_reserve=1 561eventq_index=0 562forward_snoops=true 563hit_latency=20 564is_read_only=false 565max_miss_count=0 566mshrs=20 567prefetch_on_access=false 568prefetcher=Null 569response_latency=20 570sequential_access=false 571size=2097152 572system=system 573tags=system.cpu.l2cache.tags 574tgts_per_mshr=12 575write_buffers=8 576writeback_clean=false 577cpu_side=system.cpu.toL2Bus.master[0] 578mem_side=system.membus.slave[1] 579 580[system.cpu.l2cache.tags] 581type=LRU 582assoc=8 583block_size=64 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586hit_latency=20 587sequential_access=false 588size=2097152 589 590[system.cpu.toL2Bus] 591type=CoherentXBar 592children=snoop_filter 593clk_domain=system.cpu_clk_domain 594eventq_index=0 595forward_latency=0 596frontend_latency=1 597response_latency=1 598snoop_filter=system.cpu.toL2Bus.snoop_filter 599snoop_response_latency=1 600system=system 601use_default_range=false 602width=32 603master=system.cpu.l2cache.cpu_side 604slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 605 606[system.cpu.toL2Bus.snoop_filter] 607type=SnoopFilter 608eventq_index=0 609lookup_latency=0 610max_capacity=8388608 611system=system 612 613[system.cpu.tracer] 614type=ExeTracer 615eventq_index=0 616 617[system.cpu.workload] 618type=LiveProcess 619cmd=hello 620cwd= 621drivers= 622egid=100 623env= 624errout=cerr 625euid=100 626eventq_index=0 627executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello 628gid=100 629input=cin 630kvmInSE=false 631max_stack_size=67108864 632output=cout 633pid=100 634ppid=99 635simpoint=0 636system=system 637uid=100 638useArchPT=false 639 640[system.cpu_clk_domain] 641type=SrcClockDomain 642clock=500 643domain_id=-1 644eventq_index=0 645init_perf_level=0 646voltage_domain=system.voltage_domain 647 648[system.dvfs_handler] 649type=DVFSHandler 650domains= 651enable=false 652eventq_index=0 653sys_clk_domain=system.clk_domain 654transition_latency=100000000 655 656[system.membus] 657type=CoherentXBar 658clk_domain=system.clk_domain 659eventq_index=0 660forward_latency=4 661frontend_latency=3 662response_latency=2 663snoop_filter=Null 664snoop_response_latency=4 665system=system 666use_default_range=false 667width=16 668master=system.physmem.port 669slave=system.system_port system.cpu.l2cache.mem_side 670 671[system.physmem] 672type=DRAMCtrl 673IDD0=0.075000 674IDD02=0.000000 675IDD2N=0.050000 676IDD2N2=0.000000 677IDD2P0=0.000000 678IDD2P02=0.000000 679IDD2P1=0.000000 680IDD2P12=0.000000 681IDD3N=0.057000 682IDD3N2=0.000000 683IDD3P0=0.000000 684IDD3P02=0.000000 685IDD3P1=0.000000 686IDD3P12=0.000000 687IDD4R=0.187000 688IDD4R2=0.000000 689IDD4W=0.165000 690IDD4W2=0.000000 691IDD5=0.220000 692IDD52=0.000000 693IDD6=0.000000 694IDD62=0.000000 695VDD=1.500000 696VDD2=0.000000 697activation_limit=4 698addr_mapping=RoRaBaCoCh 699bank_groups_per_rank=0 700banks_per_rank=8 701burst_length=8 702channels=1 703clk_domain=system.clk_domain 704conf_table_reported=true 705device_bus_width=8 706device_rowbuffer_size=1024 707device_size=536870912 708devices_per_rank=8 709dll=true 710eventq_index=0 711in_addr_map=true 712max_accesses_per_row=16 713mem_sched_policy=frfcfs 714min_writes_per_switch=16 715null=false 716page_policy=open_adaptive 717range=0:134217727 718ranks_per_channel=2 719read_buffer_size=32 720static_backend_latency=10000 721static_frontend_latency=10000 722tBURST=5000 723tCCD_L=0 724tCK=1250 725tCL=13750 726tCS=2500 727tRAS=35000 728tRCD=13750 729tREFI=7800000 730tRFC=260000 731tRP=13750 732tRRD=6000 733tRRD_L=0 734tRTP=7500 735tRTW=2500 736tWR=15000 737tWTR=7500 738tXAW=30000 739tXP=0 740tXPDLL=0 741tXS=0 742tXSDLL=0 743write_buffer_size=64 744write_high_thresh_perc=85 745write_low_thresh_perc=50 746port=system.membus.master[0] 747 748[system.voltage_domain] 749type=VoltageDomain 750eventq_index=0 751voltage=1.000000 752 753